JP2586307B2 - Charge transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device,
In particular, the present invention relates to a charge transfer device including an output circuit that detects transfer signal charges using one or more source followers.

[0002]

2. Description of the Related Art Conventionally, as an output circuit of a charge transfer device, an FDA (Floating Diffusion Amplifier) amplifier,
Alternatively, an FGA (Floating Gate Amplifier) amplifier is known, but one or more source followers are used in each amplifier. Among them, the FDA amplifier guides a signal charge to a floating diffusion layer provided at the subsequent stage of the charge transfer region and detects a potential change by a source follower. The FGA amplifier places the signal transfer region on the charge transfer region. A gate electrode capacitively coupled to the gate electrode is provided, and a potential change of the gate electrode due to a passing signal charge is detected by a source follower.

Here, of the above two methods, FDA
The amplifier will be described with reference to the drawings. FIG. 3 shows the FD
FIG. 11 is an equivalent circuit diagram of a conventional output circuit using an A amplifier.
In the figure, Cfj is the junction capacitance of the floating diffusion layer, Tr0
Is a reset transistor for resetting the potential of the floating diffusion layer to the reset potential V _RD ;
Driving MOS transistors and load MOS transistors constituting the source follower of the stage, Tr3, Tr4
Is a driving MOS constituting a second-stage source follower
A transistor and a load MOS transistor.

Prior to detecting the amount of transfer signal charge, the potential at point A is reset. Reset operation is carried out by conducting the reset transistor and the reset pulse phi _R to be applied to the gate of the reset transistor Tr0 high. As a result, the potential at the point A, that is, the potential of the floating diffusion layer is set to the reset potential V _RD . Thereafter, the reset pulse phi _R to the low level, to complete the reset operation floating diffusion layer in a floating state. In this state, when signal charges are injected from the charge transfer path into the floating diffusion layer, the potential at point A changes according to the charge amount due to the junction capacitance Cfj of the floating diffusion layer. The potential change is indicated by Vin in FIG. This potential change is
The first stage and the second stage are led to the gate of the S transistor Tr1.
The signal is converted into a low output impedance detection signal Vout by the source follower at the stage and output.

Among the MOS transistors constituting the source follower, the driving transistors Tr1 and T1
r3 is an enhancement type, and the load transistors Tr2 and Tr4 are of a depletion type. The drains of Tr1 and Tr3 are set to the power supply voltage V _DD , and the sources and gates of Tr2 and Tr4 are grounded. In the circuit shown in FIG. 3, the power supply voltage V _DD
Is 15 V, for example, point B is at 10 V, for example, and point C is at 8 V, for example.

FIG. 4 shows the above-mentioned MOS transistor Tr2.
FIG. 5 is a cross-sectional view of a region where Tr4 is formed. As shown in FIG. 1, an n ⁺ -type impurity region 5 serving as a source region and a drain region in a surface region of a p-well layer 2 buried in an n-type semiconductor substrate 1, an n-type impurity region 4 forming a channel, and An n ⁻ -type impurity region 3 is formed. A gate electrode 8 is provided on the channel region via a silicon oxide film 7. This MOS transistor is isolated from other regions by being surrounded by ap ⁺ -type impurity region serving as an element isolation region. A reverse bias is applied between the n-type semiconductor substrate 1 and the p-well layer 2 by the power supply Vsub9.

[0007]

FIG. 5 is a diagram showing the channel potential of the MOS transistor shown in FIG. As shown in the figure, since a high voltage is applied to the drain region, a potential valley is formed deep in the substrate in the channel near the drain, but the channel potential becomes shallower as it approaches the source region at the ground potential. Become. As a result, in the channel closer to the source, carriers flow near the substrate surface, and charges are trapped at the interface trap level existing at the silicon-oxide film interface, thereby generating an interface trap charge e. Therefore, S / N
Are deteriorated, and as shown in FIG. 6, the output load capacitance Ctr caused by the interface trap charge reduces the bandwidth of the output circuit.

In the conventional output circuit described above, the MO
Since the gate potentials of the S transistors Tr2 and Tr4 were fixed to the ground potential, the current of the load transistor could not be adjusted. If the impurity concentration, the gate oxide film, or the gate electrode varied due to process variations, This directly causes variations in the gain and operating speed of the output circuit, making it difficult to achieve uniform characteristics.

[0009]

According to the present invention, a charge transfer region of a second conductivity type is provided in a surface region of a semiconductor layer of a first conductivity type. Is converted into a voltage signal, and the voltage signal is amplified by one or more source followers formed on the first conductivity type semiconductor layer, and the voltage of the source follower is increased. The load resistance is constituted by a depletion type MOS transistor having a source / drain region of the second conductivity type and a channel region, wherein the first conductivity type region is provided on the surface of a portion of the channel region from the source region. A charge transfer device is provided. Preferably, an adjustable bias voltage is applied to a gate electrode of the depletion type MOS transistor.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a load-side MOS transistor of a source follower according to an embodiment of the present invention. In FIG. 1, parts common to those of the conventional example shown in FIG.
Since the same reference numbers are given, duplicate description is omitted, but in the present embodiment, in the channel unit,
A floating p ⁺ -type region 9 is formed on the surface of the n-type impurity region 4 constituting the channel region near the source region, and the gate electrode 8 is formed of a channel region where the p ⁺ -type impurity region 9 is not formed. Only formed on top. A variable voltage power supply Vs is connected to the gate electrode 8 so that the constant current of the source follower can be adjusted.

FIG. 2 is a circuit diagram of an FDA amplifier using this load MOS transistor. As shown in the figure, the load MOS transistor of this embodiment has an equivalent circuit in which depletion type MOS transistors Tr2 and Tr4 are connected to junction type FETs Tr5 and Tr6 whose gates are in a floating state, respectively. It can be represented by the following configuration. In the load transistor configured as described above, even if the channel potential becomes shallow in the region near the source, carriers pass through the inside of the substrate, so that carrier trapping due to the interface trap level at the oxide film interface does not occur. Therefore, the output load capacity does not increase,
The deterioration of the output amplifier band can be prevented. Also,
The reduction in S / N can be suppressed.

Further, since the variable voltage power supply Vs is connected to the gate electrode 8, the constant current of the source follower can be set to a predetermined value. Therefore, it is possible to correct the operating point in each source follower, and it is possible to compensate for variations in characteristics due to process variations.

While the preferred embodiment has been described,
The present invention is not limited to the above embodiments,
Various modifications are possible within the gist of the present invention described in the claims. For example, in the embodiment, the p ⁺ -type impurity region on the channel region of the load transistor is in a floating state, but may be changed to a fixed potential such as a ground potential. Further, the load transistor according to the present invention is not only an FDA amplifier but also a load transistor.
It can be applied in an FGA amplifier. Further, in the embodiment, the source follower having the two-stage configuration has been described, but the output circuit of the present invention is not particularly limited to this number of stages.

[0014]

As described above, the charge transfer device of the present invention provides a load follower MO for a source follower in an output circuit.
Since the channel region near the source of the S transistor is covered with the p ⁺ -type impurity region, the channel current can pass through the substrate separated from the interface trap level. / N
Degradation and bandwidth reduction can be prevented. further,
Since the gate voltage of the load transistor can be adjusted,
Current variations due to process variations can be compensated, and the characteristics of the output circuit can be made uniform.

[Brief description of the drawings]

FIG. 1 shows a load M of an output circuit according to an embodiment of the present invention.
FIG. 14 is a cross-sectional view of an OS transistor.

FIG. 2 is an equivalent circuit diagram of an output circuit according to one embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of a conventional output circuit.

FIG. 4 is a cross-sectional view of a load MOS transistor in a conventional output circuit.

FIG. 5 is a potential diagram for explaining a problem of the conventional example.

FIG. 6 is an equivalent circuit diagram for explaining a problem of the conventional example.

[Explanation of symbols]

Reference Signs List 1 n-type semiconductor substrate 2 p-well layer 3 n ^- type impurity region 4 n-type impurity region 5 n ⁺ -type impurity region 6 p ⁺ -type impurity region 7 silicon oxide film 8 gate electrode 9 p ⁺ -type impurity region

Claims (2)

(57) [Claims] A first conductive type semiconductor layer in a surface region of the first conductive type semiconductor layer;
A charge transfer region of a conductivity type is provided, the signal charge transferred through the charge transfer region is converted into a voltage signal, and the voltage signal is converted into one or more stages formed on the first conductivity type semiconductor layer. In a charge transfer device amplifying by a source follower, a load resistance of the source follower has a source / drain region of a second conductivity type and a channel region of a second conductivity type, and a surface of a portion of the channel region near the source region. A MOS transistor provided with a first conductivity type region. 2. The charge transfer device according to claim 1, wherein an adjustable bias voltage is applied to a gate electrode of said MOS transistor.