JP2583774B2 - High-speed numerical operation device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-speed numerical operation device including a storage unit and an operation unit that performs multiplication and addition operations.

(Prior Art) Conventionally, in a supercomputer that performs an operation by a vector operation method, a large number of buses are connected between an arithmetic unit, a memory, and the like with a configuration as shown in FIG. Had control. In FIG. 4, a main memory 1, a sub-memory 2, a high-speed memory 3 for writing and reading intermediate data and result data are provided, and five buses 4 each have a multiplier 5 and an adder 6. Connected with the output terminal. The input sections A, B, C, and D of the multiplier 5 and the adder 6 are connected to five buses 4 shown in FIG. 1 by switches (not shown). In this configuration, since the five buses 4 have a 32-bit configuration, 160 signal lines are provided, and thus the switches are enormous. Further, a product-sum calculator convenient for use in the cumulative addition operation shown in FIG. 6 is used in the vector operation system computer. 6, the same parts as those in FIG. 5 are denoted by the same reference numerals. This arithmetic unit performs, for example, an operation as shown in equation (1).

A is connected to the A terminal of the multiplier 5, and b _i (i = 1, 2,...,
n) give. Fi _-1 appears at the output E terminal of the adder 6,
It is fed back as an addition data to the D terminal to F _i is determined.

(Problems to be Solved by the Invention) By the way, such a supercomputer requires an extremely large number of buses and associated switches, so that it has been difficult to manufacture an LSI using a printed board. In addition, a multiply-accumulate type computer can perform multiplication and addition operations simultaneously by using a multiplier and an adder separately, despite having a built-in multiplier and an adder as described above. Was inconvenient.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the number of buses required for moving data in and out of each memory, and to perform multiplication and addition not only independently but also independently. It is another object of the present invention to realize a high-speed numerical operation device that can perform the calculation.

(Means for Solving the Problems) The present invention for solving the above problems includes a storage means, a multiplication means for performing a multiplication operation, and an addition means for performing an addition operation. A numerical operation device, comprising at least four connection sections for inputting or outputting data, storing data from the storage means, supplying the data to the multiplication means or addition means, and providing the multiplication means or addition means An intermediate storage unit for exchanging data as a result of the computation, a first connection unit for exchanging data between the storage unit and the intermediate storage unit, and a unit for supplying data from the intermediate storage unit to the multiplication unit. (2) a third connecting means for supplying the data of the intermediate storage means to the adding means; and a data which is a calculation result of the multiplying means and the adding means to the intermediate storing means. A fourth connecting means, a fifth connecting means comprising a chaining buffer for connecting the fourth connecting means to the second and third connecting means, and a memory means for dividing one clock cycle into two. , Causing the intermediate storage means and the fifth connection means to perform two-stage operations during one clock cycle, and causing the first, second, third, and fourth connection means to perform operations in accordance with the two-stage operations. Control means for controlling transmission of two types of data by dividing the data.

(Operation) The control means generates a sequence signal based on the system clock, divides one clock cycle into two, causes the intermediate storage means and the like to perform a two-stage operation, and causes the connection means to be used in a time-sharing manner. Based on this, the multiplication means or the addition means exchanges data via the intermediate storage means or the connection means to perform an accumulation operation or an independent operation.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, 11 is a main memory storing data to be calculated, 12 is a table storing trigonometric functions, exponential functions and other functions, and is a sub-memory for converting input data into respective functions, 13 Temporarily stores the data from the main memory 11 and the sub-memory 12, sends the data to the multiplier 14 and the adder 15 for the operation, stores the intermediate data after the operation, and multiplies to continue the operation. The intermediate data is sent to the adder 14 and the adder 15, and the data of the final operation result
5 is a register file of 5 ports to be transferred to. Reference numeral 16 denotes a microprogram memory for storing horizontal microinstructions and the like, and a sequence signal is generated by a system clock, and the timing of data transfer between the main memory 11, the sub memory 12, the register 13, the multiplier 14, and the adder 15 is performed. The above-mentioned circuits are controlled by a microprogram of the control circuit 16 for each system clock. Reference numeral 17 denotes a chaining buffer for temporarily returning the operation result of the multiplier 14 to the register file 13 and causing the operation result to be input to the multiplier 14 again without delay, and for directly returning the operation result to the input terminal of the multiplier 14. Adder
This is a chaining buffer that performs the same operation as that of the chaining buffer 17 for. An external interface circuit 19 connects the external circuit 20 and the control circuit 16 and exchanges data.

Next, the operation of the embodiment configured as described above will be described with reference to FIG. Horizontal microinstructions are stored in a microprogram memory built in the control circuit 16, and the horizontal microinstructions have, for example, a configuration as shown in FIG. In the figure, 21 stores data and instructions to be given to the main memory 11, and 22 shows sub memories 12, 23.
Indicates a case where register files 13 and 24 store data and instructions to be applied to multipliers 14 and 25 to adder 15, respectively. Commands to be given to each section are arranged in the horizontal direction, and the structure is such that reading and writing can be performed simultaneously at every clock. All circuits are controlled every clock by the horizontal microinstruction and the sequencer.

FIG. 2 is a time chart of the operation of all the circuits. In the figure, (a) is a system clock for controlling all circuits,
(B) is a sequence signal output by the sequencer in the control circuit 16 according to the system clock. (C) is a control signal provided from the control circuit 16 to the register file 13, and for example, one cycle of the sequence signal of (b) is divided into a first half and a second half according to whether the system clock is at a high level or a low level. ing. (D) is an adder
At the operation timing 15, A is given in the first half and B is given in the second half from the register file 13, and the operation of A + B is performed. In the next cycle, AB is calculated, and in the next cycle, BA is calculated. (E)
Is the operation timing of the multiplier 14, and the data of C is given in the first half and the data of D is given in the second half from the register file 13,
D is being calculated. (F) shows the operation timing of the main memory 11 and exchanges a total of two data in the first half and the second half of one clock cycle in one clock cycle. (G) shows the operation timing of the sub memory 12 and (f)
It operates in the same way as.

In FIG. 1, an external interface circuit 19 that has received data and the like from an external circuit 20 writes instruction data and the like to a control circuit 16.

The control circuit 16 gives an instruction written in the microprogram memory to each circuit to control the operation. First, data to be operated is written into the main memory 11, and data to be used in the table of the sub memory 12 is sent to the sub memory 12.
The main memory 11 and the sub memory 12 give data and operation instructions to the register file 13, respectively. At this time, two data can be provided in the first and second half of one clock cycle in one clock cycle. Therefore, the main memory 11 and the register file 13 have one signal line (actually, the number of bits × 1).
And the same amount of data or commands as those connected by the two signal lines can be sent. The register file 13 can provide C and D data to the multiplier 14 and A and B data to the adder 15 in one clock cycle.
Four data are supplied to the arithmetic unit by two signal lines.
The data of the operation results of the multiplier 14 and the adder 15 are returned to the register files, respectively.
14 uses the latter half by the adder 15 to send both data to the register file 13 within one clock. In the case of performing the accumulation operation, as one method of this embodiment, the multiplier 14 receives the data C and the data D and returns the operation result to the register file 13 three clocks later. Also, depending on the program,
Data is immediately returned to the multiplier 14 by the chaining buffer 17 to realize high-speed arithmetic processing. A control signal for determining whether or not to send data to the multiplier 17 is input to a control terminal of the chaining buffer 17 to determine the direction of data. The chaining buffer 18 also works for the adder 15.

Regarding the operation of ΣAi Bi in the multiplier 14 and the adder 15, for example, the case where i = 1, 2,..., 11 is shown in FIG. 4 (for convenience of drawing, FIG. 4 (b) shows steps 11 to 24). Here, each state of the sequence that advances by one clock cycle is referred to as step 1, step 2,..., Step 24. First, in step 1, data (A1, B1) is supplied from the main memory 11 to the register file 13 via the port, and in step 2, the data is supplied to the register file 13 via the port.
Supplied to 14. In steps 3 and 4, the multiplier 14 multiplies the data by two stages, and in step 5 writes this operation (M1) to the register file 13 via the port. Hereinafter, this arithmetic processing is performed by using data (A2, B2),.
Continue for 11, B11). In step 8, the above (A
The multiplication result M1 of (1, B1) and the multiplication result M2 of (A2, B2) are supplied to the adder 15 via the port. In steps 9 and 10, adder 15 performs two-stage addition on this data.
In step 11, the result (FA12) is written to the register file 13 via the port. Hereinafter, such arithmetic processing is continued. That is, in steps 8, 9, and 10, the adder 15 starts addition using the intermediate data of the register file 13. Here, since the adder 15 is a three-stage pipeline, the pipeline is continuously filled in steps 8, 9, and 10. Steps
From 11, the output from the multiplier 14 is chained to the input to the adder 15 by the chaining buffer 18, and the output of the adder 15 is also chained to the input to the adder 15 and added. From step 12, reading from the main memory 11 is stopped, and in step 13, there is no input to the multiplier 14. Then, in step 17, FA956 (= M9 + M5 + M6) + F
A10712 (= M10 + M7 + M1 + M2) is executed, and the result is output in step 20. Therefore, FA11834 (= M11 + M8 +
M3 + M4), and the total addition result (ΣAi Bi) is output to the register file 13 in the three-step step 23. Finally, at step 24, the operation result is written back from the register file 13 to the main memory 11.

In FIG. 1, a line connecting each circuit with a solid line and a broken line indicates that a single line indicates that signals are transmitted and received using the first half of one clock, and a broken line indicates that signals are transmitted and received using the latter half. I have. As can be seen by comparing FIG. 1 of the present embodiment with FIG. 5 of the conventional example, the use of the register file 13 having five ports and the use of one clock cycle in a time-sharing manner This embodiment can greatly reduce the number of signal lines as compared with the conventional example.

As described above, according to the present embodiment, the signal transmission / reception is performed in the first half and the second half of one clock, so that the signal line for transmitting the signal can transmit / receive twice as many signals. Can be halved, and
No switch is required, and the circuit configuration is simplified.

Further, the adder and the multiplier can be simultaneously used as a single adder and a multiplier, respectively, in addition to the operation as the product-sum operation unit.

Also, by using a register file, all intermediate data can be stored in the register file, and the same data can be read out to a plurality of ports at the same time, so that the degree of freedom in software design is increased.

Also, by using a chaining buffer, intermediate data can be directly input to an adder or the like without writing to a register file, so that the arithmetic processing is speeded up.

Note that the present invention is not limited to the present embodiment, and the following modifications are conceivable.

Those that do not have a secondary memory as a table for function conversion.

One that accesses the secondary memory once.

One that accesses the main memory once.

(Effects of the Invention) As described above in detail, according to the present invention, the bus for connecting each memory and the arithmetic unit is reduced, and a switch is not required. It can be performed independently, and the arithmetic processing is accelerated,
The practical effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
FIG. 3 is an explanatory diagram of a configuration of a horizontal microinstruction, and FIG. 4 is a timing chart of the embodiment of i = 1, 2,.
FIG. 5 is a block diagram of a conventional computer, and FIG. 6 is a block diagram of a product-sum calculator. 11: Main memory, 12: Sub memory 13: Register file, 14: Multiplier 15: Adder, 16: Control circuit 19: External interface circuit

Claims (1)

(57) [Claims] 1. A storage means; a multiplication means for performing a multiplication operation;
A high-speed numerical operation device having an addition means for performing an addition operation, wherein at least four connection parts for inputting or outputting data are provided.
An intermediate storage unit for storing data from the storage unit, supplying the data to the multiplication unit or the addition unit, and transmitting and receiving data that is a calculation result by the multiplication unit or the addition unit; A first connection unit that exchanges data with the intermediate storage unit, a second connection unit that supplies the data of the intermediate storage unit to the multiplication unit, and a second connection unit that supplies the data of the intermediate storage unit to the addition unit. Connection means for supplying the data, which is the operation result of the multiplication means and the addition means, to the intermediate storage means; and connecting the fourth connection means to the second and third connection means. A fifth connecting means comprising a chaining buffer connected to the storage means, the intermediate storage means and the fifth connecting means for dividing one clock cycle into two, and performing two-stage operations during one clock cycle; And control means for controlling the first, second, third, and fourth connection means to transmit two types of data in a time-sharing manner in accordance with the two-step operation. A high-speed numerical operation device for performing a vector operation characterized by the following.