JP2579556B2 - Digital / analog converter - Google Patents

Description

The present invention relates to a digital / analog converter suitable for use in digital audio equipment such as a compact disk (CD) player and a digital audio tape (DAT) recorder, and more particularly to a plurality of digital / analog converters ( The present invention relates to a digital / analog conversion device in which an output error at the time of low level output is improved by using a DAC.

[Prior Art] Generally, DACs are manufactured so as to satisfy a nonlinear output error of ± 1/2 LSB or less over the entire output level range. However, DACs such as DACs used in digital audio equipment have high resolution.
For AC, the weight accuracy of the upper bits does not become perfect even by adjustment by laser trimming, and in many cases AC does not satisfy the above output error. Therefore, the upper bit side causing the output error can be further adjusted externally, but this also has various problems such as being easily affected by changes in temperature, humidity, and vibration.

Most of the DACs used in digital audio equipment are configured with unipolar output (unipolar output) DACs for simplification of the circuit configuration. In other words, since the input data indicates an audio signal, the signal is output with one polarity, and the DC offset generated at the output is removed by a coupling capacitor, a DC servo circuit, or the like.

In digital audio equipment, digital data input to the DAC is represented by a 2'S complement code or a binary offset code indicating a bipolar analog signal (positive or negative decimal value). Even when a signal is shown, the upper bit side is in the “1” state.

Therefore, in the case of the above-described DAC, even when digital data indicating a low-level analog signal is input, its output includes an output component on the upper bit side, and as a result, the analog signal is low-level. Despite this, there is a disadvantage that the output error does not decrease.

On the other hand, a digital-to-analog conversion apparatus conventionally constituted by a data shift circuit, a mantissa DAC, an exponential DAC, etc., which is called a floating DAC, an exponential DAC, etc., is disclosed in Japanese Patent Application Laid-Open No. 61-2424.
No. 21 (US Pat. No. 4,727,355) is proposed.

According to this digital / analog converter, the digital data is shifted to the upper bit side in response to the level of the analog signal indicated by the digital data, and D / A converted by the mantissa DAC, so that the output at the time of low level output is obtained. The error can be substantially reduced.

[Problems to be Solved by the Invention] However, since this digital / analog converter employs a two-stage DAC configuration in which the output of the mantissa DAC is connected to the exponential DAC, the switching noise of the exponential DAC is converted into an analog signal. There was a problem that was included.

[Means for Solving the Problems] The present invention is to provide a digital / analog converter in which the output error at the time of low-level output is improved without inviting the above-mentioned problems. Is
N-bit input data is input, and the first to L-th (L ≧ 3)
A digital data conversion circuit that outputs main output data of the first and second main DACs, a first to an L-th main DAC that can perform D / A conversion of the first to the L-th main output data into a first to an L-th analog signal,
The weights of the LSBs of the first to Lth main output data are sequentially increased, and the LSB of the first main output data and the LSB of the input data are increased.
And an analog adder circuit for adding the first to Lth analog signals at a predetermined addition ratio so that the MSB weight relationship between the Lth main output data and the input data overlaps.

The second device of the present invention receives N-bit input data and converts the first to L-th (L ≧ 3) main output data and the one-bit first to (L−1) sub-output data. A digital data conversion circuit for outputting, first to L-th main DACs capable of D / A-converting the first to L-th main output data into first to L-th analog signals; (L-1) first to (L-1) -th sub-output circuits for forming first to (L-1) -th sub-output signals which change in response to the sub-output data; The weight of each LSB of the main output data becomes heavier in order, the weight relationship between the LSB of the first main output data and the LSB of the input data, the weight relationship between the LSB of the Lth main output data and the MSB of the input data, and the first To the (L-1)
The first to L-th analog signals and the first to (L-1) -th sub-output signals are so set that the weights of the L-sub output data of the second to the L-th main output data coincide with each other. And an analog adding circuit for adding at a predetermined addition ratio.

[Operation] According to the first device of the present invention, when the input data changes in a predetermined data range that can be represented by the first main output data, the digital data conversion circuit outputs only the first main DAC. Outputs the first main output data based on the input data so as to be D / A-converted. When the input data changes beyond a predetermined data range, the input data is changed from the first main data to the K-th main DAC ( The first to the K-th main output data are output based on the input data so that K increases in response to the size of the input data and is D / A converted by an integer of 2 or more and L or less. Also the second
1st to 1st in which the weight relationship overlaps with the Kth main output data
The upper bit group of the (K-1) th main output data is fixed to the maximum value.

According to the second device of the present invention, when the digital data conversion circuit changes the predetermined data range that can be represented by the first main output data, the digital data conversion circuit changes the input data to the first main DA data.
First based on input data so that D / A conversion is performed only by C
When the input data changes beyond the predetermined data range, the input data changes from the first main data to the Kth main DAC (where K increases in response to the size of the input data). And an integer of 2 or more and L or less)
The first to Kth main output data are output based on the input data so as to be D / A converted.
The sub-output data of 1) is set to a state of assisting 1 LSB of the second to K-th main output data, and the first to (K-1) -th main outputs having a weight relationship overlapping with the second to K-th main output data. The upper bits of the output data are fixed at the maximum value.

[Embodiment] FIGS. 1 to 4 show a first embodiment of the digital / analog converter of the present invention when applied to a CD player.
This will be described with reference to the drawings.

FIG. 1 shows a block diagram, in which input data of a 20-bit, 2'S complement code output from a digital filter (not shown) is input to input terminals D1 to D20 of a digital data conversion circuit 1, Fig. 2 (A)
As shown in the data conversion table of (D) to (D), in response to the data value,
It is converted into 16-bit first to third main output data and 1-bit first and second sub output data, and output terminals (A1 to A16), (B1 to B16), and (C1 to C16), respectively. , (S1),
Output from (S2).

The first to third main output data output is input to the first to third main DAC2A~2C each resolution 16 bits D / A converted into an analog current I ₁ ~I _3. Note that these D
DAC when the AC2A~2C has DAC of the same circuit configuration is used to align the characteristics, output current I ₁ ~I ₃ of each DAC to main output data indicates a decimal value plus
When a negative decimal value is indicated in the inward direction (the direction of the arrow in the drawing), it flows outward in the DAC.

On the other hand, the first sub-output data is input to the sub output circuit 3A constituted by resistors R ₁ to R _3, the second main DAC2B
Bruno + is converted to the same current I ₄ and a current value corresponding to 1LSB,
Similarly, the second sub output data is input to the sub output circuit 3B having the same circuit configuration as the sub output circuit 3A, and the third main DAC 2
It is converted to the same current I ₅ and the current value corresponding to C of + 1LSB. Note that the sub output circuits 3A and 3B are constituted only by resistors to convert the logic level voltage when the sub output data is in the "1" state to a predetermined current, so that the output Direction of currents I ₄ and I ₅ is DAC2B, 2C
Although the output currents I ₂ and I _{3 have} the opposite directions, the state of the sub output data is inverted with respect to the original state as described later, and a predetermined offset current is output in normal times, and Sometimes the relative currents are matched by stopping the offset current.

The output current I _{1 of the} DAC 2A is I / V converted to a voltage V ₁ with a gain α by an I / V conversion circuit 4A composed of an OP amplifier A ₁ and a resistor R ₁ , and the output current I _{2 of the} DAC 2B is a sub output. Circuit 3A
After being summed with the output current I _4, is I / V converted by the same gain α to the voltage V ₂ by the I / V conversion circuit 4B, also the output current I ₅ of the output current I ₃ of DAC2C sub output circuit 3B after being added to the same gain to the voltage V ₃ by the I / V conversion circuit 4C alpha in I / V
Is converted. Note that these I / V conversion circuits 4A to 4C also have the same circuit configuration so that glitches do not occur in an output signal of an analog addition circuit 5 described later due to characteristic differences such as slew rate and phase characteristics. .

The output voltages V _{1 to} V ₃ of the I / V conversion circuits 4A to 4C are OP
Analog addition is performed at a gain ratio of 1/16: 1/4: 1 by an analog addition circuit 5 including an amplifier A ₂ and resistors R _{5 to} R _9, and an aliasing component accompanying D / A conversion is removed by an LPF 6, sub output circuit 3 by a coupling capacitor C ₁
A, 3B offset output and I / V conversion circuits 4A-4C generated
The DC offset is removed, and the signal is output from the analog output terminal 7 as an analog signal.

Here, the relationship between the bit weights of each data will be described with reference to FIG. 3. In the above embodiment, the main DAC 2
2C are added at a ratio of 1/16: 1/4: 1, the weights of the MSB to LSB of the first main output data match the weights of 5SB to LSB of the input data, respectively. The weights of the MSB to LSB of the second main output data are equal to the weights of 3SB to 18SB of the input data, respectively, and the weights of the MSB to LSB of the third main output data are respectively equal to the weights of the MSB to 16SB of the input data. Will match.

The outputs of the sub output circuits 3A and 3B are the L level of DACs 2B and 2C respectively.
Since it matches the SB output, the weight of the first sub-output data matches the LSB weight of the second main output data, and the weight of the second sub-output data matches the third main output data LS.
It will match the weight of B.

Next, the details of the above-described data conversion tables in FIGS. 2A to 2D will be described. In addition, [] after each data is 10
Indicates a decimal value.

First, the input data of the first sub output data is “100000
… 000000 ”to“ 000001… 111111 ”[−524288 to +32767]
During this time, it is always “1” [+1] and “000010 ... 000000”
During "011111 ... 111111" [+32768 to +524287], it is always "0" [0]. The input data of the second sub-output data is “100000... 000000” to “001001... 111111” [−
524288-+163839], it is always "1" [+1]
"001010 ... 000000" to "011111 ... 111111" [+163840 to +
524287], it is always “0” [0]. The first and second sub-output data are supplied to the sub-output circuit 3 as described above.
In order to match the directions of the output currents of A and 3B with the directions of the output currents of the main DACs 2B and 2C, the states are reversed with respect to the original state.

Next, the input data of the first main output data is “1111”.
10 ... 000000 "to" 000001 ... 111111 "[−32768 to +32767]
During the period "1000 ... 00" to indicate the decimal value indicated by the input data
0 "to" 0111 ... 111 "[-32768 to +32767], and when the input data exceeds" 000010 ... 000000 "[+32768],
The upper 14 bits whose bit weights overlap the second main output data always become "0111 ... 1" indicating the plus maximum value, and the remaining lower 2 bits change to the same state as the lower 2 bits of the input data. And the input data is "111101 ... 111111"
When [−32769] or less, the first main output data becomes “1000... 0” indicating that the upper 14 bits whose bit weights overlap the second main output data always indicate a minus maximum value, and the remaining lower 2 bits are input. It changes to the same state as the lower two bits of the data.

Next, the input data of the second main output data is “1111”.
10 ... 000000 "to" 000010 ... 000011 "[−32768 to +32771]
During this period, the value is always "0000 ... 000" [0], and when the input data is equal to or more than "000010 ... 000100" (+32772), it is increased by 1 every time the input data is increased by 4 as a decimal value. That is, the input data is "000010 ... 000100" to "000010 ... 000111" [+3277
2 to +32775], "0000 ... 001" [+1], "000010 ...
Between "001000" to "000010 ... 001011" [+32776 to +32779], it becomes "0000 ... 010" [+2],.
163839] plus the maximum value “0111… 111” [+32767]
become. Further, if the input data is "001010 ... 000000" [+163
840] or more, the second main output data becomes “0111... 1” in which the upper 14 bits whose bit weights overlap the third main output data always indicate a plus maximum value, and the remaining lower 2 bits
The bits (15SB, LSB) change to the same state as 17SB and 18SB of the input data, respectively.

The input data of the second main output data is “1111”.
When 01 ... 111111 "[−32769] or less, the input data becomes 10
Decrement by 1 every time the decimal value decreases by 4. That is, the input data is "111101 ... 111111" to "111101 ... 111100" [−32769 to −3
2772], "1111 ... 111" [-1], "111101 ... 11101"
"1" to "111101 ... 111000" [-32773 to -32776]
111 ... 110 "[-2],..., And the input data is“ 110 ”
110… 000011 ”to“ 110110… 000000 ”[−163837 to −16384
0], the negative maximum value is “1000… 000” [−32768]. Further, if the input data is “110101... 111111” [−16384
1] or lower, the second main output data becomes 1000... 0 "indicating that the upper 14 bits whose bit weights overlap the third main output data always indicate the minus maximum value, and the remaining lower 2 bits (15SB, LSB) Changes to the same state as 17SB and 18SB of the input data, respectively.

Next, in the third main output data, the input data is “1101”.
10 ... 000000 "to" 001010 ... 001111 "[-163840 to +16385
In the case of [5], it always becomes "00000... 00" [0], and when the input data becomes "001010... 010000" [+163856] or more, it is increased by 1 every time the input data is increased by 16 in decimal value. That is, the input data is "001010 ... 010000" to "001010 ... 011111" [+
163856 to +163871], “00000 ... 01” [+1], “00
1010 ... 100000 "to" 001010 ... 101111 "[+163872 to +1638
87] is “00000... 010” [+2],..., And the input data is “011111... 110000” to “011111.
524272 to +524287] becomes "010101 ... 1" [+22527]. Then, the input data is “110101... 111111” [−163
841], the input data decreases by 1 every time the input data decreases by 16 in decimal. That is, the input data is "110101 ... 11111".
"11111 ... 11" [-1] and "110101 ... 101111" to "110101" between 1 "to" 110101 ... 110000 "[-163841 to -163857]
... 100,000 "[111163 ... 10" between [-163857 to -163872]
[-2],..., And the input data is “100000… 0011”
"101010 ... 0" [-22528] between 11 "and" 100000 ... 000000 "[-524273 to -524288].

As described above, each output data changes to indicate the input data. In particular, when the input data is “000001.
When the first sub output data is increased from “1” to “0” when the data increases from “1111” (+32767) to “000010... 000000” (+32768), the timing at which the second main output data increases by +1 Delay, input data is “000010… 000000”
~ "001001 ... 111111" (+32768 to +163839)
4SB to LSB of the main output data of
Same state as B to 18SB.

Also, the input data is "001001 ... 111111" (+163839)
From "001010 ... 000000" (+163840) to "0" by changing the second sub-output data from "1" to "0",
The timing at which the third main output data increases by one is delayed, and the input data is changed from "001010 ... 000000" to "011111 ... 11111".
At the time of 1 "(+163840 to +524287), 6SB to LSB of the third main output data are set to the same state as 6SB to 16SB of input data, respectively.

According to this, the number of operation bits of a digital addition circuit (described later) required for generating the second and third main output data can be greatly reduced, and the circuit of the digital data conversion circuit 1 can be simplified. Contribute.

Hereinafter, as shown at the right end of the figure, the input data is "0000".
The range where 10 ... 000000 "[+32768] or more is set to UP1," 11111
0 ... 000000 "to" 000001 ... 111111 "[−32768 to +32767]
Is defined as MID1, and a range less than or equal to “111101... 11111” [−32769] is defined as DOWN1. Also, if the input data is "00101
The range of 0 ... 000000 "[+163840] or more is UP2," 11011
0 ... 000000 "to" 001001 ... 111111 "[-163840 to +16383
9] is MID2, “110101 ... 11111” [−163841]
The range below becomes DOWN2.

Next, an example of an internal circuit of the digital data conversion circuit 1 that achieves the data conversion tables of FIGS. 2A to 2D will be described with reference to FIGS. 4A to 4C.

First, a data value detection circuit is configured to detect which range the input data is included in.

Whether the input data is in the UP1 range can be determined by detecting that the MSB is “0” and that all of the 2SB to 5SB are not “0”, as shown in FIG. 4 (B). Input terminal D1 is IN
The input terminals D2 to D5 are respectively connected to one input of the AND11 via V10, and the respective inputs of the INVERT-NAND (hereinafter abbreviated as I-NAND) 12, and the output of the I-NAND12 is connected to the other input of the AND11. It is connected to the. According to this circuit configuration, when the input data is in the range of UP1, the output of AND11 is "1".

Next, whether the input data is in the range of DOWN1 is determined by the MSB
Is "1" and it is sufficient to detect that 2SB to 5SB are not all "1". Therefore, the input terminal D1 is connected to one input of the AND13, and the input terminals D2 to D5 are connected to the respective inputs of the NAND14. Is connected to the other input of AND13. According to this circuit configuration, when the input data is in the range of DOWN1, AND
The output of 13 becomes "1".

And whether the input data is in the range of MID1 is UP
1 and DOWN1, it is sufficient to detect that the output is not in either range. Therefore, the outputs of AND11 and AND13 are INVERT-AND (hereinafter, I
When the input data is in the range of MID1, the output of I-AND 15 is "1".

Whether the input data is in the range of UP2 is determined by the MSB being “0”, 2SB and 3SB not being both “0”, and 2SB to 5SB.
Since it is only necessary to detect that SB is not "0", "1", "0", or "0", respectively, as shown in FIG.
D1 is connected to INV16, input terminals D2 and D3 are connected to respective inputs of I-NAND17, input terminals D2, D4 and D5 are respectively connected to respective inputs of I-NAND18, and input terminal D3 is connected to INV19. I
-Connected to each input of AND18. And INV16, I
-The outputs of NANDs 17 and 18 are connected to the inputs of AND 20, respectively. According to this circuit configuration, when the input data is in the range of UP2, the output of AND20 is "1".

Next, whether the input data is in the range of DOWN2 is determined by the MSB
Is “1”, 2SB and 3SB are not both “1”, and 2SB
5SB are not "1", "0", "1", and "1", respectively. Therefore, the input terminal D1 is used as the input of the AND21, and the input terminals D2 and D3 are used as the inputs of the NAND22. Also, input terminal D2,
D4, D5 and the output of INV19 are respectively connected to respective inputs of NAND23, and outputs of NAND22, 23 are respectively connected to respective inputs of AND21. According to this circuit configuration, when the input data is in the range of DOWN2, the output of AND21 is "1".

And whether the input data is in the range of MID2 is UP
2 and DOWN2, it is sufficient to detect that the output is not in either range, so that the outputs of AND20 and AND21 are connected to the respective inputs of I-AND24, and when the input data is in the range of MID, the output of I-AND24 is It becomes “1”.

The first and second sub output data and the first to third main output data are formed based on the outputs of these data value detection circuits.

As shown in FIGS. 2A to 2D, the first sub output data becomes "1" only when the input data is in a range other than UP1, so that the output (UP1) of AND11 is connected to INV25. Then, the first sub output data is formed (FIG. 4 (B)). Since the second sub-output data becomes "1" only when the input data is in a range other than UP2, the output (UP2) of AND20 is connected to INV26 to form the second sub-output data (No. 4 (A)).

A time lag occurs in data formed by the delay time of each logic circuit, and a glitch occurs in the output of each DAC and the output of the analog addition circuit 5, so that the first and second sub-output data, that is, INV25, The outputs of 26 are latch circuits 27 and 2, respectively.
8 is connected to each data terminal D1 and has a predetermined phase delay with respect to the output clock of the input data.
It is latched based on K, and is output from each of its output terminals Q1, and further from the output terminals S1 and S2 of the digital data conversion circuit 1.

On the other hand, the MSB, 15SB and LSB of the first main output data are the same as those of the input data regardless of the range of the input data.
Since the state becomes the same as MSB, 19SB and LSB respectively, the input terminal
The states of D1, D19 and D20 indicate the MSB, 15SB and LSB of the first main output data, respectively (FIG. 4 (C)).

When the input data is in the range of MID1, the 2SB to 14SB of the first main output data is 6SB to 18SB of the input data.
, And all become "1" when the input data is in the range of UP1, and all become "0" when the input data is in the range of DOWN1.

Therefore, the input terminals D6 to D18 are connected to one input of the ANDs 29 to 41, respectively, and the output (DOWN1) of the AND 13 is connected to the A through the INV 42.
Connected to each other input of ND29-41. Also, AND2
The outputs of 9-41 are connected to one input of OR43-55, respectively, and A
The output (UP1) of ND11 is connected to the other input of each of OR43 to OR55. With the above connection, the outputs of the ORs 43 to 55 indicate the first main output data 2SB to 14SB, respectively.

In order to remove the same time lag as described above, the first main output data, that is, the input terminals D1, the outputs of the ORs 43 to 55, and the input terminals D19 and D20 are connected to the data terminals D to D16 of the latch circuit 56, respectively.
And is latched based on the latch clock LCK,
The output terminals Q1 to Q16 and the output terminals A1 to A16 of the digital data conversion circuit 1 are output.

Next, the MSB of the second main output data is D
Since it becomes "1" only in the range of OWN1, the output state (DOWN1) of AND13 immediately indicates the MSB of the second main output data (FIG. 4 (B)).

Then, 2SB and 3SB of the second main output data are values obtained by subtracting “01” from the data value composed of 4SB and 5SB of the input data when the input data is in the range of UP1, and the input data is in the range of DOWN1. In this case, the value is obtained by adding "01" to the data value composed of 4SB and 5SB of the input data.

Therefore, the input terminals D4 and D5 are respectively connected to the digital addition circuit 57.
The output (UP1) of AND11 is connected to the input terminal B1 of the digital addition circuit 57, and the power supply is connected to the input terminal B2.
It is connected to the. According to this, a digital addition circuit
57 is 4 of input data when input data is in the range of UP1.
Add the data value consisting of SB and 5SB and "11", and if it is outside the range, add the data value consisting of 4SB and 5SB and "01" and output the lower 2 bits from output terminals Q1 and Q2 I do. Note that the value of the lower 2 bits of the result of adding “11” is the same as the value obtained by subtracting “01”.

Further, 2SB and 3SB of the second main output data both become “0” when the input data is in the range of MID1 or DOWN2,
Since both become "1" when it is P2, the digital addition circuit
The output terminals Q1 and Q2 of 57 are connected to one input of AND60 and 61 respectively, and the output of I-AND15 (MID1) and the output of AND21 (DOWN
2) is input to OR58, and connected to the other inputs of AND60 and 61 via INV59. The outputs of the ANDs 60 and 61 are connected to one input of the ORs 75 and 76, respectively, and the output (UP2) of the AND 20 is connected to the other input of the ORs 75 and 76, respectively.
With the above connection, the outputs of ORs 75 and 76 indicate 2SB and 3SB of the second main output data, respectively.

When the input data is in the range of MID2 excluding MID1, the 4SB to 14SB of the second main output data
The state becomes the same as each of 6SB to 16SB, and all become "0" when the input data is in the range of MID1 or DOWN2, and all become "1" when it is UP2.

Therefore, the input terminals D6 to D16 are connected to one input of the ANDs 62 to 72, respectively, and the output of the INV 59 is connected to the other input of each of the ANDs 62 to 72. The outputs of AND62 to 72 are OR77 respectively.
Connected to one input of ~ 87, and the output (UP2) of AND20 is ORed
77-87 are connected to the other inputs. With the above connection, the outputs of OR77 to 87 are each 4S of the second main output data.
B to 14SB are shown.

Further, the 15SB and LSB of the second main output data are both "0" when the input data is in the range of MID1, and otherwise the same state as the 17SB and 18SB of the input data.

Therefore, the input terminals D17 and D18 are connected to one input of the ANDs 73 and 74, respectively, and the output (MID1) of the AND 15 is connected to the other input of each of the ANDs 73 and 74 via the INV88. With the above connection, the outputs of the ANDs 73 and 74 indicate the 15SB and LSB of the second main output data, respectively.

As described above, in order to remove the time lag, the second main output data, that is, the outputs of AND13, OR75 to 87, AND73, and 74 are connected to the data terminals D1 to D16 of the latch circuit 89, respectively.
Latched based on the latch clock LCK and its output terminal Q
1 to Q16, and the output terminal of digital data conversion circuit 1
Output from B1 to B16. Next, since the MSB of the third main output data becomes "1" only when the input data is in the range of DOWN2, the output state (DOWN2) of AND21 immediately indicates the MSB of the third main output data. (FIG. 4 (A)).

Then, 2SB to 5SB of the third main output data is a value obtained by subtracting “0101” from the data value of 2SB to 5SB of the input data when the input data is in the range of UP2. At one time, the value is obtained by adding “0101” to the data value of 2SB to 5SB of the input data.

Therefore, the input terminals D2 to D5 are respectively connected to the digital adder 90.
And the output (UP2) of the AND 20 is connected to the input terminals B1 and B3 of the digital addition circuit 90. The output (UP2) of the AND 20 is connected to the input terminal B2 of the digital addition circuit 90 via the INV 91, and the power supply is connected to the input terminal B4. According to this, when the input data is in the range of UP2, the digital addition circuit 90 adds the data value of 2SB to 5SB of the input data to "1011", and when the input data is in the other range, the digital addition circuit 90 adds 2SB to 5SB. , And "0101" are added, and the lower 4 bits are output to the output terminals Q1 to Q4.
Output from The lower 4 of the result of adding “1011”
The value of the bit is the same as the value obtained by subtracting “0101”.

Further, since the 2SB to 5SB of the third main output data are all "0" when the input data is in the range of MID2, the output terminals Q1 to Q4 of the digital adder circuit 90 are connected to one input of AND92 to 95, respectively. Connected and the output (MID2) of I-AND24 is INV10
7 are connected to the other inputs of the ANDs 92 to 95, respectively.
With the above connection, the outputs of the ANDs 92 to 95 indicate the second main output data 2SB to 5SB, respectively.

The 6SB to LSB of the third main output data is 6SB to 1SB of the input data except when the input data is in the range of MID2.
The state becomes the same as that of 6SB, and all become "0" when the input data is in the range of MID2.

Therefore, the input terminals D6 to D16 are connected to one input of the ANDs 96 to 106, respectively, and the output of the INV 107 is connected to the other input of each of the ANDs 96 to 106. With the above connection, the outputs of the ANDs 96 to 106 indicate the 6SB to LSB of the third main output data, respectively.

As described above, in order to remove the time lag, the third main output data, that is, the respective outputs of AND21 and AND92 to 106 are connected to the data terminals D1 to D16 of the latch circuit 108, respectively, and are latched based on the latch clock LCK. Its output terminals Q1-Q16,
Further, the output terminals C1 to C16 of the digital data conversion circuit 1
Output from

 Next, the operation of the above-described embodiment apparatus will be described.

Operation state First, “111110... 000000” to “00001... 111111” [−327
68 to +32767] will be described.

During this time, the input terminal D1 (first sub-output data) of the latch circuit 27 is always "1" because the output (UP1) of the AND11 is "0" (FIG. 4 (B)). 28 input terminal D1 (second sub output data) is also AND20 output (UP
Since 2) becomes "0", it always becomes "1" (FIG. 4 (A)).

On the other hand, the input terminals D1, D15 and D16 (MSB, 15SB and 16SB of the first main output data) of the latch circuit 56 are connected to the input terminals D1, D19 and D20 of the digital data conversion circuit 1, respectively. The MSB, 19SB, and LSB of the data change to the same state, and the input terminals D2 to D14 (2SB to 14SB of the first main output data) also have the output (DOWN1) of AND13 and the output (UP1) of AND11 both " 0 ", so 6SB of input data
SB18SB (FIG. 4 (C)). For example, when the input data is “000001 ... 111111” [+32767],
The first main output data is "0111 ... 111" [+32767], and when the input data is "111111 ... 111110" [-2],
"1111 ... 110" [-2].

On the other hand, the input terminal D1 (MSB of the second main output data) of the latch circuit 89 is always "0" because it is connected to the output (DOWN1) of AND13, and the input terminals D2 to D14 (the second main output data). Data 2SB-14SB) AND15 output (MID1), AN
The output of D21 (DOWN2) and the output of AND20 (UP2) are "1",
Since they become "0" and "0", they all become "0". Also, input terminal
D15 and D16 also become "0" because the output (MID1) of AND15 becomes "1". That is, during this time, the second main output data is always "0000 ... 000" [0] (FIG. 4 (B)).

The input terminal D1 (MSB of the third main output data) of the latch circuit 108 is always "0" because it is connected to the output (DOWN2) of the AND21, and the input terminals D2 to D16 (the third main output data). The data (2SB to LSB) is also output from the I-AND24 (MID
Since 2) becomes "1", all become "0". That is, during this time,
The third main output data is always “00000... 00” [0] (FIG. 4A).

Each of the above output data is taken into each of the latch circuits based on the rising edge of the latch clock LCK, whereby the time lag between bits and between data is removed, and the data is output from each output terminal of the digital data conversion circuit 1. Most of the time, only the first main output data changes during this time.
Only the time lag between bits in the first main output data will be removed.

The output first main output data is D / A converted into an analog signal (current I ₁ ) by the DAC 2A, and the I / V conversion circuit 4A
I / V conversion to a voltage V ₁ (V ₁ = I ₁ · R ₁ ) (first
Figure). Then, the second main output data is D / A-converted into an analog signal (current I ₂ ) by the DAC 2B, but since the value is always “0000... 000”, the current I ₂ always remains zero. On the other hand, since the first sub output data is always “1”,
Output current I ₄ equivalent to 1 LSB of DAC 2B by sub output circuit 3A
And the voltage V ₂ (V ₂ = −I ₄
・ I / V converted to R ₁ ).

The third main output data is D / A-converted into an analog signal (current I ₃ ) by the DAC 2C, but since the value is always “0000... 000”, the current I ₃ also always remains zero.
Meanwhile, the second sub-output data is always "1", the converted by the sub-output circuit 3B to the output current I ₅ equivalent 1LSB of DAC2C, the voltage V ₃ by the I / V conversion circuit 4C (V ₃ = -I ₅・ R ₁ )
I / V conversion. These output voltages V _{1 to} V ₃ are added at a ratio of 1/16: 1/4: 1 by the analog adder circuit 5, and the added voltage V ₄ is filtered by the LPF 6 to remove the aliasing component associated with the D / A conversion. coupling capacitors C ₁ by the sub-output circuit 3A, 3B, DC offset generated in the I / V conversion circuit 4A~4C are removed, the result, only the output component of the first main output DAC2A is output from the analog output terminal 7 .

Thus, "111110 ... 000000" to "000001 ... 111111"
While the input data within [−32768 to +32767] is being input, the input data is substantially subjected to D / A conversion only by the first main DAC 2A, so that the analog signal output from the analog output terminal 7 is output. Is determined only by the output error of the DAC 2A.

That is, if the DAC 2A performs D / A conversion of the 16-bit data with an output error of ± 1/2 LSB (16-bit accuracy), the output error included in the analog signal is also ± 1/2 LSB.
D / A similar to DAC with both resolution and accuracy of 20 bits
Conversion can be performed.

When the output error is less than ± 2 ^-m LSB
D / A conversion is called (n + m-1) bit precision.

Operating state Next, "000010 ... 000000" to "001001 ... 111111" [+32
[768 to +163839] will be described.

During this time, the input terminal D1 (first sub-output data) of the latch circuit 27 is always "0" because the output (UP1) of the AND11 is "1". "1" because the output (UP2) of AND20 is "0"
Remains.

On the other hand, the input terminals D1, D15 and D16 (MSB, 15SB and 16SB of the first main output data) of the latch circuit 56 are connected to the input terminals D1, D19 and D20 of the digital data conversion circuit 1, respectively. The data MSB, 19SB, and LSB change to the same state, but the input terminals D2 to D14 (2SB to 14SB of the first main output data) output the output of AND13 (DOWN1) and the output of AND11 (UP1) to "0", respectively. "," 1 ", so that all become" 1 ". That is, during this time, the upper 14 bits of the first main output data have the plus maximum value "0111 ... 1", and only the lower 2 bits change state in response to the lower 2 bits of the input data.

On the other hand, the input terminal D1 (MSB of the second main output data) of the latch circuit 89 remains "0" because it is connected to the output (DOWN1) of the I-AND13, but the input terminals D2 to D14 (the 2 main output data 2SB to 14SB) is AND15 output (MI
D1), the output of AND21 (DOWN2), and the output of AND20 (UP2) all become "0", and the state changes in response to the output terminals Q1, Q2 of the digital adder circuit 57 and 6SB to 16SB of the input data, respectively. . Here, the digital addition circuit 57 outputs the output (U
Since P1) is "1", the lower two bits of the value obtained by adding "11" to the data value composed of 4SB and 5SB of the input data are output from the output terminals Q1 and Q2. The input terminals D15 and D16 of the latch circuit 89 change their states in response to the input data 17SB and 18SB, respectively, because the output (MID1) of the I-AND 15 is "0".

The input terminal D1 (MSB of the third main output data) of the latch circuit 108 is always "0" because it is connected to the output (DOWN2) of the AND21, and the input terminals D2 to D16 (the third main output data). The data (2SB to LSB) is also output from the I-AND24 (MID
Since 2) becomes "1", all become "0". That is, during this time, the third main output data is always “00000... 00” [0].

Each of the output data described above is a latch clock LC.
By being taken into each latch circuit based on the rise of K, a time lag between bits and between data is removed, and the data is output from each output terminal of the digital data conversion circuit 1.

The output first main output data is D / A converted into an analog signal (current I ₁ ) by the DAC 2A, and the I / V conversion circuit 4A
I / V conversion to a voltage V ₁ (V ₁ = I ₁ · R ₁ ).

The second main output data is D / A converted into an analog signal (current I ₂ ) by the DAC 2B, but the first sub output data becomes “0”, so that the output current I _{4 of the} sub output circuit 3A is output.
Is also zero, and the current I ₂ is converted to the voltage V ₂ by the I / V conversion circuit 4B.
(V ₂ = I ₂ · R ₁ ). Note that by current I ₄ becomes zero, the output current I ₂ of DAC2B relatively +1
This means that the LSB (this LSB is the LSB of DAC2B) has risen considerably.

The third main output data is D / A-converted into an analog signal (current I ₃ ) by DAC 2, and its value is always “0”.
000 ... 000 ", the remains always be current I ₃ zero. On the other hand, the second sub-output data is always" 1 ", the converted by the sub-output circuit 3B to the output current I ₅ equivalent 1LSB of DAC2C, The voltage V ₃ (V ₃ = −I ₅ · R ₁ ) is converted to I
/ V converted. These output voltages V _{1 to} V ₃ are added at a ratio of 1/16: 1/4: 1 by the analog adding circuit 5, and the added voltage
V ₄ is removed aliasing component due to D / A conversion by the LPF 6, the sub-output circuit 3 by a coupling capacitor C ₁
B, DC offset generated in the I / V conversion circuits 4A to 4C is removed, and output from the analog output terminal 7.

Thus, "000010 ... 000000" to "001001 ... 111111"
While the input data within [+32768 to +163839] is being input, the input data is output from the analog output terminal 7 because the D / A conversion is substantially achieved by the main DACs 2A and 2B and the sub output circuit 3A. The output error of the analog signal is also determined by the output errors of the DACs 2A and 2B and the sub output circuit 3A. Note that the output error of the sub output circuit 3A is usually small, and can be substantially ignored.

That is, if the DACs 2A and 2B convert 16-bit data with an output error of ± 1/2 LSB (16-bit accuracy), the output error included in the analog signal is ± 2.5 LSB.
Thus, D / A conversion similar to a DAC having a resolution of 20 bits and an accuracy of about 18 bits can be performed.

Operating state Next, "001010 ... 000000" to "011111 ... 111111" [+16
3840 to +524287] will be described.

During this time, the input terminal D1 (first sub-output data) of the latch circuit 27 is always “0” because the output (UP1) of the AND11 is “1”, and the input terminal D1 (second The sub-output data of the AND 20 is always “0” because the output (UP2) of the AND 20 is “1”.

On the other hand, the input terminals D1, D15, and D16 (MSB, 15SB, and 16SB of the first main output data) of the latch path 56 are connected to the input terminals D1, D19, and D20 of the digital data conversion circuit 1, respectively. The data MSB, 19SB, and LSB change to the same state, but the input terminals D2 to D14 (2SB to 14SB of the first main output data) output the output of AND13 (DOWN1) and the output of AND11 (UP1) to "0", respectively. "," 1 ", so that all become" 1 ". That is, during this time, the upper 14 bits of the first main output data have the plus maximum value “0111.
Only the bits change state in response to the lower two bits of the input data.

On the other hand, the input terminal D1 (MSB of the second main output data) of the latch circuit 89 is "0" because it is connected to the output (DOWN1) of the AND13, but the input terminals D2 to D14 (the second main output data). 2SB to 14SB of data) are the output (MID1) of I-AND15,
Since the output (DOWN2) of AND21 and the output (UP2) of AND20 become "0", "0", and "1", respectively, they all become "1". However, the input terminals D15 and D16 of the latch circuit 89 are I-AN
Since the output (MID1) of D15 is "0", each of the input data 17S
State changes in response to B and 18SB. That is, during this period, the upper 14 bits of the second main output data become the plus maximum value “0111... 1” similarly to the first main output data, and only the lower 2 bits respond to the lower 2 bits of the input data. And change state.

On the other hand, the input terminal D1 (MSB of the third main output data) of the latch circuit 108 is always "0" because it is connected to the output (DOWN2) of the AND21, but the input terminals D2 to D16 (the third main output data). The output data (2SB to LSB) is the output of the I-AND24 (MID
Since 2) becomes "0", the state changes in response to the output terminals Q1 to Q4 of the digital adder circuit 90 and the input data 6SB to 16SB, respectively. Here, since the output (UP2) of the AND20 is "1", the digital addition circuit 90 outputs the lower 4 bits of the value obtained by adding "1011" to the data value consisting of 2SB to 5SB of the input data to its output terminal Q1. Output from ~ Q4.

Each of the output data described above is a latch clock LC.
By being taken into each latch circuit based on the rise of K, a time lag between bits and between data is removed, and the data is output from each output terminal of the digital data conversion circuit 1.

The output first main output data is D / A converted into an analog signal (current I ₁ ) by the DAC 2A, and the I / V conversion circuit 4A
I / V conversion to a voltage V ₁ (V ₁ = I ₁ · R ₁ ).

The second main output data is D / A converted to an analog signal (current I ₂ ) by the DAC 2B, and I / V converted to a voltage V ₂ (V ₂ = I ₂ · R ₁ ) by the I / V conversion circuit 4B. Is done. Note that by the output current I ₄ of the sub-output circuit 3A becomes zero,
DAC2B output current I ₂ is relatively + 1LSB (this LSB is DAC2B
The LSB).

Then, the third main output data is D / A converted into an analog signal (current I ₃ ) by the DAC 2C, but the second sub output data becomes “0”, so the output current of the sub output circuit 3B
I ₅ also becomes zero, and the voltage V ₃ (V ₃ = I ₃
I / V conversion to ₃ · R ₁ ). Note that by the current I ₅ becomes zero, the output current I ₃ of DAC2C becomes relatively + 1LSB (this LSB is the LSB of DAC2) that corresponds elevated. The output voltages V _{1 to} V ₃ are added at a ratio of 1/16: 1/4: 1 by the analog adder circuit 5, and the added voltage V ₄ is subjected to LPF 6 to remove aliasing components accompanying D / A conversion. , DC offset generated in the I / V conversion circuit 4A~4C by the coupling capacitor C ₁ is removed, output from the analog output terminal 7.

Thus, "001010 ... 000000" to "011111 ... 111111"
While the input data in [+163840 to +524287] is being input, the input data is output from the analog output terminal 7 because D / A conversion is substantially achieved by the main DACs 2A to 2C and the sub output circuits 3A and 3B. The output error of the analog signal is also determined by the output errors of the DACs 2A to 2C and the sub output circuits 3A and 3B. Note that the output errors of the sub output circuits 3A and 3B are usually small and can be substantially ignored.

That is, if the DACs 2A to 2C convert 16-bit data with an output error of ± 1/2 LSB, the output error included in the analog signal becomes ± 10.5 LSB and the resolution 2
It can perform D / A conversion similar to DAC with 0 bits and precision of about 16 bits.

Operating state Next, "111101 ... 111111" to "110110 ... 000000" [-32
769 to -163840] will be described.

During this time, the input terminal D1 (first sub-output data) of the latch circuit 27 is always “1” because the output (UP1) of the AND11 is “0”, and the input terminal D1 (second sub-data) of the latch circuit 28 is The sub output data of the AND 20 also remains “1” because the output (UP2) of the AND 20 becomes “0”.

On the other hand, the input terminals D1, D15 and D16 (MSB, 15SB and 16SB of the first main output data) of the latch circuit 56 are connected to the input terminals D1, D19 and D20 of the digital data conversion circuit 1, respectively. The data MSB, 19SB, and LSB change to the same state, but the input terminals D2 to D14 (2SB to 14SB of the first main output data) output the output of the AND13 (DOWN1) and the output of the AND11 (UP1) to "1", respectively. "," 0 ", so that they all become" 0 ". That is, during this period, the upper 14 bits of the first main output data have a minus maximum value of “1000...
Only the bits change state in response to the lower two bits of the input data.

On the other hand, the input terminal D1 (MSB of the second main output data) of the latch circuit 89 is always "1" because it is connected to the output (DOWN1) of the AND13, and the input terminals D2 to D14 (the second main output 2SB to 14SB of data) is the output of AND15 (MID1), AN
Since the output of D21 (DOWN2) and the output of AND20 (UP2) are all "0", the output terminals Q1, Q
2. The state changes in response to 6SB to 16SB of input data. Here, since the output (UP1) of AND11 is "0", the digital addition circuit 57 outputs the lower two bits of the value obtained by adding "01" to the data value composed of 4SB and 5SB of the input data to its output terminal Q1. , Output from Q2. Also, the input terminal of the latch circuit 89
Since the output (MID1) of AND15 is "0", the states of D15 and D16 change in response to the input data 17SB and 18SB, respectively.

The input terminal D1 (MSB of the third main output data) of the latch circuit 108 is always "0" because it is connected to the output (DOWN2) of the AND21, and the input terminals D2 to D16 (the third main output data). The data (2SB to LSB) is also output from the I-AND24 (MID
Since 2) becomes "1", all become "0". That is, during this time, the third main output data is always “00000... 00” [0].

Each of the output data described above is a latch clock LC.
By being taken into each latch circuit based on the rise of K, a time lag between bits and between data is removed, and the data is output from each output terminal of the digital data conversion circuit 1.

The output first main output data is D / A converted into an analog signal (current I ₁ ) by the DAC 2A, and the I / V conversion circuit 4A
I / V conversion to a voltage V ₁ (V ₁ = I ₁ · R ₁ ).

Further, the second main output data is D / A converted into an analog signal (current I ₂ ) by the DAC 2B, and the first sub output data is always “1”.
It is converted to 1LSB corresponding output current I ₄ of B. The output currents I ₂ and I ₄ are converted to a voltage V ₂ (V ₂ = R ₂₎ by the I / V conversion circuit 4B.
₁ (I ₂ −I ₄ )).

Further, the third main output data is D / A converted into an analog signal (current I ₃ ) by the DAC 2C, but since the value is always “0000... 000”, the current I ₃ always remains zero. On the other hand, since the second sub output data is always “1”, the output current I ₅ equivalent to 1 LSB of the DAC 2C is output by the sub output circuit 3B.
And the voltage V ₃ (V ₃ = −I ₅
・ I / V converted to R ₁ ).

These output voltages V _{1 to} V ₃ are output by the analog adding circuit 5.
The added voltage V ₄ is added at a ratio of 1/16: 1/4: 1, the aliasing component accompanying the D / A conversion is removed by the LPF 6 by the LPF ₆ , and the sub output circuits 3A, 3B, I / The DC offset generated in the V conversion circuits 4A to 4C is removed and output from the analog output terminal 7. Thus, "111101
... 111111 "to" 110110 ... 000000 "[-32769 to -163840]
While the input data is being input, the input data is substantially subjected to D / A conversion by the main DACs 2A and 2B, so that the output error of the analog signal output from the analog output terminal 7 is also reduced by these DACs 2A and 2B. Is determined by the output error of

That is, if the DACs 2A and 2B convert 16-bit data with an output error of ± 1/2 LSB (16-bit accuracy), the output error included in the analog signal is ± 2.5 LSB.
Thus, D / A conversion similar to a DAC having a resolution of 20 bits and an accuracy of about 18 bits can be performed.

Operating state Next, "110101 ... 111111" to "100000 ... 000000" [−16
3841 to -524288] while the input data is being input.

During this time, the input terminal D1 (first sub-output data) of the latch circuit 27 is always “1” because the output (UP1) of the AND11 is “0”, and the input terminal D1 (second sub-data) of the latch circuit 28 is The sub output data of the AND 20 also remains “1” because the output (UP2) of the AND 20 becomes “0”.

On the other hand, the input terminals D1, D15 and D16 (MSB, 15SB and 16SB of the first main output data) of the latch circuit 56 are connected to the input terminals D1, D19 and D20 of the digital data conversion circuit 1, respectively. The data MSB, 19SB, and LSB change to the same state, but the input terminals D2 to D14 (2SB to 14SB of the first main output data) output the output of the AND13 (DOWN1) and the output of the AND11 (UP1) to "1", respectively. "," 0 ", so that they all become" 0 ". That is, during this period, the upper 14 bits of the first main output data have the minus maximum value “1000...
Only the bits change state in response to the lower two bits of the input data.

On the other hand, the input terminal D1 (MSB of the second main output data) of the latch circuit 89 is always "1" because it is connected to the output (DOWN1) of the AND13, and the input terminals D2 to D14 (the second main output The data (2SB to 14SB) is the output of the I-AND15 (MID
1) Since the output of AND21 (DOWN2) and the output of AND20 (UP2) are "0", "1" and "0", respectively, they are all "0", but the input terminals D15 and D16 are the outputs of AND15. (MID1) is “0”,
The state changes in response to input data 17SB and 18SB, respectively.
That is, during this time, the second main output data also becomes the first main output data.
As in the case of the main output data, the upper 14 bits have a minus maximum value "1000... 0", and only the lower 2 bits change state in response to the input data 17SB and 18SB.

On the other hand, the input terminal D1 (MSB of the third main output data) of the latch circuit 108 is always "1" because it is connected to the output (DOWN2) of the AND21, but the input terminals D2 to D16 (the third main output data). The output data (2SB to LSB) is the output of the I-AND24 (MID
Since 2) becomes "0", the state changes in response to the output terminals Q1 to Q4 of the digital adder circuit 90 and the input data 6SB to 16SB, respectively. Here, since the output (UP2) of AND20 is "0", the digital adder circuit 90 outputs the lower 4 bits of the value obtained by adding "0101" to the data value of 2SB to 5SB of the input data to its output terminal Q1. Output from ~ Q4.

Each of the output data described above is a latch clock LC.
By being taken into each latch circuit based on the rise of K, a time lag between bits and between data is removed, and the data is output from each output terminal of the digital data conversion circuit 1.

The output first main output data is D / A converted into an analog signal (current I ₁ ) by the DAC 2A, and the I / V conversion circuit 4A
I / V conversion to a voltage V ₁ (V ₁ = I ₁ · R ₁ ).

Further, the second main output data is D / A converted into an analog signal (current I ₂ ) by the DAC 2B, and the first sub output data is always “1”.
It is converted to 1LSB corresponding output current I ₄ of B. The output currents I ₂ and I ₄ are converted to a voltage V ₂ (V ₂ = R ₂₎ by the I / V conversion circuit 4B.
₁ (I ₂ −I ₄ )).

Then, the third main output data is D / A converted into an analog signal (current I ₃ ) by the DAC 2C, and the second sub output data is always “1”.
It is converted to 1LSB corresponding output current I ₅ of C2C. Then, the output currents I ₃ and I ₅ are converted to a voltage V ₃ (V ₃
= R ₁ (I ₃ −I ₅ )).

These output voltages V _{1 to} V ₃ are output by the analog adding circuit 5.
1/16: 1/4: 1 is added, the added voltage V ₄ is filtered by the LPF 6 to remove aliasing components associated with D / A conversion, and the coupling capacitor C ₁ causes the sub-output circuits 3A, 3B and I /
DC offset generated in V conversion circuits 4A to 4C is removed,
Output from the analog output terminal 7.

Thus, "110101 ... 111111" to "100000 ... 000000"
While the input data in [−163841 to −524288] is being input, the input data is substantially D by the main DACs 2A to 2C.
Since the / A conversion is achieved, the output error of the analog signal output from the analog output terminal 7 is also determined by the output errors of the DACs 2A to 2C.

That is, if the DACs 2A to 2C convert 16-bit data with an output error of ± 1/2 LSB, the output error included in the analog signal becomes ± 10.5 LSB and the resolution 2
D / A conversion similar to DAC with 0-bit precision of approximately 16 bits can be performed.

As described above, according to the embodiment, the main DAC is additionally used in response to the increase of the input data in the positive or negative direction, and the D / A conversion of the input data is achieved. Can perform D / A conversion only with approximately 16-bit accuracy. However, the accuracy improves as the output level becomes low, and the input data of approximately -12 dB or less (2 bits dropped) has 18-bit accuracy. -24dB or less (4 bits dropped)
D / A conversion can be performed with approximately 20-bit accuracy for the input data of.

Further, according to the above-described embodiment, the first main output data has the upper 14 bits whose bit weight overlaps with the second main output data plus the maximum value “0111...
1 "in the operation state, the negative maximum value becomes" 1000 ... 0 ", and the upper 14 bits of the second main output data having the same bit weight as the third main output data have the positive maximum value" 0111 "in the operation state. … 1 ”, the negative maximum value becomes“ 1000… 0 ”in the operating state.Thus, even when the outputs of two or more main output DACs simultaneously change in response to a change in the input data, the change direction is the same. Becomes
For example, conversion operation timing deviation between main DAC and I / V
Even if there is a slew rate or phase characteristic deviation between the conversion circuits, spike-like glitch noise does not occur in the analog signal output from the analog output terminal.

The device of the present invention can take various aspects without being limited to the above-described embodiment.

For example, according to the above embodiment, the operation state and the first
Are changed in state according to the lower bits of the corresponding input data, and the lower two bits of the first main output data and the lower two bits of the second main output data are changed at the time of the operation state. Although the state is changed in accordance with the lower bits of the corresponding input data, the change in state of these lower bits may be stopped because it has little significance in terms of accuracy.

That is, the input data is equal to or more than "000010 ... 000000" [+32768] or equal to or less than "111101 ... 111111" [-32769] (other than MID1).
, The lower two bits of the first main output data are both set to "0", and "001010 ... 000000" [+163840] or more or "110101 ... 111111" [-163841] or less (other than MID2)
, The lower 4 bits of the first main output data and the lower 2 bits of the second main output data are all "0".
Then, the first sub output data is set to "1".

In this case, the digital data conversion circuit 1 shown in FIGS. 4 (A) to (C) may be changed in circuit as shown in FIGS. 5 (A) to (C), respectively. FIG. 4 (A)
The same parts as in (C) are assigned the same numbers and their detailed explanations are omitted.

Explaining the difference on the circuit, the lower two bits (15SB, LSB) of the first main output data are both "0" in the range other than MID1, so that the input terminals D19, D20 of the digital data conversion circuit 1 Are connected to one input of AND 200 and 201, respectively, and the output (MID1) of I-AND 15 is ANDed via INV 202.
The outputs of the ANDs 200 and 201 are connected to the input terminals D15 and D16 of the latch circuit 56, respectively. Therefore, when the input data exceeds the range of MID1, the operation of the lower two bits of the first main DAC 2A, which is smaller than the output error, stops.

13SB and 14SB of the first main output data are
Since both become "0" in the range other than D2, the outputs of AND54 and 55 are connected to one input of AND203 and 204, respectively, and INV10
The output of 7 is connected to the other input of each of AND203 and 204, and AND2
The outputs of 03 and 204 are input terminals D13 and D14 of latch circuit 56, respectively.
Connected to.

The lower 2 bits (15S) of the second main output data
B, LSB) are both "0" in a range other than MID2, so that the output (MID1) of I-AND15 is connected to one input of OR205, and the output of INV107 is connected to the other input of OR205. , OR205 are connected to INV88.

Then, the first sub-output data further becomes "1" in a range other than MID2, so that the output of INV25 is connected to one input of OR206, the output of INV107 is connected to the other input of OR206, and OR206 Is connected to the input terminal D1 of the latch circuit 27. Therefore, when the input data exceeds the range of MID2, the operation of the lower two bits of the first main DAC 2A and the lower two bits of the second main DAC 2B, which is equal to or less than the output error, stops.

In the above embodiment, the first and second sub-output circuits 3A and 3B are provided to simplify the circuit configuration of the digital data conversion circuit 1 (in particular, to reduce the number of operation bits of the digital addition circuit). However, the present invention can be realized without providing these sub output circuits. In this case, the input data of the second main output data is “000010.
If it exceeds 000000 "[+ 32768], the input data increases by 1 every time the decimal value increases by 4. In other words, the input data becomes" 000010 ... 000000 "to" 000010 ... 000011 "[+3276].
8 to +32771], “0000… 001” [+1], “000010…
000100 "to" 000010 ... 000111 "[+32772 to +32775] is" 0000 ... 010 "[+2], ..., and the input data is" 001001 ... 111000 "to" 001001 ... 111011 "[+163832 to +
163835] plus the maximum value “0111… 111” [+32767]
become. Further, when the input data of the second main output data becomes “001001... 111100” [+163836] or more, the upper 12 bits whose bit weight overlaps with the third main output data always indicate the plus maximum value “0111. And the remaining lower 2
Bits (15SB, LSB) are “01”, “10”, and “10”, respectively, when 17SB and 18SB of the input data are “00”, “01”, “10”, and “11”, respectively.
It changes to “11” and “00”.

In the third main output data, the input data is “0010”.
If the input data becomes 01… 111100 ”[+163836] or more, the input data becomes 1
Increment by 1 for every 16 increase in 0-base value. That is, the input data is "001001 ... 111100" to "001010 ... 001011" [+ 163836-
+163851], "00000 ... 01" [+1], "001010 ... 00
Between "1100" and "001010 ... 011011" [+163852 to +163867], "00000 ... 010" [+2], ..., "011111 ... 101100"
"011111 ... 111011" [+524268 to +524283]
10101… 1 ”[+22527], and the input data is“ 011111…
.. 111111 "[+524284 to +524287] and becomes" 010110 ... 0 "[+22528].

Also, when used in a CD player as in the above embodiment,
When the input data represents an audio signal and the analog signal to be output does not require a DC component, the input data must be within a range that does not overflow the third main output data (in the above embodiment, "110110 ... 0" to "001010 ... 0"). Any offset data within the range can be added. Incidentally, due to the fact that by adding the offset data to the third main output data, since the DC offset generated at the output of the third main DAC2C is removed by a coupling capacitor C _1,
There is no problem in operation. Although the input data and each main output data are represented by the 2'S complement code, they may be binary offset codes, and the input data and the main output data are always represented by the same code. It is not limited to that. Furthermore, DAC
, Each output data can take a state inversion.

Further, the digital data conversion circuit 1 is mainly constituted by a theoretical circuit. However, the digital data conversion circuit 1 is constituted by a ROM which stores input data as addresses and stores and outputs each output data.
Or a digital signal processor (DSP). This type of configuration would compensate for the disadvantages of not providing a sub-output circuit.

Further, DAC bipolar output may be either unipolar output, since in the case of using the DAC for bipolar output the amount of DC offset generated is also insignificant, omissions coupling capacitor C ₁ It is possible. Further, the coupling capacitor can be changed to a DC servo circuit or the like.

In the above embodiment, a parallel input DAC is used for the sake of simplicity. However, a serial input DAC may be used. In this case, the digital data conversion circuit 1 outputs the main output data. And outputs the sub-output data at the timing synchronized with the conversion clock of the main DAC.

In addition, the sub-output circuit can be changed in circuit such as a constant current circuit and a switching circuit in order to improve the output accuracy.

Further, the analog circuit section including the I / V conversion circuit and the analog addition circuit, which adds the output of each main DAC and the output of the sub output circuit, is not limited to the circuit of the above-described embodiment. If the addition is performed so that the LSB weight output of each output data becomes the same, any change may be made.

Lastly, in the above embodiment, three main DACs and two sub-output circuits are used, but the number is not limited, and input data and the number of bits of the main DAC are considered. Various modifications are possible. When a sub output circuit is provided, the number of used sub output circuits is the first main DAC.
In terms of assisting the 1 LSB output of the main DAC except for the above, it will be one less than the number of main DACs.

[Effects of the Invention] As described above, according to the apparatus of the present invention, D / A conversion can be performed on input data representing a low level with high accuracy while achieving high resolution. When used in equipment, distortion at low levels that are important for hearing can be improved, and high sound quality can be obtained.

In particular, according to the first apparatus of the present invention, when the input data changes beyond the predetermined data range, the first to (K-1) th main data whose weight relations overlap with the second to Kth main output data. Since the upper bits of the output data are fixed at the maximum value,
Even if the input data changes from within the predetermined data range to outside the predetermined data range, even if the output change characteristics of the first to Kth DACs differ, pulse-like glitch noise does not occur in the output of the analog addition circuit.

Furthermore, according to the second device of the present invention, the first to (L) bits of one bit overlapping the LSB of the second to Lth main output data
-1) The sub output data is provided, and when the input data changes beyond the predetermined data range, these sub output data are set to the state of assisting 1 LSB of the first to (L-1) th main DACs. The lower-order bit group of the second to L-th main output data becomes the same state as the corresponding bit group of the input data,
As a result, the number of calculation bits of the digital adder required to generate the second to L-th main output data is reduced, and the cost is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the apparatus of the present invention, and FIG.
3A to 3D are data conversion tables performed by the digital data conversion circuit 1, and FIG. 3 is a bit weight relationship between input data, first to third main output data, and first and second sub output data. 4 (A) to 4 (C) show an example of the digital data conversion circuit 1, and FIGS. 5 (A) to 5 (C) show another example of the digital data conversion circuit 1. FIG. BRIEF DESCRIPTION OF SYMBOLS 1 ... Digital data conversion circuit, 2A ... First main
DAC, 2B ... second main DAC, 2C ... third main DA
C, 3A... First sub output circuit, 3B... Second sub output circuit, 4A to 4C... I / V conversion circuit, 5.

Claims (2)

(57) [Claims] A digital data conversion circuit for inputting N-bit input data and outputting first to L-th (L ≧ 3) main output data; To the first to L-th main DACs that can be D / A-converted to the L-th analog signal; and the LSB weights of the first to L-th main output data are sequentially increased. The first to L-th analog signals are added at a predetermined addition ratio so that the weight relationship between the LSB and the LSB of the input data and the weight relationship between the L-th main output data and the MSB of the input data overlap. The digital data conversion circuit, when the input data changes in a predetermined data range that can be represented by the first main output data, the digital data conversion circuit converts the input data to the first main DAC. D / A change only by Outputting the first main output data based on the input data so that the input data changes from the first main data to the K-th data when the input data changes beyond the predetermined data range.
(Where K increases in response to the size of the input data, and is D / A converted by an integer greater than or equal to 2 and less than or equal to L) based on the input data. And the upper bits of the first to (K-1) th main output data having a weight relationship overlapping with the second to Kth main output data are fixed to the maximum value. A digital / analog conversion device characterized by the above-mentioned. 2. A digital circuit which receives N-bit input data and outputs first to L-th (L ≧ 3) main output data and 1-bit first to (L−1) -th sub-output data. A data conversion circuit, and first to L-th main DACs capable of D / A-converting the first to L-th main output data into first to L-th analog signals
And first to (L-1) th sub-outputs forming first to (L-1) th sub-output signals that change in response to the first to (L-1) th sub-output data. Circuit, the weight of each LSB of the first to Lth main output data sequentially increases, and the weight relationship between the LSB of the first main output data and the LSB of the input data; The weight relationship of the MSB of the input data and the weight of the first to (L-1) -th sub-output data are set so that the weight relationship of the LSB of the second to the L-th main output data respectively matches. The digital data conversion circuit includes an analog addition circuit that adds the first to Lth analog signals and the first to (L−1) th sub-output signals at a predetermined addition ratio. When changing the predetermined data range that can be represented by the main output data, Outputting the first main output data based on the input data so that the input data is D / A-converted by only the first main DAC; and when the input data changes beyond the predetermined data range, The input data is the K-th data from the first main data.
(Where K increases in response to the size of the input data, and is D / A converted by an integer greater than or equal to 2 and less than or equal to L) based on the input data. Of the first to (K)
-1) The sub-output data is set to a state of assisting 1 LSB of the second to K-th main output data, and the first to (K) whose weights overlap the second to K-th main output data.
(1) A digital / analog converter wherein the upper bit group of the main output data is fixed to a maximum value.