JP2573679B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device provided with a defect relief circuit for relieving a defect by adding a redundant memory cell.

[Conventional technology]

Conventionally, in detecting a defect (defect) of a storage circuit (memory cell) constituting such a semiconductor storage device, a defective cell is rescued by a redundant memory cell added to the storage circuit and a defect rescue circuit. However, there is a case where there is a memory cell which cannot be remedied by using the defective remedy circuit. In order to detect the presence or absence of a defective memory cell in such a case, the defective memory cell is specified using an external control circuit or the like.

FIG. 3 is a block circuit diagram of a semiconductor memory device showing an example of such a prior art.

As shown in FIG. 3, in order to detect the presence / absence of a defect in the memory cell 4 that cannot be remedied by using the defect rescue circuit 7 that rescues a defect by adding a redundant memory cell 4A to the storage circuit, first, externally, The mode is set by the provided control circuit 16, and the address of the memory cell 4 is specified from the address input terminal 11. The input address signal is accessed to the memory cell 4 via the address buffer 12 and the address decode circuit 13, and the data of the selected memory cell 4 is output via the sense amplifier 5, the defect rescue circuit 7 and the output buffer 9. Output to terminal 10. Next, the control circuit 16 sets a mode in which the defect relief of the defect relief circuit 7 is invalidated, and outputs the data of the address of the specified memory cell 4 from the address input terminal 11 to the output terminal 10. By comparing these two data externally,
The defect rescue circuit 7 can detect the presence or absence of a defect in one unrecoverable memory cell. By performing such a comparison operation on all the memory cells 4, the presence or absence of a defect of the memory cell which cannot be repaired conventionally is detected.

[Problems to be solved by the invention]

In the above-described conventional semiconductor memory device, when detecting a defect in a memory circuit (memory cell) constituting a central portion thereof, a read time of data before input to the defect rescue circuit and a data read time through the defect rescue circuit are reduced. A read time is required, which has a disadvantage that it takes twice as long as a normal read time.

In particular, in the case of a circuit that performs defect repair by adding a redundant memory cell to an original memory cell, the main data of the original memory cell and the redundant data of the redundant memory cell must be read. As a result, it takes four times as long as the normal data reading time.

Further, in such a conventional semiconductor memory device, it is necessary to set each read mode in order to read main data and redundant data before and after input to the defect relief circuit, and the operation becomes complicated. Has disadvantages.

An object of the present invention is to provide a semiconductor memory device that can easily and quickly detect the presence or absence of a defect in a memory cell that cannot be remedied by using such a defect rescue circuit.

[Means for solving the problem]

A semiconductor memory device according to the present invention includes a storage circuit having a redundant memory cell, an address selecting means for accessing the storage circuit, and relieving data of a defective cell among data read from the storage circuit via a sense amplifier. And a data detection circuit for detecting a mode signal for repairing the defective cell, and storing data to be written to the storage circuit for comparing data before and after the defect relief. A data comparison circuit for reading the stored data and the data written to the storage circuit and comparing the output of the defect relief circuit with a data output of the defect relief circuit; and an output of the defect relief circuit and the data comparison circuit. An output switching circuit for performing switching control based on the output of the signal detection circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block circuit diagram of a semiconductor memory device showing a first embodiment of the present invention.

As shown in FIG. 1, in this embodiment, a signal detection circuit 2 is connected to a storage circuit (memory cell) 4 having a redundant memory cell 4A and a mode input terminal 1 and detects a mode signal for detecting a defective cell. And an address sequential selection circuit 3 for selecting and sequentially switching the lowest address of the memory cell 4 when the signal detection circuit 2 detects the failure detection mode, and amplifies data read from the memory cell 4. A sense amplifier 5 to perform a repair operation, and a defect relieving circuit 7 for relieving data of a defective cell among outputs of the sense amplifier 5,
A data comparing circuit 6 for comparing data before and after the input of the defect relief circuit 7; an output switching circuit 8 controlled by the output of the signal detection circuit 2 to switch the output of the data comparison circuit 6 or the defect relief circuit 7; An output buffer 9 for outputting the output of the switching circuit 8 to the output terminal 10 is provided.

In the semiconductor memory device having such a configuration, first, when a mode signal is input to the input terminal 1 of the failure detection mode, a control signal is output from the signal detection circuit 2 and the address sequential selection circuit 3 and the output switching circuit 8 can operate. State. Next, the lowest address of the memory cell 4 is selected by the address sequential selection circuit 3. The data read from the lowest address is input through a sense amplifier 5 to a data comparison circuit 6 and a defect relief circuit 7 for relieving a cell defect by adding a redundant memory cell 4A to the memory cell 4. The output of the defect relief circuit 7 is input to the data comparison circuit 6. Therefore, the data comparison circuit 6
Are the output of the sense amplifier 5 (that is, the data before the input of the defect relief circuit 7) and the output of the defect relief circuit 7 (that is, the data
After the input), and as a result, the defect relief circuit 7
If the difference of data equal to or more than the number of defective data that can be remedied is detected, "1" is sent to the output switching circuit 8 otherwise. As described above, the result of comparing the data before and after the defect is remedied by the control signal from the signal detection circuit 2 is as follows:
That is, the output of the data comparison circuit 6 is sent to the output terminal 10 through the output buffer 9. If the data comparison circuit 6
If no unrecoverable data is detected, the address sequential selection circuit 3 selects the next address, compares the data at that address, and outputs the result in the same manner.

If the above operation is repeated and "1" is output, it means that the presence of an irreparable memory cell has been detected.

The writing of data to such a semiconductor memory device is well known, and is omitted for the sake of simplicity. That is, it goes without saying that circuits such as a data input terminal and an input buffer are also provided in this embodiment.

FIG. 2 is a block circuit diagram of a semiconductor memory device showing a second embodiment of the present invention.

As shown in FIG. 2, this embodiment is the same as the above-described first embodiment except that the address selection means for the memory cell 4 and the data supplied to the data comparison circuit 6A are different.

First, when a mode signal is input to the mode input terminal 1, a control signal is output from the signal detection circuit 2A, and the output switching circuit 8 is activated. Since this signal detection circuit 2A does not have an address selection function, it is simpler than the signal detection circuit 2 shown in FIG. The address input from the address input terminal 11 specifies an arbitrary address of the memory cell 4 via the address buffer 12 and the decoding circuit 13.

Next, data is written from the input / output terminal 14 through the input buffer 15 to the address of the memory cell 4 designated as described above. At this time, the same data as the written data is latched in the data comparison circuit 6A.

Thereafter, the data read from the memory cell 4 is sent to the defect relief circuit 7 via the sense amplifier 5, and is input to the data comparison circuit 6A after the defect relief. Here, the data comparison circuit 6A compares the identity with the data input from the input / output terminal 14 and latched, and as a result, if there is a defect equal to or greater than the number of defective data that can be rescued in the defect rescue circuit 7, "1" is sent out to the output switching circuit 8 otherwise. The output switching circuit 8 outputs the output of the data comparison circuit 6A to the input / output terminal 14 through the output buffer 9 according to the control signal from the signal detection circuit 2A.
That is, if the output of the input / output terminal 14 is "1", it means that the presence of an unrecoverable memory cell has been detected.

Therefore, according to the present embodiment, there is an advantage that a defect of a memory cell can be detected for an arbitrary portion of the memory cell 4.

In the above, two embodiments have been described. In short, in these embodiments, the mode setting for defect detection needs to be performed only once, and the original data at one address and the data from the redundant memory cell are compared. Can be performed at once and simultaneously.

〔The invention's effect〕

As described above, the semiconductor memory device of the present invention detects a failure of a memory cell included in a storage circuit.
By forming a failure detection circuit with a mode signal detection circuit, a failure relief circuit, a data comparison circuit, and an output switching circuit, the presence / absence of a failure in a memory cell that cannot be repaired by using the failure relief circuit can be detected in one mode. There is an effect that the setting can be easily realized in a short time of 1/4 of the conventional case.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention, FIG. 2 is a block circuit diagram of a semiconductor memory device according to a second embodiment of the present invention, and FIG. FIG. 3 is a block circuit diagram of a similar device showing one example. 1 ... mode input terminal, 2, 2A ... signal detection circuit, 3 ...
Address sequential selection circuit, 4 ... Storage circuit (memory cell), 4A ... Redundant memory cell, 5 ... Sense amplifier, 6,
6A: Data comparison circuit, 7: Defect relief circuit, 8: Output switching circuit, 9: Output buffer, 10: Output terminal, 11
…… Address input terminal, 12 …… Address buffer, 13…
... Address decode circuit, 14 ... I / O terminal, 15 ... Input buffer.

Claims (1)

(57) [Claims] 1. A storage circuit having a redundant memory cell, an address selection means for accessing the storage circuit, and a defect relief for relieving data of a defective cell among data read from the storage circuit via a sense amplifier. A signal detection circuit for detecting a mode signal for repairing the defective cell, and data to be written to the storage circuit for comparing the identity of data before and after the defect relief. A data comparison circuit for reading the stored data and the data written to the storage circuit, comparing the data output recovered by the defect relief circuit with a defect, and outputting the comparison result; A semiconductor memory device, comprising: an output switching circuit that switches and controls each output of the data comparison circuit based on the output of the signal detection circuit.