JP2572734B2 - Display circuit for serial data - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a digital communication line test apparatus for testing a multimedia multiplexer (MTDM) and the like. This is for a serial data display circuit in which the first bit of data is shifted to the last stage of the shift register and displayed.

(B) Conventional technology and problems First, the configuration diagram of the digital communication line test apparatus is shown in FIG.
Shown in the figure.

In FIG. 3, reference numeral 21 denotes an error bit measuring device, and reference numeral 22 denotes a multiplexer.

The signal on the upper side of FIG. 3 is sent from the error bit measuring device 21 to the multiplexer 22, and the signal on the lower side of FIG. 3 returns to the error bit measuring device 21 from the multiplexer 22.

The error bit measuring device 21 compares the transmission data with the reception data, and checks the operation states of the communication line and the multiplexer.

In this case, the number of bits inserted between the synchronization signals differs depending on the method used.

In the example of FIG. 3, "01010" is entered, but about 30 channels are transmitted and received simultaneously in a normal digital communication line.

Next, FIG. 4 shows a conventional circuit diagram for displaying the state of each channel in FIG.

4 is a shift register, 7 is a latch circuit, 8 is a display, 11 is serial data, 12 is a clock, and 13 is a control signal.

In FIG. 4, serial data 11 is added to the shift register 6 at the timing of the clock 12, and the shift register 6
Is latched by the latch circuit 7 by the control signal 13.

The latch circuit 7 sends the latched data to the display 8 for display.

 Next, FIG. 5 shows the time chart of FIG.

FIG. 5A is a waveform diagram of the serial data 11, and FIG.

In the example of FIG. 5A, the first bit is S, the next bit is T, and the last bit is U.

The serial data 11 in FIG. 5A is the clock in FIG.
The control signal 13 shown in FIG. 5C is output at the end of the serial data 11.

FIGS. 5D to 5C show the output of the shift register 6. FIG.

In the prior art shown in FIGS. 3 and 4, the position of the first bit S displayed on the display 8 differs depending on the number of bits of the serial data 11.

For example, when the number of bits is three, the first bit S is displayed on the display 8C, and when the number of bits is five, the first bit S is displayed on the display 8E.

Therefore, if the contents of the serial data 11 are not known, there is a problem that the first bit of the serial data 11 cannot be known.

The circuit shown in FIG. 4 is a simple circuit that does not include a CPU (Central Processing Unit) and the like, as is apparent from FIG. Since only data etc. are transmitted, it is adjusted to the bit length of the serial data 11 (by software processing).
There is a problem that it is impossible to change the operation setting of the circuit.

(C) Object of the invention It is an object of the invention to provide a display circuit in which the first bit of serial data is always displayed at the last stage of a display even when testing a digital communication line having a different number of bits. I do.

(D) Embodiment of the Invention Next, FIG. 1 shows a configuration diagram of an embodiment according to the present invention.

1 and 2 are flip-flops (hereinafter referred to as FF), 3 is a clock generator, 4 is a switch, 5 is a counter, and 6 to 8 are the same as those in FIG.

The clock generator 3 generates a clock 14 that is sufficiently shorter than the clock 12.

For example, when the cycle of the clock 12 is 156 μs, the cycle of the output pulse of the clock generator 3 is set to about 33 ns.

In FIG. 1, serial data 11 and clock 12 are applied to the input of FF1, and control signal 13 and clock 12 are applied to the input of FF2.

 The switch 4 is controlled by the output of FF2.

The switch 4 has two switching circuits, and one circuit is
The output of FF1 and the ground are switched to output either one as a switching output 4A, and the other circuit switches clocks 12 and 14 to output either one as a switching output 4B.

The counter 5 counts the switching output 4B and sends the output to the latch circuit 7.

The input of the shift register 6 has a switching output 4A and a switching output
Add 4B.

 1 operates as follows.

When receiving the serial data 11, the counter 5
Counts the clock 12, and when the control signal 13 is received, the control signal 13 switches the switch 4 and the counter 5 counts the clock 14.

 Next, FIG. 2 shows a time chart of FIG.

FIG. 2A is a waveform diagram of the serial data 11, and FIG. 2A is a waveform diagram of the control signal 13.

FIG. 2A shows an example in which the first bit is composed of S bits, the next bit is composed of T bits, and the last bit is composed of 3 bits of U bits.

The control signal 13 is configured to output when the serial data 11 ends.

FIG. 2C is a waveform diagram of the clock 12, and FIG. 2D is a waveform diagram of the switching output 4A of the switch 4.

The serial data 11 and the control signal 13 come out in synchronization with the clock 12.

FIG. 2E is a waveform diagram of the clock 14, and FIG.
2 is an output waveform diagram of FIG.

FIG. 2 is a waveform diagram of the switching output 4B of the switch 4, and FIG.

The switching output 4B outputs the clock 1 when the control signal 13 is input to FF2.
4 is sent to the counter 5.

After counting up to “3”, the counter 5 counts “4” and “5” with the clock 14.

In other words, when the counter 5 counts “5”, the counter 5 drives the latch circuit 7. When the serial data 11 is 3 bits, when the control signal 13 is input, the counter 5 counts. The clock 14 is applied to the input of the counter 5 so that it becomes "5" earlier. And
When the counter 5 counts "5", the serial data
The first 11 bits are shifted to the last stage of the shift register 6, and this state is displayed on the display 8 as the output of the latch circuit 7.

2 to FIG. 2 show the output of the shift register 6. FIG.

(E) Effects of the Invention According to the present invention, even when a digital communication line having a different number of bits is tested, the second clock which is sufficiently shorter than the first clock of the communication line is employed, and the serial clock is set based on the set value of the counter. When the number of data bits is small, the second clock is counted until the counter value is reached, and the latch circuit is driven by the counter output. Therefore, the first bit of serial data is always displayed on the last stage of the display. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment according to the present invention, and FIG.
FIG. 3 is a block diagram of a digital communication line test apparatus, FIG. 4 is a conventional circuit diagram for displaying the state of each channel of FIG. 3, and FIG. 5 is a time chart of FIG. It is. 1 flip-flop (FF), 2 FF, 3 clock generator, 4 switcher, 4A switch output, 4B switch output, 5 counter, 6 shift register, 7 ...
... Latch circuit, 8 ... Display, 11 ... Serial data,
12 ... clock, 13 ... control signal, 14 ... clock.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kiyomi Hara 4-19-7 Kamata, Ota-ku, Tokyo Inside Ando Electric Co., Ltd. (56) References JP-A-59-83243 (JP, A) JP-A-58 -51652 (JP, A) JP-A-60-178745 (JP, A)

Claims (1)

(57) [Claims] A digital communication line test apparatus controlled by a first clock (12) to activate a control signal (13) after transmitting serial data (11). A first flip-flop (1) that outputs a control signal (13) in synchronization with the first clock (12); a second flip-flop (2) that outputs a control signal (13) in synchronization with the first clock (12); When the output of a clock generator (3) that generates a second clock (14) having a shorter cycle than the first clock (12) and the output of the second flip-flop (2) becomes active, the first switching output (4A) ) From the output of the first flip-flop (1) to ground and a switch (4) for switching the second switch output (4B) from the first clock (12) to the second clock (14); Second switching output (4B) Doo counter (5)
A shift register (6) for inputting the first switching output (4A) in synchronization with the second switching output (4B); and a shift register (6) when the count value of the counter (5) reaches a predetermined value. Circuit (7) for latching the output of
And a display (8) that receives an output of the latch circuit (7) as an input.