JP2572656B2 - D / A conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to, for example, a video signal processing apparatus that digitizes a video signal of one channel and then divides the video signal to obtain video signals of a plurality of channels for driving a liquid crystal. And a suitable D / A conversion circuit.

[Prior Art] The current television system, the NTSC system, has 525 scanning lines.
Book / frame, interlace ratio 2: 1, aspect ratio
4: 3. In this case, since the video signal band is as narrow as several MHz, it is not necessary to divide the video signal into a plurality of channels to improve the processing speed.

[Problems to be Solved by the Invention] On the other hand, a so-called high-definition television system, which is a so-called high-definition television system, has 1125 scanning lines / frame, an interlace ratio of 2: 1, and an aspect ratio of 16: 9. The amount of information is about five times that of the NTSC system. Video signal bandwidth up to 30 MHz
It becomes wide with z.

For example, when a liquid crystal display is used to display an image based on a video signal of such a high-definition television system, the video signal is sampled at an extremely high speed along with a large increase in the number of pixels, and each of the liquid crystal panels is displayed. It is necessary to obtain a pixel signal for driving the pixel portion.

However, current source driver (for horizontal scanning)
Because the speed of the sample-and-hold circuit in the above is limited, it is possible to form a video signal of a plurality of channels by dividing a video signal of one channel and form a pixel signal by sequentially and repeatedly sampling the video signals of the plurality of channels. Conceivable. According to this, a pixel signal can be satisfactorily formed while the speed of the sample and hold circuit in each channel is kept low. For example, by dividing a video signal of one channel and forming a video signal of n channels, the speed of the sample and hold circuit in each channel can be reduced to 1 / n.

By the way, when a video signal of one channel is divided and a video signal of a plurality of channels is formed and processed as described above, if there is a deviation between the channels, variation occurs between the displayed pixels, and the image quality is reduced. to degrade.

Also, when the circuit operation changes due to temperature, humidity, etc. when used for a long time, and deviation occurs between each channel,
Similarly, the image quality deteriorates.

Since the liquid crystal is deteriorated by DC driving, it is necessary to add a video signal whose polarity is inverted every predetermined period around a certain DC voltage.

In view of the above, the present invention provides a D / A conversion circuit suitable for application to a video signal processing device for forming video signals of a plurality of channels for driving a liquid crystal without causing a deviation between the channels.

[Means for Solving the Problems] A D / A conversion circuit according to the present invention is a D / A conversion means for a video signal having a polarity inversion function and a full scale level adjustment function, and is output from the D / A conversion means. A full-scale voltage for adjusting the full-scale level of the video signal, voltage switching means for switching the offset voltage added to the video signal between positive polarity and negative polarity, and adjusting the full-scale voltage for each polarity It comprises a first voltage adjusting means and a second voltage adjusting means for adjusting the offset voltage for each polarity.

[Operation] By using the D / A conversion circuit having the above-described configuration when converting each digital video signal divided into a plurality of channels into an analog signal, the polarity is inverted every predetermined period to drive the liquid crystal display. A suitable analog video signal can be obtained. In addition, the full-scale voltage and the offset voltage can be adjusted for each channel, and the deviation of the video signal between the channels can be removed.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In this example, in order to form a video signal to be supplied to a liquid crystal panel constituting a liquid crystal display for displaying a high-definition television system image, one channel of a red signal R, a green signal G, and a blue signal B is divided into n The present invention is applied to a video signal processing device that uses channels, for example, six channels.

 FIG. 2 shows the overall configuration of the video signal processing device.

 First, the system of the red signal R will be described.

In the figure, a red signal R supplied to an input terminal 1R is supplied to a fixed terminal on the a side of a changeover switch 4 via an attenuator 2 and a clamp circuit 3.

A reference signal Sref is supplied from a reference signal generator 20 to a fixed terminal on the b side of the changeover switch 4.

The reference signal Sref is, as shown in FIG.
It is composed of signals of the first level and the second level in the 2n horizontal period (2nH). The first level corresponds to a black level of the video signal, and the second level corresponds to a white level of the video signal. In this example, the first level is hereinafter referred to as an offset level, and the second level is referred to as a full scale level.

Actually, as the signal of the offset level and the signal of the full scale level, a signal shifted from the black level and the white level by a few quantization steps to the white side and the black side, respectively, is used. The reason for this is that if the black level and the white level themselves are used, when a level change occurs in the black level direction and the white level direction, respectively, it becomes impossible to detect the change.

The reference signal generator 20 is controlled by the controller 22, and the reference signal Sref is generated within a vertical blanking period. The changeover switch 4 is controlled by the controller 22, and is connected to the b side during a period in which the reference signal Sref is supplied to the fixed terminal on the b side, and is connected to the a side during the other periods. That is, the switch 4 outputs a red signal R in which the reference signal Sref is inserted during the vertical blanking period (see FIG. 3).

The controller 22 is supplied with the horizontal synchronizing signal HD, the vertical synchronizing signal VD, the system clock CK, and the frame pulse FP. The clamp pulse to the clamp circuit 3 is also supplied from the controller 22.

The output signal of the changeover switch 4 is band-limited by a low-pass filter 5 to prevent aliasing distortion, and then converted to a digital signal by an A / D converter 6.

The output signal of the A / D converter 6 is supplied to a gamma correction circuit 7 and a gamma through circuit 8. The gamma correction circuit 7
For example, it is a circuit that is configured by a ROM and outputs gamma-corrected nonlinearity data. The gamma through circuit 8 is a circuit that outputs linearity data without gamma correction.

A control signal is supplied from the controller 22 to the gamma correction circuit 7 and the gamma through circuit 8, and linearity data is output from the gamma through circuit 8 during the period of the supply signal Sref.
In other periods, the non-linear data is output from the gamma correction circuit 7.

Here, the reason why the gamma through circuit 8 outputs the linearity data during the period of the reference signal Sref is to facilitate the arithmetic processing performed using the reference signal Sref as described later.

The output signal of the gamma correction circuit 7 and the gamma-through circuit 8 is supplied to the D / A converter 90 ₁ to 90 _n constituting the D / A conversion circuit 90 ₁ to 90 _n each are converted into analog signals. These D / A converter 9 ₁ to 9 _n are supplied control signals from the controller 22, the signal inverted every horizontal period is also performed.
This signal inversion is for AC driving of the liquid crystal.

D / A output signal of the transducer 9 ₁ to 9 _n, the adder 11 ₁ to 11 _n, respectively for adjusting the offset, a low pass filter 12 ₁ to 12 _n,
Attenuators 16 _{1 to} 16 _n , buffers 17 _{1 to} 17 _n and resistors
19 _1-19 via a series circuit of _n, n to the output terminal 27R ₁ ~27R _n
It is output as the red signals R _{1 to} R _n of the channel.

The output signal of the buffer 17 ₁ to 17 _n, respectively through the connection switch 18 ₁ ~ 18 _n and a low-pass filter 24 A /
After being supplied to a D converter 23 and converted into a digital signal, a microcomputer (hereinafter referred to as “microcomputer”) 21
Supplied to

Connected in the vertical blanking interval switch 18 ₁ ~ 18 _n
Is supplied with a control signal from the microcomputer 21 and the connection switch
18 ₁ to 18 _n are sequentially switched every two horizontal periods (2H) in the periods of the offset level and the full scale level of the reference signal Sref.

The reference signal Sref inserted during the vertical blanking period
In between 4nH but which is supplied to the signal circuit, D / signal inversion operation for every one horizontal period in the A converter 9 ₁ to 9 _n is not performed, the polarity reference signal Sref next, for example, a positive polar stationary In the case of, the positive electrode offset level B + is between 2 nH and the positive electrode full scale level W + is between 2 nH (shown in FIG. 4).

The microcomputer 21 detects the positive offset level B + and the positive full scale level W + of the reference signal Sref as the offset level (black) and the full scale level (white) of the positive signal, respectively, and the negative offset level B of the reference signal Sref. − And negative full scale level W− are the offset levels (black) of the negative polarity signal, respectively.
And full scale level (white).

As described above, the reference signal Sref of each channel is switched and supplied to the microcomputer 21 every two horizontal periods.
Since the data immediately after switching is unstable, data detection is not performed in the first horizontal period, but is performed only in the second horizontal period.

In the microcomputer 21, in addition to the red signal R, processing relating to a green signal G and a blue signal B, which will be described later, is also performed. Therefore, it takes a period of six fields to detect the offset level and the full scale level of the positive polarity signal and the negative polarity signal in each channel with respect to each of the color signals R and B, and this detection is performed by repeating the cycle of the six fields. .

For example, as shown in FIG. 5, in the first field, the offset level and the full scale level of the positive polarity signal in each channel of the red signal R are detected. In the second and third fields,
With respect to the green signal G and the blue signal B, the offset level and the full scale level of the positive polarity signal are similarly detected. In the fourth field, the offset level and the full scale level of the negative polarity signal in each channel of the red signal R are detected. In the fifth and sixth fields, the green signal G
Similarly, the offset level and the full scale level of the negative polarity signal are detected for blue signal B and blue signal B, respectively.

Also not mentioned above, the controller 22 in the first to third field, the generation period of the reference signal Sref, gives the D / A converter 9 ₁ to 9 _n and switches _{15 1 ~15 n, 26 1 ~26} n The signal inversion control signal is supplied so as to have a positive polarity. 4th
In the sixth to sixth fields, the supply is performed so as to have a negative polarity.

The microcomputer 21 compares the detected offset level B + of the positive signal, the full scale level W + of the positive signal, the offset level B− of the negative signal, and the full scale level W− of the negative signal with the reference value. This is performed for each channel.

The set data of the offset level of the positive polarity signal is adjusted according to the comparison result between the level B + and its reference value, and the D / A converter 9 is adjusted according to the comparison result between the level W + and its reference value.
The set data of the full scale level on the positive electrode side of _{1 to} 9 _n is adjusted, the set data of the offset level of the negative signal is adjusted according to the comparison result between the level B− and its reference value, and the level W− and its reference value are adjusted. D /
Set data of the negative polarity full-scale level of the A converter 9 ₁ to 9 _n are adjusted.

This adjustment is performed by, for example, an operation of increasing or decreasing “1” in the quantization step depending on the magnitude result. When the difference between the reference value and the detection level is small and within an allowable range, the set data is kept as it was last time. Such adjustment of the set data is performed within the vertical blanking period.

The set data of the positive-side and negative-side full scale levels adjusted by the microcomputer 21 are D / A converters 10 ₁ to 10 _n for non-inverted full scale and D / A converters for full scale when inverted, respectively. is supplied to the fixed terminal 25 _to 253 is supplied to the _n by a side by and b side of the changeover switch 26 ₁ ~ 26 _n Chi was is an analog signal. And this changeover switch 26
The output signal of the ₁ ~ 26 _n is supplied to the voltage terminal for determining the full scale of each D / A converter 9 ₁ to 9 _n.

Control signals are supplied from the controller 22 to the changeover switches 26 _{1 to} 26 _n, and the switches are connected to the a side during a horizontal period in which signal inversion is not performed in the D / A converters 9 _{1 to} 9 _n , so that horizontal switching is performed. In the period, it is connected to the b side. That is, the D / A converter 9
₁ full scale level to 9 _n, in the horizontal period in which the signal inversion is not carried out by the D / A converter 9 ₁ to 9 _n are set with the set data of the full scale level of the positive side, the horizontal period of the signal inversion is performed Is set with the set data of the full scale level on the negative electrode side.

Set data of the offset level of the positive electrode side and negative electrode side, which is adjusted by the microcomputer 21, D / A converters 14 ₁ ~ for each D / A converter 13 ₁ to 13 _n and the inverted time offset for inverting at offset is supplied to 14 _n is supplied to the fixed terminal on the a side and b side of the changeover switch 15 ₁ to 15 _n Chi was is an analog signal. The output signal of the changeover switch 15 ₁ to 15 _n are supplied to the adder 11 ₁ to 11 _n, respectively.

The change-over switch 15 ₁ to 15 _n is supplied the control signal from the controller 22, the horizontal period where signal inversion is not carried out by the D / A converter 9 ₁ to 9 _n is connected to a side, horizontal signal inversion is performed In the period, it is connected to the b side. Thus, the offset level of the red signal R ₁ to R _n of the n-channel is set with a set data of the offset level of the positive side in the horizontal period where signal inversion is not carried out by the D / A converter 9 ₁ to 9 _n,
In the horizontal period in which signal inversion is performed, it is set with the set data of the offset level on the negative electrode side.

Thus, the offset level and the full scale level of the positive polarity signal and the negative polarity signal detected from the n-channel red signals R _{1 to} R _n are compared with the reference value, and the D / A converters 9 ₁ to 9 since 9 _n full-scale level of the set data of the set data of the offset level with the adjustment is adjusted, as a result, the red signal R ₁ to R _n of the n-channel obtained at the output terminal 27R ₁ ~27R _n is , The full scale level and the offset level are equal, and the deviation is automatically corrected.

Figure 6 is shows a variation of the offset level and full-scale level of the offset level and full scale level and the signal of negative polarity positive polarity signal after correction before and correction for the red signal R ₁ to R _n of the n-channel It is.

As is apparent from this figure, after the correction, the offset level and the full scale level of each channel are all equalized to the reference value.

FIG. 7 shows an example of the waveform of the n-channel red signals R _{1 to} R _n after correction. The offset level of the positive polarity signal, for example, -8.0V its full scale level,
For example, this is an example in which the offset level of the negative signal is -1.0 V, and the full scale level thereof is -4.0 V, for example.

Although not described above, the level detection operation and the set data adjustment operation in the microcomputer 21 are performed according to the flowchart shown in FIG.

In the figure, when the power is turned on, various initial settings are made in step 101.

Next, in step 102, the initial reference set data of the offset level of the positive polarity signal, the full scale level of the positive polarity signal, the offset level of the negative polarity signal, and the full scale level of the negative polarity signal in each channel of each of the color signals R to B are obtained. Output, D / A converters 9 _{1 to} 9 _n and adder 11 ₁
Full-scale level and the offset level of the positive polarity signal and a negative polarity signal in each channel of each color signal R~B is set by to 11 _n.

 Next, at step 103, an interrupt is permitted.

Next, at step 104, it is determined whether there is an interrupt. The interrupt signal is continuously supplied from the controller 22 in the vertical blanking period with a cycle of two horizontal periods. In this case, the reference signal Sref of 4 nH inserted in the vertical blanking period of each field is supplied corresponding to the even-numbered horizontal period.

If there is an interrupt, it is determined in step 105 whether or not the data is the head data of the offset level and full scale level data (2n pieces) for n channels. In this case, a flag indicating the first data is supplied from the controller 22 corresponding to the second horizontal period of the 4 nH reference signal Sref inserted in the vertical blanking period of each field. Judgment is made by checking whether or not it is supplied.

If it is the first data, in step 106, the interruption of the first data is performed. In this case, in the first field, the connection switch ₁₈₁ is connected, the offset level of the positive polarity signal for the first channel of the red signal R (B +) is detected. In the second and third fields, the first and second signals of the green signal G and the blue signal
Offset level of positive polarity signal for channel (B
+) Is detected. In the fourth field, the connection switch
18 ₁ is connected, and the offset level (B−) of the negative polarity signal for the first channel of the red signal R is detected. In the fifth and sixth fields, similarly, the offset level (B−) of the negative polarity signal for the first channel of the green signal G and the blue signal B is detected.

During the horizontal blanking period after the data interruption, the connection switch corresponding to the channel to be detected next time is connected. For example, the in the next connection switch ₁₈₁ connects the switch 18 ₂ is connected.

Next, at step 107, it is determined whether or not there is an interrupt. When there is an interrupt, at step 108, R, G, B
Data of the offset levels B +, B- of the positive / negative signals of the second to n-th channels of the respective color signals and the full scale levels +, W- of the positive / negative signals of the first to n-th channels are interrupted. Then, in step 109, it is determined whether or not all the offset level and full scale level data (2n data) for n channels have been detected. Until all 2n data have been detected, the data in steps 107 and 108 is processed. Interrupts are repeatedly performed.

Thereby, in the first field, the first signal of the red signal R
The offset level B + and the full scale level W + of the positive polarity signal for the nth channel are detected. Second
And in the third field, the green signal G
The offset level B + and the full-scale level W + of the positive polarity signal for the first to n-th channels of the blue signal B are detected. In the fourth field, the offset level B- and the full scale level W- of the negative polarity signal for the first to n-th channels of the red signal R are detected.
In the fifth and sixth fields, similarly, the offset level B− and the full scale level W− of the negative polarity signals for the first to n-th channels of the green signal G and the blue signal B are detected, respectively.

When it is determined in step 109 that all 2n data have been detected, the process returns to step 104 via the subroutine of step 110, and the operation of the next field is started. That is, the operation of detecting data in the first to sixth fields is repeatedly performed in this order (see FIG. 5).

The data processing in step 110 is performed as shown in FIG.

First, in step 111, the level B + for the first channel is compared with its reference value, and it is determined whether or not the difference is within an allowable range.

If it is not within the allowable range, it is determined in step 112 whether the value is below the reference value. If the difference is equal to or smaller than the reference value, in step 113, the set data of the offset level of the positive polarity signal for the first channel is increased by the “1” quantization step.
Is stored in the memory. If it is not equal to or smaller than the reference value in step 112, the set data of the offset level of the positive polarity signal for the first channel is reduced by “1” quantization step in step 115,
At step 114, it is stored in memory.

When it is within the allowable range in step 111,
After the set data is determined to be the same as the previous time in step 116, the data is stored in the memory in step 114.

The above processing is performed with the offset level B− of the negative polarity,
This is also performed for the positive polarity full scale level W +. Regarding the negative full-scale level W-, the relationship of addition and subtraction in steps 113 and 115 is reversed.

After the set data is stored in the memory at step 114, it is determined at step 117 whether or not the processing for all of the 2n data detected in each field has been completed. If not all completed, steps 111 to 116
Thus, all the processes are performed.

Thereby, in the first field, the first signal of the red signal R
New set data of the offset level and the full scale level of the positive polarity signal for the nth channel are stored in the memory. In the second and third fields, similarly, new set data of the offset level and the full scale level of the positive polarity signals for the first to n-th channels of the green signal G and the blue signal B are stored in the memory. In the fourth field, the first to n-th red signals R
New set data of the offset level and the full scale level of the negative signal for the channel is stored in the memory. In the fifth and sixth fields, similarly, new set data of the offset level and the full scale level of the negative polarity signals related to the first to n-th channels of the green signal G and the blue signal B are stored in the memory.

When it is determined in step 117 that the processing for all of the 2n data has been completed, in step 119, the set data stored in the memory by the above-described processing is output, and the full scale level and the offset level are newly set. Is done.

That is, in the first to third fields, the offset level and the full-scale level of the positive polarity signal for the first to n-th channels of the color signals R to B are newly set. In the fourth to sixth fields, the color signals R to
The offset level and the full scale level of the negative polarity signal for the first to n-th channels of B are newly set.

The data processing shown in FIG. 9 is performed during the vertical blanking period.

Figure 1 shows a specific configuration example of the D / A conversion circuit 90 ₁ to 90 _n.

In the figure, reference numeral 51 denotes a D / A converter.
For example, a red signal R digitized by 8 bits per sample is supplied to 51.

This D / A converter 51 has a signal inversion function. That is, the D / A converter 51 includes the controller 22 (second
The digital code is inverted every horizontal period (1H) after the code inversion signal SCl is supplied from the drawing (shown in the figure) (excluding the insertion period of the reference signal Sref). As a result, the D / A converter 5
The one output signal becomes a negative signal and a positive signal every horizontal period.

The output signal of the D / A converter 51 is supplied to an inverting input terminal of an operational amplifier 52 forming an adder via a resistor r1. The non-inverting input terminal of the operational amplifier 52 is grounded, and the output signal is supplied to the inverting input terminal via a feedback resistor r2. The output signal of the operational amplifier 52 is output after being band-limited by the low-pass filter 53.

Reference numeral 54 denotes a D / A converter for setting an offset level. When a negative signal is output from the above-described D / A converter 51 to the D / A converter 54 (hereinafter referred to as “at the time of negative polarity”)
And when a positive polarity signal is output (hereinafter referred to as “positive polarity”
The set data for the positive / negative polarity latched by the 10-bit register 55 is switched by the controller 22 and supplied. In this case, the set data of the 10-bit offset level output from the microcomputer 21 is 8 bits.
10-bit register 55 using bit bus line twice
And temporarily stored in the register 55 by the latch signal SL0 from the controller 22, and then supplied.

A stable constant voltage is output to a reference voltage terminal VREF of the D / A converter 54, and a voltage that changes in accordance with 10-bit set data is output to a correction voltage terminal OUT.

The reference voltage terminal VREF of the D / A converter 54 is connected to the inverting input terminal of the operational amplifier 52 via a volume VR1 for adjusting the offset level of the positive polarity signal.

The reference voltage terminal VREF is connected to an inverting input terminal of an operational amplifier 56 constituting a buffer. An output terminal of the operational amplifier 56 is connected to a non-inverting input terminal of an operational amplifier 57 via a volume VR3 for adjusting an offset level of a negative polarity signal. Connected to terminal. The output terminal of the operational amplifier 57 is connected to its inverting input terminal via a feedback resistor r4, and this output terminal is connected to the I-side fixed terminal of a changeover switch 58 via a volume VR2. switch
The fixed terminal on the N side of 58 is grounded.

The changeover switch 58 is constituted by a so-called electronic switch, and is connected to the N side when the polarity is positive and to the I side when the polarity is negative. The output side of the changeover switch 58 is connected to the inverting input terminal of the operational amplifier 52 via the resistor r11.

Further, the correction voltage terminal OUT of the D / A converter 54 is connected to the inverting input terminal of the operational amplifier 52 via a series circuit of an operational amplifier 59 and a resistor r3 that constitute a buffer.

In the above configuration, at the time of positive polarity, a constant voltage output to the reference voltage terminal VREF of the D / A converter 54 is added by the operational amplifier 52 through the volume VR1, and
The voltage corresponding to the set data at the time of the positive polarity output to the correction voltage terminal OUT of the D / A converter 54 is added by the operational amplifier 52 through the operational amplifier 59 and the resistor r3. This allows
The control is performed so that the offset level of the positive polarity signal output from the operational amplifier 52 becomes equal to the reference value.

In the case of negative polarity, the reference voltage terminal VR of the D / A converter 54
Constant voltage output to EF is operational amplifier 56, volume V
R3, an operational amplifier 57, a volume VR2, a changeover switch 58, and a voltage corresponding to the negative polarity set data output to the correction voltage terminal OUT of the D / A converter 54 while being added by the operational amplifier 52 through a resistor r11. Is an operational amplifier 59
And the result is added by the operational amplifier 52 through the resistor r3. Thus, the offset level of the negative signal output from the operational amplifier 52 is controlled to be equal to the reference value.

Reference numeral 60 denotes a D / A converter for setting a full scale level. To the D / A converter 60, the positive / negative polarity set data latched in the 8-bit register 63 is switched by the controller 22 and supplied to the negative polarity and the positive polarity, respectively. In this case, 8
Bit full-scale level set data is supplied to an 8-bit register 63 using an 8-bit bus line, and is temporarily stored in the register 63 by a latch signal SLF from the controller 22 before being supplied.

A stable constant voltage is output to the reference voltage terminal VREF of the D / A converter 60, and a voltage that changes according to the 8-bit set data is output to the correction voltage terminal OUT.

The reference voltage terminal VREF of the D / A converter 60 is connected to the inverting input terminal of the operational amplifier 61 via the volume VR4 for adjusting the full scale level and the resistor r10. The non-inverting input terminal of the operational amplifier 61 is grounded, and its output terminal is connected to the base of a PNP transistor 62 for generating a full-scale correction voltage. The emitter of the transistor 62 is grounded via a resistor r7 and connected to the inverting input terminal of the operational amplifier 61 via a feedback resistor r6.

The collector of the transistor 62 is connected to the reference voltage terminal VEE of the D / A converter 51 via the resistor r9. Then, the voltage dropped by the resistor r9 is supplied to the full scale setting terminal of the D / A converter 51.

Further, the correction voltage terminal OUT of the D / A converter 60 is connected to the inverting input terminal of the operational amplifier 61 via the resistor r8.

In the above configuration, when the negative polarity and the positive polarity,
The constant voltage output to the reference voltage terminal VREF of the D / A converter 60 is controlled by the volume VR4, the operational amplifier 61, and the transistor 62.
Is applied to the full scale setting terminal of the D / A converter 51, and a voltage corresponding to the set data output to the correction voltage terminal OUT of the D / A converter 60 is supplied to the D / A converter through the operational amplifier 61 and the transistor 62. Applied to the full-scale setting terminal of the detector 51. As a result, the full-scale level of the negative polarity signal and the positive polarity signal output from the operational amplifier 52 is controlled so as to be equal to the reference value.

By the way, in the example of FIG. 1, when the polarity is positive, the signal is not inverted by the D / A converter 51, so that the ground potential corresponds to the offset level, and the full-scale setting terminal and the reference voltage terminal VEE The potential difference corresponds to the full scale level. In other words, at the time of positive polarity,
Even if the voltage of the full-scale setting terminal changes due to the full-scale level correction operation, the offset level does not change.

However, when the polarity is negative, the signal is inverted by the D / A converter 51, so that the ground potential corresponds to the full scale level, and the potential difference between the full scale setting terminal and the reference voltage terminal VEE corresponds to the offset level. It will be. That is, at the time of the negative polarity, when the voltage of the full scale setting terminal changes by the full scale correction operation, the offset level changes.

Therefore, in the example of FIG. 1, the emitter of the transistor 62 is connected to the inverting input terminal of the operational amplifier 57 via the resistor r5.

The emitter potential of the transistor 62 corresponds to the full-scale level correction voltage output to the correction voltage terminal OUT of the D / A converter 60, and this is applied to the inverting input terminal of the operational amplifier 57 as an offset level correction signal. . As a result, the fluctuation of the offset level due to the full-scale correction operation at the time of the negative polarity is corrected in the reverse direction and canceled.

In this case, the resistance value of the resistor r7 is made equal to the resistance value of the resistor r9, and the resistance value of the resistor r1, the resistance value of the volume VR2, the ON resistance value of the changeover switch 58, and the resistance value of the resistor r11 are obtained. The sum is equal, and the resistance of resistor r4 and the resistor
The correction sensitivity is adjusted by equalizing the resistance value of r5.

In the above, the system of the red signal R has been described, but the system of the green signal G and the blue signal B is similarly configured.

In FIG. 2, the processing circuits of these systems are blocked.
Shown at 100G and 100B. When the green signal G and the blue signal B are supplied to the input terminals 1G and 1B, the output terminal 27
G _{1 to} 27 G _n and 27 B _{1 to} 27 B _n each have no deviation n
Green signal G ₁ ~G _n and B ₁ .about.B _n channel is obtained.

According to this embodiment, since the signal inversion is performed every horizontal period in the D / A converting circuit 90 ₁ to 90 _n, the signal R ₁ ~ n-channel suitable for AC driving a liquid crystal display
R _n, it is possible to obtain the G ₁ ~G _n and B ₁ ~B _n.

Also, since the offset level and full-scale levels in the D / A conversion circuit 90 ₁ to 90 _n in the negative polarity signal and the positive polarity signal is adjusted to be constant, 1 channel signal R, from G and B, respectively It is possible to obtain n-channel signals R _{1 to} R _n , G _{1 to} G _n and B _{1 to} B _n without deviation,
Image quality can be prevented from deteriorating.

Further, according to this example, even if the circuit operation changes due to temperature, humidity, etc. when used for a long time, the offset level and the full scale level of the signal of each channel are adjusted to be constant, so that the image quality is Degradation can be prevented.

Even if not described above, when the resolution of the A / D converter 6 is M bits and the resolution of the A / D converter 23 is N bits in FIG. Can do it. For example, M = 8 and N = 10.

[Effects of the Invention] As described above, according to the D / A conversion circuit of the present invention, the D / A conversion means has a polarity inversion function,
It has means for adjusting the offset level and the full scale level at the time of positive polarity and at the time of negative polarity. Therefore, by applying when converting each digital video signal divided into a plurality of channels into an analog signal,
It is possible to obtain an analog video signal suitable for driving the liquid crystal display by inverting the polarity every predetermined period.
Further, the full scale level and the offset level can be adjusted for each channel, and the deviation between the channels can be eliminated. Further, fluctuation due to a change with time in the same channel can be removed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a specific configuration of a D / A conversion circuit, FIG. 2 is a diagram showing a configuration of a video signal processing apparatus, FIGS. 3 and 4 are diagrams showing a configuration of a reference signal, and FIG. FIG. 6 is a diagram showing a detection order of scale levels, FIG. 6 is a diagram showing an operation of correcting a deviation between channels, FIG. 7 is a diagram showing an example of a signal waveform after level correction, and FIGS. 9 is a flowchart illustrating a detection operation and a set data adjustment operation. 1R, 1G, 1B ... input terminals 4, 15 ₁ to 15 _n , 26 _{1 to} 26 _n , 58 ... changeover switches 6, 23 ... A / D converters 9 _{1 to} 9 _n , 10 ₁ to 10 _n , 13 ₁ -13 _n , 14 ₁ -14 _n , 25 ₁ -25 _n , 51,
54,60 D / A converters 11 _{1 to} 11 _n Adders 18 ₁ to 18 _n Connection switches 20 Reference signal generator 21 Microcomputer 22 Controllers 27R _{1 to} 27R _n , 27G _{1 to} 27G _n , 27G _{1 to} 27G _n ... output terminals 52, 56, 57, 59, 61 ... operational amplifiers 90 _{1 to} 90 _n ... D / A conversion circuit

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Politics Shuto 22-22, Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (56) References JP-A-50-28969 (JP, A) JP-A-63- 121320 (JP, A) JP-A-64-35493 (JP, A) JP-B-48-44825 (JP, B1)

Claims (1)

(57) [Claims] 1. A D / A converter for a video signal having a polarity inversion function and a full scale level adjustment function, and a full scale voltage for adjusting a full scale level of a video signal output from the D / A converter. Voltage switching means for switching an offset voltage to be added to the video signal between a positive polarity and a negative polarity; first voltage adjusting means for adjusting the full scale voltage at each of the polarities; Is adjusted for each of the above polarities.
A D / A conversion circuit, comprising: