JP2569867B2 - Effective Address Precalculation Pipeline Microprocessor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an effective address pre-computation type pipelined microprocessor, and more particularly, to a mechanism for avoiding a register hazard that may occur in an effective address pre-computation calculation.

2. Description of the Related Art Conventionally, a large-scale computer operating in a pipeline system may be provided with a copy register for copying the contents of all general-purpose registers to an effective address calculation unit or an instruction decode unit. In this type of computer, when the decoder decodes an instruction that changes the contents of the general-purpose register, the effective address calculation unit or the instruction decode unit predicts the execution result of the instruction and updates the copy register value. It is configured to be. Therefore, when a general-purpose register is used as a base register for register indirect addressing, a register hazard generated in the effective address preceding calculation stage is avoided by using a copy register that copies the general-purpose register as a base register. .

However, in such a configuration, the scale of hardware becomes very large, so that even the same effective address pre-calculation type pipeline system cannot be adopted in the case of a microprocessor. Therefore, in a pipeline microprocessor of the effective address preceding calculation type, when a general-purpose register whose contents can be modified by addressing with auto-modifying in a preceding instruction is used in register indirect addressing in a subsequent instruction, a register hazard is used. The occurrence was inevitable.

In particular, the base address register value is
An addressing mode in which the base address register value is increased or decreased by the data size during instruction execution after addressing as an address (hereinafter referred to as “post” or “modify addressing”), or the base address register value is replaced by the data size. An addressing mode in which the result of addition or subtraction is used as an operand address to make the base address register value an addition or subtraction result of the data size at the time of instruction execution (hereinafter referred to as pre-modify addressing;・
Immediately after "modify addressing" and "auto-modify addressing", the register specified by the auto-modify addressing is specified as the base address register for operand address calculation by a subsequent instruction Until the execution of the instruction having the preceding auto-modify addressing is completed, the address generation of the succeeding instruction cannot be performed, and the pipeline has an empty space.

The vacancy of the pipeline will be described with reference to FIG. 5 which is a block diagram around the effective address advance calculation section of the prior art effective address advance calculation type pipeline microprocessor and FIG. 6 which is a timing diagram thereof.

In the prior art effective address pre-computation type pipeline and microprocessor, the addressing mode description section 501 of the instruction code 108 is input to the addressing mode decoder 107 to obtain a modification amount designation signal 503, and the instruction The base address register identification code part 502 of the code 108 is decoded by the base address decoder 105 and the base
Get address register value 506.

Constant ROM1 for pre-modify addressing
A modification amount designation signal 503 is input to the constant ROM 103 so that 03 supplies the modification amount to the effective address adder 102, and the effective address adder 102 outputs the modification amount to the base address register value 506 as an effective address output 505. Is output to the address translator (TL) 106.

Next, in the case of post-modify addressing, the output of the constant ROM 103 is controlled to be zero, and the base address register value 506 is output to the address converter 106 as it is.

In the effective address preceding calculation type pipeline microprocessor, one instruction process after instruction decoding can be divided into an effective address calculation stage, an address conversion stage, and an instruction execution stage.

For example, when executing the instruction sequence shown in FIG. 8, the modification of the base address register in the instruction shown in FIG. 6 is performed at the end of the instruction execution stage (time M).
The effective address calculation stage of the instruction is extended until the time M at which the value of the register file 104 is actually modified by the instruction execution unit 901 in order to maintain the sequentiality of instruction execution. Such a waiting state of the effective address calculation of the succeeding instruction due to the change of the register value of the preceding instruction is called a register hazard.

When a register hazard occurs, two stages of execution space are generated between the end of the instruction execution and the start of the instruction due to the delay of the effective address calculation and address translation stages of the instruction.

Problems to be Solved by the Invention As described above, the conventional effective address pre-computation type pipelined microprocessor has no mechanism for avoiding register hazards, so that the register whose value can be rewritten by the preceding instruction can be rewritten. Is used as the base address register for the effective address calculation in the subsequent instruction, a register hazard occurs in the effective address calculation stage, and the performance may be degraded.

Accordingly, an object of the present invention is to provide a configuration of a new effective address preceding calculation type pipeline microprocessor which can effectively reduce register hazards occurring in a pipeline without extremely increasing the circuit scale. And

Means for Solving the Problems According to the present invention, a register file that can be used as a base value of an operand address (hereinafter, referred to as a base address);
An effective address generator that calculates and generates an effective address of an operand prior to instruction execution as an address register, and a value obtained by adding a constant value to an effective address generation result (hereinafter, referred to as an address register).
A register (hereinafter referred to as a register) that selects and holds one of a modification amount addition result and an effective address generation result.
A mechanism for detecting a specific operand addressing method (hereinafter referred to as a specific addressing mode); and an effective address generation result or a modification in the copy register when the specific addressing mode is used. A control mechanism for writing the result of the quantity addition, a mechanism for storing the write history (hereinafter referred to as a copy valid bit), and an identification code of a register used as a base address register when the specific addressing mode is designated. A register to be stored (hereinafter, referred to as a copy register identification code latch); and a state in which the copy valid bit indicates that the copy register has been written (hereinafter, referred to as a valid state).・ Register identification code latch value and base address register A data bus for providing the effective address generator with the copy register value, rather than from a register file, if the data numbers match. Is done.

In a preferred embodiment of the present invention, the register identification code held by the copy register identification code latch is fixed in advance (hereinafter, the register specified by this identification code is referred to as a specific register), and all or part of the instruction code is stored. And a control mechanism for individually writing to the copy register and reading to the effective address generator only when it is detected that the specific register is used as the base address register.

Further, in another preferred embodiment of the present invention, when the identification code of the base address register is the identification code of the specific register, a mechanism for suppressing a latch operation to the copy register identification code latch, Only when the register is used as a base address register, there is provided a control mechanism for separately writing to a dedicated copy register and reading to an effective address generator.

Operation As described above, in the conventional effective address advance calculation type pipeline microprocessor, no countermeasures are taken against the register hazard generated in the effective address advance calculation stage.

Contrary to such prior art, the effective address pre-computation type pipeline microprocessor according to the present invention uses the auto-modify addressing mode for the preceding instruction and uses the auto-modify addressing mode for the subsequent instruction. When a modified register is used as the base address register, the effective address is generated by the preceding instruction and the modified value of the base address register calculated and held in the copy register is stored in the copy register. Has a mechanism to pre-supply as the base address register value of the effective address calculation by the instruction of (1).

In the microprocessor according to the present invention configured as described above, this occurs in the effective address pre-calculation stage of the subsequent instruction using the same register as the base address register as the general-purpose register used in the register indirect addressing with auto-modification of the preceding instruction. Register hazards can be effectively avoided with relatively small hardware.

Hereinafter, the present invention will be described in more detail with reference to the drawings. However, the following disclosure is merely an example of the present invention, and does not limit the technical scope of the present invention.

Embodiment 1 FIG. 1 is a block diagram showing a first embodiment of a pipeline microprocessor of an effective address preceding calculation type according to the present invention.

Note that this effective address preceding calculation type pipelined microprocessor has a stack pointer in a general-purpose register, and a register indirect addressing mode with post-increment and a register indirect addressing mode with pre-decrement using the stack pointer as a base address. It has two types of register indirect addressing functions with auto-modify.

As shown in FIG. 1, the effective address preceding calculation type pipeline microprocessor mainly includes an instruction decoder 11, an effective address calculation unit 12, and an instruction execution unit 13.

The effective address calculation unit 12 has the following elements. That is, in order to calculate the modified register value of the register used for the indirect addressing with auto-modification, a constant RO for outputting the amount of modification is used.
M16, an address adder 17 for adding the amount of modification to the data on the base register bus 24, and either one of the data on the base register bus 24 or the output of the address adder 17 is selected according to the operand address selection signal 35. And an effective address write-back bus 22 for guiding the address addition result from the address adder 17 to the copy address register 18, and a base which is a command from the instruction decoder unit 101. A base register multiplexer 19 multiplexes an output output from the general-purpose register file 26 in the instruction execution unit 13 via the base register bus 21 or an output of the copy address register 18 in response to the address register selection signal 33.

The instruction decode unit 11 is configured as follows. That is, it includes an instruction decoder 14, an instruction execution instruction information register 27, and a copy register valid bit 15. The instruction decoder 14 outputs a modify amount designation signal 31 for designating the output of the constant ROM 16. Further, the instruction decoder 14 specifies a copyright signal 34, a base register specifying signal 32 for specifying a general-purpose register to be used as a base address register, and a stack pointer to be copied as a base address register. And an operand address selection signal 35 indicating whether or not to calculate a register indirect address with pre-decrement.

Further, the instruction execution unit 13 includes a general-purpose register file 26 used as a base address register in the register indirect addressing mode. The modification and instruction execution information are set in the instruction execution designation information register 27 after the effective address calculation, and are specified by the instruction execution designation information 36 which is the output.

In the effective address preceding calculation type pipeline microprocessor according to the present invention configured as described above, usually, the effective address calculation of the register indirect addressing is as follows.
The output from the general-purpose register file 26 in the instruction execution unit 13 designated by the base register designation signal 32 is executed as a base address.

If the instruction specifies register indirect addressing with pre-decrement as the addressing mode,
Operand address selection signal 35 causes data on base address bus 24 to be output to operand address bus 23. On the other hand, when another addressing mode is specified, the output of address adder 17 is output to operand address bus 23. As output above, operand address select signal 35 is input to operand address multiplexer 25.

Further, separately from the above, in the case of the register indirect addressing mode with auto-modification, the modification amount is designated by the modification amount designation signal 31, and the constant ROM 16
And adds the data on the base address bus 24 to the address adder 17.

When the stack pointer is specified as the base address register for register indirect address calculation with auto-modify, the copy signal 34 is activated, and the data sent from the address adder 17 via the effective address write-back bus 22 is copied. At the same time as writing to the address register 18, the copy register valid bit 15 is activated.

Next, in a case where the stack pointer is used as a base address register in an instruction following the instruction,
As long as the copy register valid bit 15 is active, the output of the copy address register 18 is used as a substitute for the data on the base register bus 21, which is the output of the general-purpose register file 26.

Whether to use the data of the base register bus 21 or the output data of the copy address register 18 as the base address is determined by the logical product of the stack pointer use detection signal 37 and the copy register valid bit 15 and the base address register selection signal 33. Use the copy address register 18 as the base address register when it is active.

As described above, by selectively using the contents of the general-purpose register and the contents of the copy address register, the effective address preceding calculation type pipeline microprocessor of the present invention can
When calculating the register indirect address when using the stack pointer, there is no waiting due to the register hazard state.
Pipeline efficiency does not decrease.

As described above, the effective address pre-computation type pipeline microprocessor according to the first embodiment includes, in its effective address calculation unit, some specific registers in a general-purpose register file frequently used for addressing with auto-modify. Is provided with a copy address register that holds a predicted value of the modification result. Therefore, when the specific general-purpose register is specified to be used as the base address register of the register indirect addressing in the effective address preceding calculation stage of the subsequent instruction, the copy address register value in the effective address preceding calculation unit is used instead. Thus, a correct effective address value can be obtained.

In particular, by providing a copy of a register frequently used as a part of the base address register such as a stack pointer at the time of auto-modify addressing in the effective address calculation unit, the register in the effective address preceding calculation stage can be relatively small in hardware amount. Hazard generation can be suppressed, and a decrease in pipeline efficiency can be prevented.

Embodiment 2 FIG. 2 is a block diagram of a second embodiment in which the present invention is applied to an effective address pre-calculation type pipeline microprocessor. The components corresponding to the components shown in FIG. 5 are denoted by the same reference numerals.

The illustrated effective address pre-computation type pipeline microprocessor according to the second embodiment includes a copy register identification code latch 205 for storing a base address register identification code unit 502 and a copy register identification code latch 2.
An identification code comparison product 206 that compares the value held by 05 with the base address register identification code unit 502 and detects that they are equal.
And The illustrated effective address pre-computation pipelined microprocessor further includes a copy register 201 holding an effective address adder output 607, and a base register.
Base address holding the value on address bus 609, bypass register 209 and effective address adder 102
Output 607 and base address bypass register 209
And an effective address multiplexer 204 that selects one of the outputs from the effective address selection signal 601 output from the addressing mode decoder 107 and outputs it to the address converter 106. In addition, it includes a copy register output buffer 202, a register file output buffer 203, and a copy register valid bit 207.

A timing generator 208 is provided. The timing generator 208 includes a copy register identification code latch 205
Base during auto-modify addressing
A timing signal (copy register identification code latch signal 604) for latching the address register identification code, and the output 60 of the effective address adder 102 to the copy register 201
7 (copy register latch signal 603) and a set timing signal of copy register valid bit 207 (copy valid bit 207).
And a set signal 605). The initial state of the copy register valid bit 207 is invalid.

If an instruction sequence similar to that of the above-described conventional example is supplied to the effective address preceding calculation type pipeline microprocessor of the second embodiment, the value of the register r31 is read from the register file 104 in the effective address calculation stage of the instruction. The addressing signal is supplied to the base address bus 609 via the register file output buffer 203, and at the same time, the amount of modification is obtained from the constant ROM 103, added by the effective address adder 102, and transferred to the effective address output 505.
The mode decoder 107 outputs a modify amount designation signal 503 and an effective address selection signal 601.

At the same time, the timing generator 208 receives the auto-modify addressing detection signal 602, and outputs the effective address adder output 607 to the copy register 201.
Copy register latch signal 603
And outputs a copy register identification code latch signal 604 to store the base address register identification code specified by the instruction in the copy register identification code latch 205, and sets the copy register valid bit 207. Thus, a copy valid set signal 605 is output. FIG. 7 is a timing chart showing the relationship between each output of the timing generator 208 and the copy register valid signal 606.
Shown in the figure.

Next, the timing of the effective address calculation stage in the instruction will be described. The base address register identification code 502 in the instruction code 108 indicates the register r31 similarly to the instruction, and the copy register identification code latch 205
Since the value matches the value, the output of the identification code comparator 206 becomes active. The output of the identification code comparator 206 is ANDed with the copy register valid signal 606 to activate the copy register read signal 610, and the value of the copy register 201 is read to the base address bus 609. It is.

The copy register read signal 610 inhibits the output base address register value 506 from the register file 104 from being output on the base address bus 609 at the same time.

Here, since the value of the copy register 201 is a value obtained in advance of the instruction execution result, no register hazard occurs.

Also, since the instruction has post-modify addressing, the effective address select signal 601 is activated so that the effective address output 505 takes the value on the base address bus 609 via the base address bypass latch 209. Controls the address multiplexer 250 and provides an effective address adder at the end of the effective address calculation stage of the instruction.
The output 607 of 102 is relatched in the copy register 201, and the result of the post-modify addressing, that is, the value of the register r31 after execution of the instruction is obtained.

Thus, register hazard in the instruction as shown in the prior art is avoided, the effective address preceding calculation period of the instruction is shortened as shown in FIG. 7, and the vacancy of the instruction execution stage between instructions is eliminated. Is done.

Third Embodiment FIG. 3 is a block diagram of a third embodiment in which the present invention is applied to an effective address precalculation type pipeline microprocessor. The components corresponding to the components shown in FIG. 2 are denoted by the same reference numerals. In the third embodiment, the copy register identification code latch 205 and the identification code comparator 206 in the second embodiment are used. A specific register use detector that abolishes the copy register identification code latch signal 604 and instead detects the fixed use of the instruction code 108 by decoding the instruction code 108 to use the specific register in the register file 104 as the base address register. 301 is provided.

Only when a specific register is designated as the base address register, the output of the specific register use detector 301 becomes active, the timing generator 208 is activated, and the value of the copy register 201 is updated as in the first embodiment. An operation and a read operation on the base address bus 609 are performed.

Embodiment 4 FIG. 4 is a block diagram of a fourth embodiment in which the present invention is applied to an effective address pre-computation type pipeline microprocessor. The components corresponding to those shown in FIGS. 2 and 3 are denoted by the same reference numerals.

Effective address preceding calculation type pipeline of the fourth embodiment
The microprocessor includes a copy register identification code latch 205 and an identification code comparator 206 described in the second embodiment, and a specific register type detector 301 described in the third embodiment. A copy register 403 for a specific register for when specified as a register;
Copy register read buffer 40 for specific register
7, a specific register timing generator 401, a specific register copy valid bit 402, and a non-specific register copy register 406 for a case where the base address register is any register other than the specific register.
And unspecified copy register read buffer 408
And a non-specific register timing generator 404 and a non-specific register copy valid bit 405.

The specific register timing generator 401 is activated by the logical product of the output of the specific register use detector 301 and the auto-modify addressing detection signal 602, and the specific register copy / register / rutter signal 708 and the specific register copy -Output the valid set signal 709. Conversely, the non-specific register timing generator 404 outputs non-specific register copy register identification code latch signal 703, non-specific register copy valid set signal 702, non-specific register copy register latch signal 701 is suppressed by the output of the specific register use detector 301. Therefore, redundant storage of the preceding modify value of the specific register in the specific register copy register 403 and the non-specific register copy register 406 is avoided.

Reading of the base address register value from the register file 104 is performed by copying a specific register.
This is performed only when both the register read signal 706 and the non-specific register copy register read signal 707 are in the inactive state.

The basic operation of the fourth embodiment is the same as that of the above-described second and third embodiments except for the matters described above.

Effect of the Invention As described above, in the effective address pre-computation type pipeline microprocessor of the present invention, the register used as the base address register in the auto-modify addressing is used in the subsequent instruction.
Since a mechanism for avoiding register hazard when used as an address register is provided, it is possible to prevent a decrease in performance under the above conditions.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a pipeline microprocessor of an effective address preceding calculation type according to the present invention. FIGS. 2, 3 and 4 show Embodiment 2 of the present invention, respectively.
FIG. 3 is a block diagram illustrating a main part related to effective address advance calculation of an effective address advance calculation type pipeline microprocessor according to 3 and 4. FIG. 5 is a block diagram for explaining the main part related to the effective address advance calculation of the effective address advance calculation type pipeline microprocessor according to the prior art. FIG. 6 is a timing chart of the effective address calculation and the instruction execution of the prior art effective-precision pipeline microprocessor. FIG. 7 is a timing chart of the effective address calculation and the instruction execution of the effective address preceding calculation type pipeline microprocessor according to the present invention. FIG. 8 is an instruction sequence used to show the result of the embodiment of the present invention. [Main Reference Numbers] 11: Instruction decoder, 12: Effective address calculation unit, 13: Instruction execution unit, 14: Instruction decoder, 15: Copy register valid bit, 16, 103: Constant ROM 17, 102: Address adder 18: Copy address register, 19: Base register multiplexer, 25: Operand address multiplexer, 26, 104: Register file, 27: Instruction execution designation information register, 21: Base register bus 22, effective address write-back bus, 23, operand address bus, 24, base address bus, 32, base register designation signal, 33, base address register selection signal, 34, copyright signal, 35 ... Operand address selection signal, 36 ... Instruction execution designation information, 37 ... Stack pointer use detection signal 105 ... Base -Address register decoder 106-Address converter 107-Addressing mode decoder 108-Instruction code 201-Copy register 204-Effective address multiplexer 205-Copy register identification code latch 206- Identification code comparator 207… Copy register valid bit 208… Timing generator 209… Base address bypass register 301… Specific register use detector 401… Specific register timing generator 402… Copy valid bit for specific register 403: Copy register for specific register 404: Timing generator for non-specific register 405: Copy valid bit for non-specific register 406: Copy register for non-specific register 407 …… Specified register copy register read buffer 408 …… Unspecified register Copy register read
Buffer 501: Addressing mode description unit 502: Base address register identification code unit 503: Modification amount designation signal 505: Effective address output 506: Base address register value 601: Effective address selection signal 602 …… Auto-modify addressing detection signal 603 …… Copy register latch signal 604 …… Copy register identification code latch signal 605 …… Copy valid set signal 606 …… Copy register valid signal 607 …… Effective Address adder output 609: Base address bus 610: Copy register read signal 901: Instruction execution unit

Claims (1)

(57) [Claims] 1. A register file that can be used as a base address of an operand address, and an effective address of an operand is calculated and generated prior to execution of an instruction by using an arbitrary register in the register file as a base address register. An effective address generator, a copy register that selects and holds one of the effective address generation result and a modification amount addition result obtained by adding a constant value to the effective address generation result, and a specific operand address designation method. A control mechanism for writing an effective address generation result or a modification amount addition result to the copy register when the specific operand addressing method is used; and a history storage mechanism for storing a write history of the write control mechanism. The specific operand addressing method An identification code storage register for storing an identification code of a register to be used as a base address register, wherein the history storage mechanism indicates that the copy register has been written, and the identification code storage register And a data bus for supplying the value of the copy register to the effective address generator instead of from the register file when the value of the base address register number matches the effective address pre-calculation type. Pipeline microprocessor.