JP2569531B2 - Memory control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial application field) The present invention relates to a memory control circuit, and in particular, to a memory control circuit immediately before a preceding one of a row address selection signal and a column address selection signal (hereinafter referred to as a row address selection signal). The present invention relates to a memory control circuit in a semiconductor memory in which a row address line is precharged by a precharge signal whose pulse width is determined by a trailing edge in a memory cycle and a leading edge in the memory cycle.

Here, the row address selection signal and the column address selection signal
Since these are usually called RAS timing and CAS timing, respectively, these names are used in the following description.

(Prior Art) Conventional memory control circuits of this type include a read operation timing generation circuit for generating a timing signal required for a read operation, and a write operation timing generation circuit for generating a timing signal required for a write operation. A request reception control circuit that returns an accept when an external memory request is received, thereby activating a read operation timing generation circuit or a write operation timing generation circuit in response to an input command; and the semiconductor memory is in an operating state. Sometimes with a busy control circuit that generates a cycle busy signal,
The request acceptance control circuit determines whether or not to accept the request based on the cycle busy signal. As is well known, the above-mentioned timing includes a RAS timing, a CAS timing, a precharge signal, a write enable signal, a read strobe signal, and the like.

(Problems to be Solved by the Invention) Generally, the write data has a large load on the output circuit, so that the transfer time is longer than that of the address and the command, and the delay time from the return of the accept becomes longer. The recycle time is longer in the write operation than in the read operation.

That is, during the write operation, there is a time during which the input of the write data is waited during the memory cycle time, and during that time, a useless time elapses. Therefore, in the case where the writing operation is continuously performed, it seems that the next memory cycle can be advanced by the waiting time. However, in the above-described conventional configuration, the continuous writing operation is first performed. If there is no means for detecting and even if the start of the subsequent write cycle is to be advanced, the request cannot be accepted because the cycle busy signal has been activated by the immediately preceding write cycle. However, even if the request is accepted, the RAS timing is the same between the write operation and the read operation, so that the pulse width of the precharge signal in the subsequent write cycle becomes narrower, resulting in a precharge failure. In the end, it is not possible to take advantage of the above-mentioned opportunity, and it is said that the write memory cycle longer than the read cycle time will be repeated. There is a problem.

An object of the present invention is to provide a memory control circuit capable of shortening a memory cycle time when a write cycle is continuous.

(Means for Solving the Problem) The circuit according to the present invention comprises a precharge in which a pulse width is determined by a trailing edge in a memory cycle immediately before a preceding one of row or column address selection signals and a leading edge in the next memory cycle. In a memory control circuit for a semiconductor memory in which a corresponding row or column address line is precharged by a signal, when an external request is received, the input of an address, a command and write data is induced to start the operation of the semiconductor memory. Request accepting means; continuous write detecting means for detecting a write cycle following the write cycle before input of an address or the like; and a semiconductor memory operating when a continuous write cycle is detected. Busy canceling means for enabling the accepting means to accept the request at that time; And delay means for delaying the leading edge of the RAS timing by a delay time of write data corresponding to an address and a command during operation, as compared with a read operation.

(Example) Next, an example of the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram showing one embodiment of the present invention.

Referring to FIG. 1, in the present embodiment, a request acceptance control circuit 1, a busy control circuit 2, a read operation timing generation circuit 3, a write operation timing generation circuit 4, a memory matrix circuit 5, a NAND gate 6, an AND gate 7, and OR gate 8. The read cycle time and the write cycle time of the semiconductor memory are 2T and 25T, respectively (T is a clock cycle time).

The request reception control circuit 1 receives the request 10 from the external device only when the busy signal 19 is “0”, returns the accept signal 13, and outputs the memory activation signal 14 to the busy control circuit 2.

The external device that has received the accept 13 outputs the address, the command 11, and the command 11 together with the write data (both not shown) during the write operation. As described above, the write data is delayed from the address and the command 11, and the delay time is 0.5T.

The request reception control circuit 1 outputs a read instruction signal 15 in accordance with the instruction of the command 11 to the read operation timing generation circuit 3.
In addition, a write instruction signal 16 is output to write operation timing generation circuit 4, and a write operation signal 17 is output to NAND gate 6 when a write operation is instructed by command 11. The write operation signal 17 is set so as to be delayed from the request 10 by 2.5T which is a result of subtracting 0.5T which is a delay time for an address of write data from the conventional write cycle time 3T.

When the read instruction signal 15 is input, the read operation timing generation circuit 3 generates timings required for the memory matrix circuit 5 to perform a read operation, for example, RAS timing 21, CAS
A timing, a precharge signal, a read strobe signal and the like are generated and supplied to the memory matrix circuit 5.

Further, when the write instruction signal 16 is input, the write operation timing generation circuit 4 generates a timing necessary for the memory matrix circuit to perform the write operation, for example, the RAS timing 22,
A CAS timing, a precharge signal, a write enable signal 23, etc. are generated and supplied to the memory matrix circuit 5. The RAS timing 22 generated at this time has a leading edge delayed by 0.5 T of the write data delay time from the RAS timing 21 in the read operation.

The memory matrix circuit, for example, like 1MDRAM,
A large number of MOS dynamic memory cells are arranged in a matrix, and access is made to one designated by a row address signal and a column address signal activated at RAS timings 21 and 22 and CAS timing, respectively.

In such a memory matrix circuit 5, since a large number of "half-selected" memory cells are connected to one row address line or column address line, the load becomes heavy. In this case, the pre-charge signal is charged in advance, and the pulse width of the pre-charge signal is generally determined by the trailing edges of the RAS timings 21 and 22 in the immediately preceding memory cycle and the RAS timing in the memory cycle. Designed to be defined with 21,22 leading edges.

The busy control circuit 2 is a cycle busy signal which is "1" until the memory matrix circuit 5 is finished operating after the read instruction signal 15 or the write instruction signal 16 is generated, and is "0" during other periods. 18 is generated and output to the AND gate 7.

On the other hand, the NAND gate 6 outputs the request 10 during the write operation.
Write designation signal 12 input from an external device at the same time as input
And the write operation signal 17 to perform a NAND operation. As described above, the write operation signal 17 is generated 2.5 T after the request 10 in the write operation. Therefore, if the input interval of the request 10 in the write operation is set to 2.5 T, the output 20 Becomes "0" only during the pulse width of the write designation signal 12 (designed to have the same waveform as the write operation signal 17). In other words, the NAND gate 6 detects the write operation instruction and indicates it by outputting "0".

The AND gate 7 has a NAND gate output 20 as described above.
AND operation with the cycle busy signal 18 and supplies the result to the request reception control circuit 1 as a busy signal 19.

As is clear from the above-described generation process, the busy signal 19 is generated during the operation of the memory matrix circuit 5 after the output of the read instruction signal 15 or the write instruction signal 16.
When a request with a subsequent write operation instruction is input,
In the meantime, it can be said that the cycle busy signal 18 is forcibly released.

As described above, when the request 10 is input, the request acceptance control circuit 1 accepts and outputs the accept 13 and the like only when the busy signal 19 is “0”, so that the operation of the NAND gate 6 and the AND gate 7 Accordingly, when the writing operation is continuous, for example, when a program is loaded from an external storage device such as a floppy disk or the like, each subsequent writing cycle can be advanced by 0.5T.

Next, the operation of the present embodiment will be described with reference to the time charts shown in FIG. 2 and FIG.

Figure 2 is (a 2T) read cycle from the timing T ₄ Following write cycle (a 3T) from the timing T ₁ is the case where continued.

When the request 10 at the timing T ₁ is accepted, the request reception control circuit 1 sends back the accept 13 at the timing T _12. As a result, when the command 11 or the like is sent from the request source, the request reception control circuit 1 sends the memory activation signal 14 to the busy control circuit 2,
Write instruction signal 16 is output to write operation timing generation circuit 4.

As a result, although busy control circuit 2 to cycle the busy signal 18 "1" at timing T _2, for a memory cycle just before at this time is a read operation specified, the output of the NAND gate 6 20 is "1" , Busy signal 19 is also "1", so that the request acceptance control circuit 1 does not accept the request.

Write operation timing generation circuit 4, the write instruction signal 16 is inputted, and generates a write enable 23 or the like in the RAS timing 22 and the timing T ₃ at the timing T _23, the memory matrix the write data not shown The circuit 5 is written. It can be seen that the leading edge of the RAS timing 22 is delayed by 0.5T from that of the RAS timing 21 at the time of the read operation described below.

On the other hand, the write designation signal 12 at the timing T ₁ is being input to the NAND gate 6, in this case, the write operation signal 17
Is not entered, so the NAND condition does not hold. Also,
Request reception control circuit 1 is a write operation signal 17 and write designation signal 12 of the waveform reached from the timing T ₁ to time T ₃₄ after 2.5T output to the NAND gate 6, the write designation signal 12 at this time is Since it has disappeared, the NAND condition does not hold. Therefore, the busy signal 19 becomes "1" at the timing T ₂ are to sustain state until the timing T ₄ "1", it will not be accepted by the input request 10 during this period.

Write cycle described above is completed at the timing T _4,
Since the busy signal 19 becomes "0", the request 10 is accepted. Incidentally, since the request of this time no write designation signal with, only present between still 0.5T from the timing T _4, the write operation signal in the immediately preceding write cycle 17
Does not satisfy the NAND condition.

In such a read cycle as well, in the same manner as in the write cycle, accept 13 and memory activation instruction 14 are output, and guidance of command 11 and the like and cycle busy signal 1 are output.
8, the busy signal 19 rises to "1", but the write operation signal 1
7 is not output, and the read operation signal generating circuit 3 is activated by the read instruction signal 15. RAS timing 21 at this time is a timing T ₅ after 1T from the timing T ₄ is a time of the request accepted.

As described below, when the writing operation is not continuous such as reading operation → writing operation → reading operation, the writing cycle time is 3T, and there is no effect of the present invention.

FIG. 3 shows a time chart when the writing operation is continued.

In this case, for example, the write designation signal 12 coming input at timing T _34, the phase matches with the write operation signal 17 and the timing T ₃₄ in the LSP starts have been write cycles from the timing T _1, output since 20 becomes "0" of the NAND gate 6, the busy signal 19 are "0", and the request 10 is accepted at the timing T _34, that can start a write cycle from the timing T ₃₄ after 2.5T from the timing T ₁ Become.

This operation of the memory matrix circuit 5 by the write cycle have the LSP starts a write cycle from the start timing T ₁ is still subsequently have though, even if starting the next write cycle at time T _34, need to return or the like of the accept 13 at the timing T _4, because are not started quickly the operation that affects the operation of the memory matrix circuit 5 above.

Note that the RAS timing 22 should be noted here. As described above, the precharge signal is determined by the trailing edge of the RAS timing in the immediately preceding memory cycle and the leading edge of the RAS timing in the memory cycle.
If the write cycle time is reduced without taking care of the memory matrix circuit 5, the trailing edge of the RAS timing 22
Although the operation is unchanged, only the leading edge is advanced, so that the pulse width of the precharge signal is narrowed and the row address line cannot be charged well, which causes a malfunction.

In this embodiment, in view of this point, the trailing edge of the RAS timing 22 generated by the write operation timing generation circuit 4 is delayed by 0.5T, that is, the time required to reduce the write cycle time, whereby the precharge signal is reduced. The pulse width remains unchanged.

(Effects of the Invention) According to the present invention, as described in detail above, means for detecting a subsequent write cycle before the operation of the semiconductor memory starts, and when the detection is detected, the semiconductor memory is in an operating state. Means for receiving a request even when the request is received, means for starting operation of the semiconductor memory when the request is received, and delaying the leading edge of the RAS timing by the write data delay time in the write operation during the read operation. By providing the means, when the write cycle is continuous, the request can be accepted even when the semiconductor memory is in operation, and the pulse width of the precharge signal can be sufficiently ensured. The start of the write cycle can be hastened, and the total write cycle time except for the last write cycle can be reduced.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention, and FIGS. 2 and 3 show time charts of the embodiment. 1 request reception control circuit, 2 busy control circuit, 3 read operation timing generation circuit, 4 write operation timing generation circuit, 5 memory matrix circuit,
6 ... Nand gate, 7 ... And gate, 8 ... OR gate.

Claims (1)

(57) [Claims] 1. A row or column address line is precharged by a precharge signal whose pulse width is determined by a trailing edge in a memory cycle immediately preceding a preceding row or column address selection signal and a leading edge in the memory cycle. Request receiving means for initiating the input of an address, a command, and write data when an external request is received to start the operation of the semiconductor memory; Continuous write detecting means for detecting a write cycle before the input guidance, and when the continuous write cycle is detected, the request receiving means detects the request at that time even if the semiconductor memory is in the operating state. Busy canceling means for making it possible to accept the address and frame during a write operation. And a delay means for delaying the leading edge by a delay time of write data with respect to a command in the read operation.