JP2568495B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2568495B2 JP2568495B2 JP60235936A JP23593685A JP2568495B2 JP 2568495 B2 JP2568495 B2 JP 2568495B2 JP 60235936 A JP60235936 A JP 60235936A JP 23593685 A JP23593685 A JP 23593685A JP 2568495 B2 JP2568495 B2 JP 2568495B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- ground
- wafer
- frequency characteristics
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 34
- 239000000758 substrate Substances 0.000 claims description 23
- 239000004020 conductor Substances 0.000 claims description 14
- 238000007689 inspection Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 3
- 239000000523 sample Substances 0.000 description 20
- 238000005259 measurement Methods 0.000 description 13
- 238000011156 evaluation Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、マイクロ波半導体装置に関し、特にその高
周波特性の測定において、精密な測定を行うために必要
なグランドのとり方を改良したものに関するものであ
る。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microwave semiconductor device, and more particularly to a device having improved grounding required for precise measurement in measuring high-frequency characteristics thereof. It is.
従来、例えば10GHz程度の高周波領域で動作するトラ
ンジスタやICなどの半導体デバイスの高周波特性を評価
するには、ウエハーをチップに切り出し、該チップをパ
ッケージやチップキャリアに組込み、その後評価用治具
にマウントし、測定する方法が一般的であった。従っ
て、マイクロ波デバイスの評価には相当の時間と費用を
必要とし、さらに組立に伴うワイヤの寄生インダクタン
スや、上記治具の接続部分の不具合等が測定結果に悪影
響を与え、不正確さを招くなどの不具合があった。Conventionally, to evaluate the high-frequency characteristics of semiconductor devices such as transistors and ICs operating in a high-frequency range of about 10 GHz, for example, a wafer is cut into chips, the chips are assembled into a package or chip carrier, and then mounted on an evaluation jig. Then, the method of measuring was common. Therefore, the evaluation of the microwave device requires a considerable amount of time and cost, and furthermore, the parasitic inductance of the wire associated with the assembly and the failure of the connection portion of the jig have a bad influence on the measurement result, resulting in inaccuracy. There was a problem such as.
このような不具合を解決するため、最近、ウエハ状態
で高周波特性の評価が可能なプローブヘッドが開発され
普及し始めている。In order to solve such problems, probe heads capable of evaluating high-frequency characteristics in a wafer state have recently been developed and started to spread.
第３図に示すものはこのような高周波プローブの一例
で、これはプローブ先端までコプラーナ線路が形成さ
れ、特性インピーダンスが50Ωとなるように設計されて
いる。第３図（ａ）は上記プローブヘッドの斜視図、第
３図（ｂ）はその裏面図である。図中１はプローブヘッ
ドの支持体で例えばアルミナやサフアイヤ等の誘電体基
板である。2,3,4は半導体チップに接触する部分であ
り、２は信号用プローブ、3,4はグランド用プローブで
ある。裏面には信号線20、グランド線30,40が特性イン
ピーダンス50Ωのコプラーナ線路を形成するように金属
パターンが形成されており、これは点21,31,41付近で同
軸コネクタ５に接続され、該コネクタ５からはケーブル
により測定器に接続されている。このようなプローブを
用いればプローブの先端まで特性インピーダンスが50Ω
の線路で信号を送ることができ、精度の高い測定が可能
である。しかしながら、第３図に示すプローブヘッドで
測定を行なうためには、信号用プローブ２、グランド用
プローブ3,4が接触できるパッドがチップ上に形成され
ていなければならない。FIG. 3 shows an example of such a high-frequency probe, which is designed such that a coplanar line is formed up to the tip of the probe and the characteristic impedance is 50Ω. FIG. 3A is a perspective view of the probe head, and FIG. 3B is a rear view thereof. In the figure, reference numeral 1 denotes a support for a probe head, which is a dielectric substrate such as alumina or sapphire. Reference numerals 2, 3, and 4 denote portions that come into contact with the semiconductor chip, reference numeral 2 denotes a signal probe, and reference numerals 3 and 4 denote ground probes. On the back surface, a metal pattern is formed such that the signal line 20 and the ground lines 30 and 40 form a coplanar line having a characteristic impedance of 50Ω, which is connected to the coaxial connector 5 near points 21, 31, and 41, and The connector 5 is connected to a measuring instrument by a cable. With such a probe, the characteristic impedance up to the tip of the probe is 50Ω
Signal can be sent through the line, and highly accurate measurement is possible. However, in order to perform measurement with the probe head shown in FIG. 3, pads that the signal probe 2 and the ground probes 3 and 4 can contact must be formed on the chip.
第２図はマイクロストリップ線路を用いて半導体チッ
プ上にマイクロ波回路を構成したMMIC（Monolithic Mic
rowave IC）を示す図であり、この図ではトランジスタ
などの部分は図示せず、単なる伝送線路のみを示してい
る。普通MMICの場合は、この図のチップ上に、トランジ
スタ、抵抗、コンデンサ、他の回路要素が集積されてい
る。図中６は例えば半絶縁性GaAs基板、７はマイクロス
トリップ線路で、金属薄膜で形成されている。８はグラ
ンド部（地導体）であり、チップ裏面に形成された金属
薄膜である。FIG. 2 shows an MMIC (Monolithic Mic) in which a microwave circuit is formed on a semiconductor chip using a microstrip line.
FIG. 2 is a diagram illustrating a rowave IC), in which a portion such as a transistor is not shown, and only a mere transmission line is shown. In the case of an ordinary MMIC, transistors, resistors, capacitors, and other circuit elements are integrated on the chip shown in this figure. In the figure, 6 is, for example, a semi-insulating GaAs substrate, and 7 is a microstrip line, which is formed of a metal thin film. Reference numeral 8 denotes a ground portion (ground conductor), which is a metal thin film formed on the back surface of the chip.
従来の装置は以上のように構成されているので、グラ
ンド部はチップ裏面にあり、チップ上面には無いため、
第３図に示すプローブの適用が出来ないという問題点が
あった。Since the conventional device is configured as described above, the ground portion is on the back surface of the chip and not on the top surface of the chip,
There was a problem that the probe shown in FIG. 3 could not be applied.
本発明は上記のような問題点を解消するためになされ
たもので、ウエハ状態で高周波特性の評価が可能なプロ
ーブヘッドにより、その高周波プロービングが可能な半
導体装置を得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of high-frequency probing with a probe head capable of evaluating high-frequency characteristics in a wafer state.
本発明に係る半導体装置は、ウエハ処理プロセスによ
り、ウエハ状態で基板の各チップ領域にモノリシックに
マイクロ波回路を形成し、各チップ領域を半導体チップ
に切り出してなる半導体装置において、上記半導体チッ
プを、該半導体チップを構成するチップ基板の裏面に形
成された地導体と、上記チップ基板の表面側に形成され
たマイクロストリップ線路と、上記チップ基板表面の、
マイクロストリップ線路の入力および出力パッド付近に
形成された検査用グランドパッドと、上記チップ基板側
面に形成され、上記基板裏面側の地導体と基板表面の上
記検査用グランドパッドとにつながる側面導体とを有す
る構造としたものである。The semiconductor device according to the present invention is a semiconductor device in which a microwave circuit is monolithically formed in each chip region of a substrate in a wafer state by a wafer processing process, and each chip region is cut into semiconductor chips. A ground conductor formed on the back surface of the chip substrate constituting the semiconductor chip, a microstrip line formed on the front surface side of the chip substrate, and
An inspection ground pad formed near the input and output pads of the microstrip line, and a side conductor formed on the chip substrate side surface and connected to the ground conductor on the back surface of the substrate and the inspection ground pad on the substrate surface. It has a structure having.
この発明においては、半導体チップを構成するチップ
基板を、その表面のマイクロストリップ線路の入力およ
び出力パッド付近に検査用グランドパッドを有し、かつ
チップ基板側面に基板裏面の地導体と基板表面の検査用
グランドパッドとにつながる側面導体を有する構造とし
たから、ウエハ状態で上記半導体チップのマイクロ波回
路と高周波プローブヘッドとの接続が可能となり、これ
によりマイクロ波回路の高周波特性の評価は、上記プロ
ーブヘッドをウエハにおける個々の半導体チップのグラ
ンドパッド及びマイクロストリップ線路の入力および出
力パッドに接触させるだけで、半導体チップをパッケー
ジに組み込んだり評価用治具にマウントしたりすること
なく簡単に行うことができ、測定時間の短縮，測定費用
の削減，さらには測定精度の向上を図ることができる。According to the present invention, a chip substrate constituting a semiconductor chip is provided with an inspection ground pad near input and output pads of a microstrip line on the surface thereof, and a ground conductor on the back surface of the substrate and inspection of the substrate surface on the side surface of the chip substrate. The structure having side conductors connected to the ground pad for use makes it possible to connect the microwave circuit of the semiconductor chip and the high-frequency probe head in a wafer state, thereby evaluating the high-frequency characteristics of the microwave circuit by using the probe By simply bringing the head into contact with the ground pads of the individual semiconductor chips on the wafer and the input and output pads of the microstrip line, the operation can be easily performed without mounting the semiconductor chips in a package or mounting on an evaluation jig. , Measurement time reduction, measurement cost reduction, and measurement It is possible to improve the accuracy of.
また、上記個々の半導体チップの高周波特性の評価が
ウエハ状態で行われることから、ウエハ内での個々の半
導体チップの位置とその評価結果とに基づいてウエハ内
における高周波特性の分布，つまりウエハ内の場所によ
る高周波特性の違い等を求めることも可能である。In addition, since the evaluation of the high-frequency characteristics of the individual semiconductor chips is performed in a wafer state, the distribution of the high-frequency characteristics in the wafer, that is, the distribution of the high-frequency characteristics in the wafer, is determined based on the position of each semiconductor chip in the wafer and the evaluation result. It is also possible to obtain a difference in high frequency characteristics depending on the location.
以下、本発明の一実施例を図について説明する。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例による半導体装置を示し、
図において、６〜８は第２図と同一のものであり、９は
チップ上面に設けられたグランド用パッド,10,11はチッ
プ側壁にメッキ法などで形成されたメタライズ部分（側
面導体）であり、これは上記グランド用パッド９と裏面
グランド部（地導体）８とを接続している。ここで上記
メタライズ部10は線路７に平行なチップ側面のメタライ
ズ部であり、上記メタライズ部11は、線路７に垂直な側
面のメタライズ部であり、このように上面グランドパッ
ド９と裏面グランド部８とを接続するメタライズ部はい
ずれの側面に設けたものでもよい。FIG. 1 shows a semiconductor device according to an embodiment of the present invention,
In the drawing, 6 to 8 are the same as those in FIG. 2, 9 is a ground pad provided on the upper surface of the chip, and 10 and 11 are metallized portions (side conductors) formed on the chip side wall by plating or the like. This connects the ground pad 9 and the back surface ground portion (ground conductor) 8. Here, the metallized portion 10 is a metallized portion on a side surface of a chip parallel to the line 7, and the metallized portion 11 is a metallized portion on a side surface perpendicular to the line 7. May be provided on any side surface.
このような本実施例では、グランド用パッドを入力お
よび出力用パッド付近に設けたので、第３図のプローブ
ヘッドの端子2,3,4をそれぞれ、チップ上のパッド7,9に
接触させることができ、これにより半導体チップをパッ
ケージや測定治具中に組み込むことなく簡単に行うこと
ができ、測定時間の短縮，測定費用の削減，さらには測
定精度の向上を図ることができる効果がある。In this embodiment, since the ground pads are provided near the input and output pads, the terminals 2, 3, and 4 of the probe head shown in FIG. 3 must be brought into contact with the pads 7 and 9 on the chip, respectively. Accordingly, the semiconductor chip can be easily manufactured without incorporating the semiconductor chip in a package or a measuring jig, and there is an effect that measurement time can be reduced, measurement cost can be reduced, and measurement accuracy can be improved.
また、上記個々の半導体チップの高周波特性の評価が
ウエハ状態で行われることから、ウエハ内での個々の半
導体チップの位置とその評価結果とに基づいてウエハ内
における高周波特性の分布，つまりウエハ内の場所によ
る高周波特性の違い等を求めることも可能である。In addition, since the evaluation of the high-frequency characteristics of the individual semiconductor chips is performed in a wafer state, the distribution of the high-frequency characteristics in the wafer, that is, the distribution of the high-frequency characteristics in the wafer, is determined based on the position of each semiconductor chip in the wafer and the evaluation result. It is also possible to obtain a difference in high frequency characteristics depending on the location.
なお、上記実施例ではICを例にとって説明したが、本
発明は単体トランジスタにも適用できることは言うまで
もない。In the above embodiment, an IC has been described as an example, but it goes without saying that the present invention can be applied to a single transistor.
以上のように、本発明に係る半導体装置によれば、半
導体チップを構成するチップ基板を、その表面のマイク
ロストリップ線路の入力および出力パッド付近に検査用
グランドパッドを有し、かつ上記基板側面に、基板裏面
の地導体の基板表面の検査用グランドパッドとにつなが
る側面導体を有する構造としたので、ウエハ状態で上記
半導体チップのマイクロ波回路と高周波プローブヘッド
との接続が可能となり、これによりマイクロ波回路の高
周波特性の評価は、上記プローブヘッドをウエハにおけ
る個々の半導体チップの検査用グランドパッド及びマイ
クロストリップ線路の入力および出力パッドに接触させ
るだけで、半導体チップをパッケージに組み込んだり評
価用治具にマウントしたりすることなく簡単に行うこと
ができ、測定時間の短縮，測定費用の削減，さらには測
定精度の向上を図ることができる効果がある。As described above, according to the semiconductor device of the present invention, the chip substrate forming the semiconductor chip has the inspection ground pads near the input and output pads of the microstrip line on the surface thereof, and is provided on the side surface of the substrate. Since the structure has side conductors that connect the ground conductor on the back surface of the substrate to the inspection ground pad on the surface of the substrate, the microwave circuit of the semiconductor chip can be connected to the high-frequency probe head in a wafer state. The evaluation of the high-frequency characteristics of the wave circuit can be performed by simply bringing the probe head into contact with the inspection ground pad of each semiconductor chip on the wafer and the input and output pads of the microstrip line, and incorporating the semiconductor chip into a package or a jig for evaluation. Measurement can be easily performed without mounting Condensation, reduction of measurement costs, there is an effect that it is possible to further improve the measurement accuracy.
また、上記個々の半導体チップの高周波特性の評価が
ウエハ状態で行われることから、ウエハ内での個々の半
導体チップの位置とその評価結果とに基づいてウエハ内
における高周波特性の分布，つまりウエハ内の場所によ
る高周波特性の違い等を求めることも可能である。In addition, since the evaluation of the high-frequency characteristics of the individual semiconductor chips is performed in a wafer state, the distribution of the high-frequency characteristics in the wafer, that is, the distribution of the high-frequency characteristics in the wafer, is determined based on the position of each semiconductor chip in the wafer and the evaluation result. It is also possible to obtain a difference in high frequency characteristics depending on the location.
第１図は本発明の一実施例による半導体チップの構成を
示す図、第２図は従来の半導体チップの構成を示す図、
第３図は高周波プローブの一例を示す図である。 図中、６は半導体基板、７はマイクロストリップ線路、
８はグランド部、９はグランド用パッド、10,11はメタ
ライズ部（側面導体）である。 なお図中同一符号は同一又は相当部分を示す。FIG. 1 is a diagram showing a configuration of a semiconductor chip according to one embodiment of the present invention, FIG. 2 is a diagram showing a configuration of a conventional semiconductor chip,
FIG. 3 is a diagram showing an example of a high-frequency probe. In the figure, 6 is a semiconductor substrate, 7 is a microstrip line,
8 is a ground portion, 9 is a ground pad, and 10 and 11 are metallized portions (side conductors). In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (1)
基板の各チップ領域にモノリシックにマイクロ波回路を
形成し、各チップ領域を半導体チップに切り出してなる
半導体装置において、 上記半導体チップは、 該半導体チップを構成するチップ基板の裏面に形成され
た地導体と、 上記チップ基板の表面側に形成されたマイクロストリッ
プ線路と、 上記チップ基板表面の、マイクロストリップ線路の入力
および出力パッド付近に形成された検査用グランドパッ
ドと、 上記チップ基板側面に形成され、上記基板裏面側の地導
体と上記検査用グランドパッドとにつながる側面導体と
を有するものであることを特徴とする半導体装置。1. A semiconductor device in which a microwave circuit is monolithically formed in each chip region of a substrate in a wafer state by a wafer processing process, and each chip region is cut into semiconductor chips. A ground conductor formed on the back surface of the chip substrate, a microstrip line formed on the front side of the chip substrate, and an inspection formed near the input and output pads of the microstrip line on the surface of the chip substrate. A semiconductor device comprising: a ground pad for use; and a side conductor formed on a side surface of the chip substrate and connected to a ground conductor on the back surface side of the substrate and the ground pad for inspection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60235936A JP2568495B2 (en) | 1985-10-21 | 1985-10-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60235936A JP2568495B2 (en) | 1985-10-21 | 1985-10-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6294965A JPS6294965A (en) | 1987-05-01 |
| JP2568495B2 true JP2568495B2 (en) | 1997-01-08 |
Family
ID=16993420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60235936A Expired - Lifetime JP2568495B2 (en) | 1985-10-21 | 1985-10-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2568495B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6341041A (en) * | 1986-08-06 | 1988-02-22 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0215652A (en) * | 1988-07-01 | 1990-01-19 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH0467657A (en) * | 1990-07-09 | 1992-03-03 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor element mounting jig |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5099870U (en) * | 1974-01-17 | 1975-08-19 | ||
| JPS59169061U (en) * | 1983-04-28 | 1984-11-12 | 株式会社村田製作所 | High frequency circuit board |
-
1985
- 1985-10-21 JP JP60235936A patent/JP2568495B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6294965A (en) | 1987-05-01 |
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