JP2567530B2 - CMOS logic circuit - Google Patents

Description

Detailed Description of the Invention

The present invention relates to a complementary metal oxide semiconductor (CMO).
S) technology for large scale integrated circuits (LSIs) and very large scale integrated circuits (VLSIs). More particularly, the present invention relates to an improved CMOS design which combines a latch and shift register to remove the timing constraints inherent in conventional designs of such circuits.

The central processing unit (CPU) of large computer systems basically consists of latches, combinatorial logic circuits and clock systems. Latches correspond to the size of words used in computer systems and are often arranged in groups called registers (a "word" is a predetermined number of bits). A combinational logic circuit, that is, a logic circuit that does not store data is provided between the groups of latches.

At the end of one clock cycle and also at the beginning of the next clock cycle, the data at the output of the combinational logic circuit is stored in a group of latches. This data appears at the output of a group of latches, that is, at the input of a combinational logic circuit coupled to the output of this group of latches. This logic circuit performs the designed logic function on the data and at the end of the clock cycle the output of the combinational logic circuit is stored in the next group of latches. This process is repeated many times as the computer system operates. That is, the data is processed by the combinational logic circuit, stored, and passed to the next group of combinational logic circuits,
It is processed and stored.

With the advent of LSI and VLSI technology, computer systems have become physically smaller. However, the availability of large numbers of logic circuits in a small package has allowed computer designers to include features in their design that increase system reliability and testability. Such features were considered too expensive before LSI and VLSI were available.

One feature common to today's large computer systems is the "scannable latch." Scannable latches include latches that can be converted into a series of shift registers by using an appropriate clock signal. This scannable latch allows "scanning" by shifting out for examination of the contents of the shift register being formed. The shift register, or latch, can also be loaded with new content by shifting new data into it.

When the latches described above are incorporated in the design, selected groups can be interconnected to form a shift register. Precise timing signals can stop the CPU from working at any time and then shift out to the operator's computer console for checking the contents of the latch, or latching a known group of data from the computer console. You can also shift to. Needless to say, such capabilities represent a powerful feature for testing large computers. For example, if a floating point divide instruction is determined to be giving an incorrect result, the latch associated with it can be loaded with a known set of numbers by shifting the known number. The CPU can then perform calculations one cycle at a time. At the end of each cycle, the contents of the latch can be shifted out and checked. When the latch has the correct result, it can shift this result back into the latch and allow the CPU to execute the next cycle. This process continues until a false result is detected. In this way, the circuit corresponding to the incorrect result can be easily found and replaced. On the other hand, without features for such testing, removing defective circuits would be extremely difficult due to the large number of circuits and the large number of clock cycles associated with floating point split computations. Become.

CMOS VLSI technology makes it possible to fabricate a general purpose register (GPR) on a single chip, for example, filed February 22, 1983 and assigned to the same assignee as the present application. Agent Dockett No. Pending U.S. Patent Application No. CRC-113. 06/466602 "Multi-port general-purpose CM
See OS Register. The GPR, as its name implies, is a general purpose register that can be used for temporary storage of data at various places in the CPU as needed. Single-chip GPR is relatively inexpensive and takes up little space, so it can be easily used in large computer systems. On the other hand, LS
Prior to the advent of I and VLSI, the features of GPR were considered too expensive.

The GPR is used to store the history of the contents of the latch as described below. This history is used to distinguish circuit errors from random errors and to perform other error detection functions. For example, at the end of the clock cycle when the outputs of the combinatorial logic are loaded into the latches, those outputs of some selected groups are also loaded into the neighboring GPR. In this way, the contents of the latch change every cycle, but the GPR
Contains a history of the latch's previous contents. Furthermore, the error detection logic can be designed as a combinatorial logic, for example parity bits can be added to the group, parity generation and check circuits can be added to the combinatorial logic and outputs from the redundancy circuit. , And their outputs can be checked for their identity.

Thus, by using the floating point split instruction example above, when the error detection circuit detects an error after the fourth cycle of computation, the CPU is deactivated and stored before the fourth cycle. GPR
The data from is loaded into the appropriate latch, at which point the CPU can be restarted. If this error is caused by some random defect mechanism, such as a noise pulse in the power supply system, a second attempt to perform the calculation is possible. This retrial feature significantly improves system reliability because many errors are random and correctable.

However, if the error was caused by a circuit failure, the error would reoccur and an appropriate latch would be operated by the operator to isolate the failed circuit.

Although the above error detection methods significantly improve the reliability and testability of computer systems, unfortunately only half a clock cycle is typically used to detect such errors. Only available. This will be explained in more detail below,
Basically it is caused by the fact that the clock signal must be in a certain state when the operation of the CPU is stopped. If this time (when the clock is in its predetermined state) is not sufficient to detect the error, the clock period must be increased, slowing down the operation of the computer system.
Therefore, what is needed here is in particular a means for detecting an error at any time during a clock cycle so that the operating speed of a computer system is not reduced for reliability. Accordingly, it is an object of the present invention to provide a computer system that provides error detection and correction capabilities without sacrificing operating speed.

Yet another object of the present invention is to provide a scannable CMOS latch which is not a limiting factor on the operating speed of the computer system in which the latch is used. More particularly, it is an object of the present invention to provide a scannable CMOS latch that monitors the latch output for errors during the entire clock cycle.

The above and other objects of the invention are realized by the unique combination of preferred features incorporated into a scannable CMOS latch design. For example, the present invention uses the same clock signal and its complement to effectively control the operation of both the master and slave portions of the latch. This allows both of them to be driven by the same local clock driver, thereby eliminating any clock skew. Additionally, a chopped clock signal in the form of a square wave can be used to provide additional time for the error detection circuit to perform its assigned task. Finally, a separate stage is used for the shift-out part. In contrast, prior art designs used the slave portion of the latch as the shift-out portion, which slows the operating speed of the latch due to the electrical load present in the next shift-in portion. It will be.

The combination of the above features provides a scannable latch circuit suitable for use in high speed computer systems. When such a scannable latch is used, the cycle time of the computer system is determined by the circuit delay of the combinational logic circuit, the wiring delay, the package delay, etc., and is not limited by the scannable latch.

The following is a description of the best mode contemplated for carrying out the invention. This description is for the purpose of illustrating the general principles of the invention only and has no limiting meaning. The actual scope of the invention should be determined with reference to the appended claims.

To appreciate and more fully understand the present invention, prior art latch circuits and prior art combinatorial latch circuits and shift register circuits are first described with reference to FIGS.

FIG. 1 is a logic circuit diagram of a typical latch used in CMOS LSI and VLSI chips.
The latch consists of two parts, a master part 10 and a slave part 11. Each part consists of two electronic switches, such as transmission gates, designated T and numbers such as T1, T2 ..., And two inverter gates, such as inverters designated I and numbers such as I1, I2.

The transmission gate is a circuit indicated by a small circle, which is turned on when the signal at the control input is low and turned off when the signal at the control input is high. When the transmission gate turns on, it acts as a closed switch and the signal passes through it. When the transmission gate is turned off it acts as an open switch and the signal is blocked from passing through it. In these figures, signal C is a clock signal, while signal C ^* Is a complementary signal of this clock signal. Therefore C and C ^* Always has a logical value in the opposite direction, and when C is high, C ^* Is low and vice versa. An inverter is a circuit whose output side polarity is always opposite to the input side polarity.

The latch of FIG. 1 functions as follows. C ^* when clock signal C is high Is low and transmission gates T1 and T4 are on, while transmission gates T2 and T3 are off. Data-in signal DI is T
1 is reversed by I1, inverted by I2 to its original polarity again, but blocked by T2. The output of I1 is also blocked by T3. The clock signal reverses polarity and C goes low to C ^*
When goes high, transmission gates T1 and T4 are turned off while gates T2 and T3 are turned on. Therefore T
The signal at the output of 2 (the same logic signal as DI) is applied to the input of I1. In this way the signal will circulate through the loop formed by I1 and I2, thus "latching" the input signal to the master portion 10 of the latch.

At the same time, the transmission gate T3 is turned on and the input signal DI appears at the output as the signal Q after being inverted twice by I1 and I3. When the clock signal goes high again, C is high and C ^* Is low. Each transmission gate of the latch then returns to its original state. Since T3 is off and T4 is on, the input signal is now latched into the slave portion 11 of the latch.

FIG. 2 is a timing diagram of the latch of FIG. 1, showing the signal DI, the clock signal C, the output M of the master part 10 and the output Q of the slave part 11. The input signal is shown with some gradual peaks for purposes of illustration (such peaks are generally not a feature of logic signals). However, the peaks may represent noise or other undesired discontinuities appearing in the data signal and, unless otherwise noted, these peaks are effective at times when output M is connected to input DI and when it is not connected. Shown in. Circuit delays are not shown in FIG. 2 to make the timing diagram easier to understand.

Further referring to FIG. 2, time point tp
During the first clock sub-cycle, which is between 0 and tp1, clock signal C goes high, T1 turns on and the output M of the master portion of latch 10 becomes the input signal DI.
Seen to follow. At time tp1, the beginning of the next clock sub-cycle, the input signal DI is latched in the master part 10 of the latch and T3 is turned on so that it passes to the output Q of the slave part 11. tp1
During the clock sub-cycle defined between TP2 and tp2, the output M of the master part is unaffected by changes in the signal DI because T1 is off and the output Q of the slave part 11 remains constant. There is. Time point tp2
, The content of the master part 10 is the slave part 11
Latched in. The clock sub-cycle between tp2 and tp3 is similar to the sub-cycle between tp0 and tp1 and the output M of the master part 10 again follows the input signal DI.

As shown in FIG. 2, the clock cycle is the time between the falling edges of clock signal C, eg, tp1.
-Tp3, tp3-tp5, etc. The master-slave latch ensures that the output Q of this latch is constant throughout the entire cycle, unaffected by changes in the inputs, and has the same logic level as the inputs had prior to the beginning of the cycle. To do.

FIG. 3 shows the manner in which the latch shown in FIG. 1 is converted into a combined latch and shift register stage by adding two transmission gates T5 and T6. Three different clock signals A, B and C are used to control the operation of this circuit. Each of these clock signals can be derived from the master clock signal by those skilled in the art by known techniques. To gate this clock signal, the additional circuit shown in FIG. 4 is required.

When the circuit of FIG. 3 is used as a latch, clock signal A is held low and clock signal B is held high. 2-input NAND gate 17
(FIG. 4) is a high level signal B and a clock signal C ^* Enabled by and signal (BC) ^* And its complementary signal BC is generated via an inverter 19. These two signals are clock signals C and C ^*, respectively ^. It matches the phase of. Signal A is low and therefore A ^* Is high, the transmission gate T5 (see FIG. 3) is off and T6 is on and the circuit is controlled by the clock signal C as described for FIG.

When using the circuit of FIG. 3 as a shift register stage, the clock signal C is held low. The 2-input NAND gate 17 has a high level signal C ^*. Is enabled by. Clock signal B is signal (BC) ^* And its complementary signal BC is generated via an inverter 19. Signals BC and (BC) ^* Are signals B and B ^* And are in phase with each other.

FIG. 5 shows a timing diagram of the circuit of FIG. 3 when it functions as a shift register stage. At time tp6 T5 is on and the shift-in signal SI from the previous stage of the shift register is inverted by T1. At time tp7 the signal SI is latched by the master part. T3 is a signal (BC) ^* at time tp8 Is turned on and the signal SI appears on the shift-out output SO. At time tp9, the slave part latches the input signal SI.

Thus, when the circuit is used as a shift register as described above, clock signal A controls the operation of the master part and clock signal B controls the operation of the slave part. These two clock signals A
And B are shown as "chops" described below. The prior art circuit of FIG. 3 has two inherent deficiencies.

(1) The circuit of FIG. 4 causes a skew between the clock signal C controlling the master part and the clock signal BC controlling the slave part when this circuit is used as a latch. This means that T3 does not turn off at exactly the same time that T1 turns on. Therefore, the input signal DI may momentarily appear on the output side and be decoded by the combinational logic circuit connected to this output as the actual signal.

(2) The shift register output SO and the latch output Q are at the same time point. The wiring required to connect SO to the next input SI is relatively long and loads down the circuit connected to Q.

Any of the problems of the prior art described above can be avoided by reducing the clock signal C. However, reducing the clock signal C is not desirable as it directly impacts the cycle time of the device in which the scannable latch is used and thus reduces the overall operating speed of the device.

FIG. 6 shows a schematic diagram of a CMOS logic circuit of the present invention which overcomes both drawbacks associated with the circuit of FIG. Since the circuit of FIG. 6 is directly controlled by the clock signals A, B and C and does not require the circuit of FIG. 4, the skew problem of FIG. 3 is solved.

When using this circuit as a latch in FIG. 6, clock signals A and B are held low and transmission gate T5 is turned off and T6 is turned on. The master parts T1, I1, T2 and I2 and the slave parts T3, I3, T4 and I4 of the latch operate under the control of the clock signal C as described with reference to FIG. The timing diagram of FIG. 5 using signal B instead of signal BC also applies to this FIG. 6 when using the circuit of FIG. 6 as a shift register stage. The circuit of FIG. 6 functions in a manner similar to that described for the shift register of FIG. 3 except that the circuit of FIG. 6 has further slave parts T7, I5, T8 and I6. In this way the output SO does not load down the circuit connected to Q.

FIG. 7 shows how the combination latch / shift register of the present invention may be used in a CPU. The three groups of latches 20a ... 20n, 24a ... 24n and 28a ... 28
n is indicated. The SO output of each latch is connected to the SI input of the next latch such that all illustrated latches form a single shift register. The various clock inputs for each latch are associated with each latch group 20, 24 and 2
8 is shown as a single input CLKS.

Blocks 32 and 33 indicating a combinational logic circuit and an error detection logic circuit are provided between the latch groups. It is shown that blocks 32 and 33 also include a general purpose register (GPR) to store the output of some latches during GPR. Thus, as described above, data is latched in latch 20 at the end of one cycle, appears at output Q, and passes through combinational logic and error detection logic 32 (which may include GPRs). It may not be included) and is latched into another latch 24 at the end of the clock cycle. When an error is detected, the CPU clock is stopped and either one of the following two steps takes place.

(1) The CPU can be "backed up" and restarted. This was done before the appropriate number of cycles by loading the associated latch with the data stored in the GPR (the mechanism for doing this is not shown in FIG. 7) and caused an error. This is done by trying the sequence again. If this error was caused by an intermittent problem, this second try should succeed. On the other hand, when the error is caused by a hardware failure, the error will occur again.

(2) The latch / shift register circuit can be used as a shift register and the data that caused the error can be shifted out to the console CPU. This data can be stored by the console CPU and shifted back into the latch and the CPU can cycle once more to repeat the error. In this way, the data in the latch containing the error can be shifted out to the console CPU. The data before and after the operation that caused the error can be known, and the operation performed when the error occurred can be known. And it is possible to try to isolate the cause of the error.

Using either circuit of FIGS. 3 and 6 as latches 20, 24 and 28 of FIG. 7 and controlling these latches with clock signal C (FIG. 2),
A large time constraint is imposed on the CPU design. Referring to FIG. 2, the clock subcycle time between tp1 and tp2 is the time for the combinational logic to process the data and the time for the error detection circuit to detect an error. At time tp1, data is latched in the master portion of the latch and occurs at the output Q of the latch. At time tp2 the data is latched in the slave part of the latch. Time point tp2 of clock subcycle
And an error is detected between tp3 and tp3, the transmission gate T
1 turns on and the output M of the master part follows the input DI. When clock signal C is stopped, the clock goes low-level and the slave part will latch the logic level present at its input. In this way, the contents of the slave portion that existed at the beginning of the cycle are changed.

One way to avoid the above problem is to enable the error detection logic to detect an error while the clock signal C is low, ie during the clock subcycle time defined between tp1 and tp2. It is to take a long cycle. However, as already mentioned, it is desirable to operate the computing device at the maximum speed possible for maximum efficiency. Therefore, the cycle time is designed to be the minimum time for which the group of combinational logic circuits having the slowest operation time can function.

8 and 9 show how the clock signal can be "chopped" and the advantages of such chopping. In FIG. 8, the signal CLK is applied to one input terminal of a 2-input NAND gate 40 and a plurality of inverters 42 to 45.
Shows a mode of adding to the other input terminal through. FIG.
FIG. 9 is a timing diagram of the circuit of FIG. Signal DCLK is delayed by inverters 42-45 by an amount equal to the time between tp10 and tp11. During the time between tp11 and tp12, both CLK and DCLK are high and the output of NAND gate 40 is low. This output is inverted by inverter 41 to produce clock signal CC (for simplicity, NAN is shown in FIG. 9).
Circuit delay due to D-gate 40 and inverter 41 is not shown).

Using a chopped clock signal CC instead of the square wave C of FIG. 1 extends the length of time that the clock signal is low. That is, the square wave C is low for 50% of the cycle, while the chopped clock signal CC is low for 90% of the cycle in this example. The chopped clock signals A and B of FIG. 5 which are the signals used in connection with the operation of the scannable latch circuit described herein are clock signal CLK in the same manner as shown in FIG. Note that it can be generated from (or any other master clock signal).

A chop cycle is initiated at tp12 when the data at the latch input is latched into the master portion using the chopped signal CC and also at the output (see FIG. 9). In this way the error detection logic has a time between tp12 and tp13 while the clock signal CC is low and detects any errors. At time tp13 the input is latched in the slave part of the latch and the next cycle begins at tp14. As can be seen from the above, the chopped clock signal C
C significantly extends the time allowed for the error detection logic to detect an error.

A logic schematic of an improved version of the latch of FIG. 6 is shown in FIG. 10 and the corresponding timing diagram is shown in FIG. When using this circuit as a latch, the elements T20, I20, T21 and I2
1 forms the master part and the elements T22, I22, T
23 and I23 form the slave part. During this mode of operation (when the circuit is used as a latch), clock signals A and B are low, transmission gates T24 and T26 are off and transmission gate T2.
5 and T27 are on. It should be noted that the polarity of the transmission gate clock signal C is opposite to that shown for the latch embodiment of FIGS. 1, 3 and 6.

The timing diagram shown in FIG. 11 shows that before time tp15 the clock signal C is low and T20 is on. In this way, the input signal DI inverted by I20 is present at the turned off input of T22. At tp15, the clock signal goes high. Thus T20 is turned off and T21 is turned on to latch the signal DI into the master portion of the latch. T22 also turns on at tp15 and the input signal DI appears at the output Q. Time t
At p16, the clock signal C goes low and T22
Off and T23 on to latch the input signal into the slave portion of the latch.

As shown, the clock cycle is tp15.
And the time between tp17. The time between tp15 and tp16 is short compared to the time it takes for the error detection logic to function. Therefore, no error could be detected in any case during this time. Thus this part of the clock cycle between tp15 and tp16 is of no significance. On the other hand, if an error is detected between tp16 and tp17, the clock signal is low and the input can be stopped without latching in the master portion of the latch. This circuit thus provides a complete cycle useful for operating the error detection signal.

When the circuit of FIG. 10 is used as a shift register stage, the clock signal C is held low. Transmission gate T22 turns off and T20 turns on. In the example of FIG. 6, the master portion of the latch also functioned as the master portion of the shift register stage because it held the data that was shifted when the clock was stopped. In contrast, in the improved circuit of FIG. 10, the data shifted when the clock is stopped is held in the slave portion of the latch. Thus the slave part of the latch becomes the master part of the shift register stage and element T2
4, I24, T25 and I25 are the slave parts of the shift register.

The timing diagram of FIG. 5 without the signal BC also applies to the circuit of FIG. 10 when operating in shift register mode. The clock signal A goes high, turning on T24 and transferring the data held in the master part of the shift register stage (slave part of the latch) to the output SO
Transfer to When clock signal A goes low, T24 turns off and T25 turns on and the data is latched in the slave portion of the shift register stage. Further, the clock signal B goes high, the transmission gate T26 is turned on, and the input signal SI from the output of the previous stage of the shift register is applied to the input of the master part of the shift register stage. When clock signal B goes low, transmission gate T26 turns off, T27 turns on, and input signal SI is latched into the master portion of the shift register stage.

The improved circuit of FIG. 10 solves both problems existing in prior art latch / shift register circuits. 100% of the clock cycles are effectively utilized by the error detection logic and the output of the latch is not loaded down by the input of the next shift register stage. This improvement allows the clock cycle to be as short as the total delay time of the system is possible without the risk of the clock signal going from high to low when an error is detected.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a typical CMOS latch circuit.

FIG. 2 is a timing diagram of the CMOS latch circuit of FIG.

FIG. 3 is a logic circuit diagram of a combined CMOS latch / shift register circuit.

FIG. 4 is a circuit diagram of a clocked gate circuit required for the latch / shift register circuit of FIG.

FIG. 5 is a timing diagram of the circuits of FIGS. 3 and 4.

FIG. 6 is a logic circuit diagram of a combined CMOS latch / shift register circuit of the present invention.

FIG. 7 is a circuit diagram showing a usage state of a combination CMOS latch / shift register circuit in the structure of the latest computer system.

FIG. 8 is a logic circuit diagram of a clock chop circuit used in the present invention.

9 is a timing diagram of the clock chop circuit of FIG.

FIG. 10 is a logic circuit diagram of another combination CMOS latch / shift register circuit of the present invention.

FIG. 11 is a timing diagram of the combined CMOS latch / shift register circuit of FIG.

[Explanation of symbols]

10 ... Master part, 11 ... Slave part, 17 ... 2-input NAND gate, 19 ... Inverter, 20, 24, 2
8 ... Latch group, 32, 33 ... Error detection logic circuit, 40
... 2-input NAND gates, 41, 42, 43, 44,
45 ... Inverter, T1, T2, T3, T4, T5, T
6, T7, T8, T20, T21, T22, T23, T
24, T25, T26, T27 ... Transmission gate (electronic switching device), I1, I2, I3, I4, I5, I6
I20, I21, I22, I23, I24, I25 ... Inverter (inverter gate).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-57-106218 (JP, A) JP-A-5-267999 (JP, A) Actual development S57-4100 (JP, U) JP-B 52- 28614 (JP, B1)

Claims (2)

(57) [Claims] 1. A first transmission gate to which a data input signal is input and a first clock signal is applied to one end, and a first inverter gate whose input end is connected to the other end of the first transmission gate. A second inverter gate having an input end connected to the output end of the first inverter gate, and one end connected to an output end of the second inverter gate to a second end
Second transmission gate to which the first clock signal is applied, and one end is connected to the other end of the second transmission gate and the other end is connected to the input end of the first inverter gate, and the first clock signal is applied. A first latch circuit comprising a third transmission gate, and a fourth transmission circuit having one end connected to the output terminal of the first inverter gate of the first latch circuit and having the first clock signal applied thereto. A gate, a third inverter gate whose input end is connected to the other end of the fourth transmission gate, a fourth inverter gate whose input end is connected to the output end of the third inverter gate, and one end Is connected to the output end of the fourth inverter gate, the other end is connected to the input end of the third inverter gate, and a fifth transmission gate to which the first clock signal is applied is applied to the second latch circuit. And one end A sixth transmission gate connected to the output terminal of the first inverter gate of the first latch circuit and to which a third clock signal is applied, and an input terminal connected to the other end of the sixth transmission gate. A fifth inverter gate, a sixth inverter gate whose input end is connected to the output end of the fifth inverter gate, one end connected to the output end of the sixth inverter gate, and the other end of the fifth inverter gate. A third latch circuit comprising a seventh transmission gate connected to the input terminal of the inverter gate of the second transmission circuit and having a third clock signal applied thereto; one end connected to the shift data input signal;
An eighth transmission gate to which a second clock signal is applied and which is connected to a common connection point of the second and third transmission gates in the latch circuit of FIG. The second latch circuit operates as a master latch circuit and a slave latch circuit, respectively, outputs a data output bit signal based on a data input signal from the second latch circuit, and outputs the data output bit signal based on the data input signal. A CMOS logic circuit configured to operate as a shift register circuit together with the third latch circuit, and to output an output signal based on a shift data input signal from the third latch circuit. 2. A first transmission gate to which a data input signal is input and a first clock signal is applied to one end, and a first inverter gate whose input end is connected to the other end of the first transmission gate. A second inverter gate whose input end is connected to the output end of the first inverter gate, and one end of which is connected to the output end of the second inverter gate and the other end of which is the input of the first inverter gate. First connected to the end
A first latch circuit composed of a second transmission gate to which the first clock signal is applied, and one end of which is connected to an output terminal of the first inverter gate of the first latch circuit to which the first clock signal is applied. A third transmission gate, an input end connected to the other end of the third transmission gate, and a fourth input gate connected to the output end of the third inverter gate. An inverter gate, a fourth transmission gate having one end connected to the output end of the fourth inverter gate and receiving a second clock signal, and one end connected to the other end of the fourth transmission gate and the other end Is connected to the input terminal of the third inverter gate and includes a fifth transmission gate to which the first clock signal is applied, and a fourth inverter of the second latch circuit having one end. Gate exit A sixth transmission gate connected to the end to which the third clock signal is applied, a fifth inverter gate whose input end is connected to the other end of the sixth transmission gate, and an input end to the fifth A sixth inverter gate connected to the output end of the inverter gate, and a third clock signal having one end connected to the output end of the sixth inverter gate and the other end connected to the input end of the fifth inverter gate And a third latch circuit including a seventh transmission gate to which is applied, one end of which is connected to the shift data input signal and the other end of which is the second
An eighth transmission gate connected to a common connection point of the fourth and fifth transmission gates in the latch circuit to which a second clock signal is applied, the first and second transmission gates in the first operation mode. The second latch circuit operates as a master latch circuit and a slave latch circuit, outputs a data output bit signal based on a data input signal from the second latch circuit, and outputs the data output bit signal based on the data input signal. A CMOS logic circuit configured to operate as a shift register circuit together with the third latch circuit, and to output an output signal based on a shift data input signal from the third latch circuit.