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JP2566207B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2566207B2
JP2566207B2 JP62234682A JP23468287A JP2566207B2 JP 2566207 B2 JP2566207 B2 JP 2566207B2 JP 62234682 A JP62234682 A JP 62234682A JP 23468287 A JP23468287 A JP 23468287A JP 2566207 B2 JP2566207 B2 JP 2566207B2
Authority
JP
Japan
Prior art keywords
control circuit
semiconductor
semiconductor device
power mosfet
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62234682A
Other languages
Japanese (ja)
Other versions
JPS6387758A (en
Inventor
ヨーゼフ、アインチンガー
ルードウイツヒ、ライポルト
イエネ、チハニ
ローラント、ウエーバー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
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Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of JPS6387758A publication Critical patent/JPS6387758A/en
Application granted granted Critical
Publication of JP2566207B2 publication Critical patent/JP2566207B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Electronic Switches (AREA)
  • Ignition Installations For Internal Combustion Engines (AREA)

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は、パワーMOSFETとこのMOSFETの制御のため
の集積された制御回路とを備えた半導体デバイスに関す
る。Description: TECHNICAL FIELD The present invention relates to a semiconductor device including a power MOSFET and an integrated control circuit for controlling the MOSFET.

［従来の技術］ かかる半導体デバイスは種々の名称、例えば「スマー
ト（Smart）FET」のような名称で市販されている。その
際制御回路とパワーMOSFETとは同一の半導体基体上に集
積されている。しかしながらかかるデバイスは、パワー
MOSFETを制御回路と同様に複雑な技術で製造しなければ
ならないという欠点を有する。更に同一面上にあるとき
には、従来製造されたパワーMOSFETに比べて明らかに高
いドレーン・ソース間抵抗を生じる。更に同一半導体基
体上での集積により、パワー部分の十分な冷却の理由か
ら必要とされるよりも多くの取り付け面を要する。[Prior Art] Such semiconductor devices are commercially available under various names, for example, "Smart FET". At that time, the control circuit and the power MOSFET are integrated on the same semiconductor substrate. However, such devices are
It has the disadvantage that the MOSFET has to be manufactured by a complicated technique like the control circuit. Furthermore, when they are on the same plane, a drain-source resistance which is significantly higher than that of a conventionally manufactured power MOSFET is generated. Furthermore, integration on the same semiconductor substrate requires more mounting surfaces than is necessary for reasons of sufficient cooling of the power part.

［発明が解決しようとする問題点］ この発明は、頭記の半導体デバイスの製造技術を簡易
化し、かつ取り付けのための所要面積を減少させ、さら
にパワーMOSFETの温度を制御回路ができるだけ正確に検
出し得るようにすることを目的とする。[Problems to be Solved by the Invention] The present invention simplifies the manufacturing technique of the semiconductor device described above, reduces the required area for mounting, and further, the control circuit detects the temperature of the power MOSFET as accurately as possible. The purpose is to be able to.

［問題点を解決するための手段］ 上述の目的を達成するため、この発明においては、パ
ワーMOSFETを含む半導体基体と、このパワーMOSFETを制
御するための制御回路を集積した別の半導体基体とを備
え、制御回路の半導体基体はパワーMOSFETの半導体基体
の一主面上に配置され、両半導体基体は相互に電気絶縁
層を介して熱的、機械的に結合され、制御回路は温度セ
ンサを備え、この温度センサはスイッチと電気的に接続
され、パワーMOSFET中に生じる温度が所定の限界温度に
達したとき前記スイッチが信号を発するようにする。[Means for Solving the Problems] In order to achieve the above-mentioned object, in the present invention, a semiconductor substrate including a power MOSFET and another semiconductor substrate in which a control circuit for controlling the power MOSFET is integrated are provided. The semiconductor substrate of the control circuit is arranged on one main surface of the semiconductor substrate of the power MOSFET, the two semiconductor substrates are thermally and mechanically coupled to each other via an electrically insulating layer, and the control circuit has a temperature sensor. The temperature sensor is electrically connected to the switch so that the switch emits a signal when the temperature generated in the power MOSFET reaches a predetermined limit temperature.

この発明の実施態様は特許請求の範囲第２項以下に記
載されている。Embodiments of the present invention are described in the second and subsequent claims.

［実施例］ 次にこの発明に基づく半導体デバイスの二つの実施例
を示す図面により、この発明を詳細に説明する。[Embodiment] The present invention will be described in detail with reference to the drawings showing two embodiments of a semiconductor device according to the present invention.

第１図及び第２図において、パワーMOSFETは半導体基
体１内に形成され、その一主面上には別の半導体基体２
が配置され、その中に制御回路が集積されている。半導
体基体２は半導体基体１より小さい面を有する。半導体
基体２は半導体基体１に対して絶縁層３により電気的に
絶縁され、接着剤層４により半導体基体１に機械的に結
合されている。絶縁層３は例えば窒化シリコンSi3N4か
ら成り、層４は絶縁性接着剤から成る。絶縁層３は半導
体基体２又は半導体基体１の構成部分とすることもでき
る。後者の場合には接着剤層は絶縁層３と半導体基体２
との間に置かれる。しかしながら絶縁層３を絶縁箔とし
て構成し両半導体基体に接着することもまた可能であ
る。この絶縁層３は数μｍの厚さにすることによって、
両半導体基体１、２間の十分良好な熱的接触を得ること
ができる。In FIG. 1 and FIG. 2, the power MOSFET is formed in the semiconductor substrate 1, and another semiconductor substrate 2 is formed on one main surface thereof.
Are arranged, and the control circuit is integrated therein. The semiconductor body 2 has a smaller surface than the semiconductor body 1. The semiconductor substrate 2 is electrically insulated from the semiconductor substrate 1 by the insulating layer 3 and mechanically coupled to the semiconductor substrate 1 by the adhesive layer 4. The insulating layer 3 is made of, for example, silicon nitride Si 3 N 4 , and the layer 4 is made of an insulating adhesive. The insulating layer 3 can also be a component of the semiconductor substrate 2 or the semiconductor substrate 1. In the latter case, the adhesive layer is the insulating layer 3 and the semiconductor substrate 2.
Placed between and. However, it is also possible to construct the insulating layer 3 as an insulating foil and bond it to both semiconductor substrates. This insulating layer 3 has a thickness of several μm,
A sufficiently good thermal contact between the two semiconductor substrates 1 and 2 can be obtained.

半導体基体１と２から構成されたユニットは冷却体13
上に固定されている。固定のための半導体基体１と冷却
体13との間に存在する層12が用いられる。層12は例えば
導電性の接着剤である。制御回路は、半導体基体２の上
面上に配置された電極７により導線９を介してケース端
子10に電気的に結合されている。制御回路は、制御回路
の出力端５をパワーFETのゲート電極６に結合する導線1
4を介して、パワーFETを制御する。パワーFETのソース
電極は電極８と二つの導線９とを介してケース端子Sour
ce及び制御回路に結合されている。The unit composed of the semiconductor substrates 1 and 2 is a cooling body 13
It is fixed on. A layer 12 which is present between the semiconductor body 1 for fixing and the cooling body 13 is used. Layer 12 is, for example, a conductive adhesive. The control circuit is electrically coupled to the case terminal 10 via a conductor 9 by an electrode 7 arranged on the upper surface of the semiconductor substrate 2. The control circuit comprises a conductor 1 which connects the output 5 of the control circuit to the gate electrode 6 of the power FET.
Control the power FET via 4. The source electrode of the power FET is the case terminal Sour via the electrode 8 and the two conducting wires 9.
coupled to the ce and control circuitry.

半導体基体１と２上の電極の位置は定められた箇所に
拘束されてはおらず、電極は半導体基体の面上に別の状
態で配置することもできる。半導体デバイスは接地のた
めのケース端子GNDを有する。このケース端子は半導体
基体２に結合されている。なぜならば制御回路を給電電
圧に結合しなければならないからである。第２のケース
端子INは制御入力端として用いられる。制御入力端INに
加わる信号は制御回路を介してパワーFETをオンする。
第３のケース端子VDDは制御回路に対し給電電圧を供給
するために用いられ、かつ冷却体13に直接結合されてい
る。ケース端子STは例えば荷電流、過熱、過電圧、負荷
欠落などのような故障の遠隔表示に用いられる。ケース
端子SourceにはパワーFETのためのソース電圧が供給さ
れる。The positions of the electrodes on the semiconductor substrates 1 and 2 are not restricted to the predetermined positions, and the electrodes can be arranged in different states on the surface of the semiconductor substrate. The semiconductor device has a case terminal GND for grounding. The case terminal is connected to the semiconductor substrate 2. This is because the control circuit has to be coupled to the supply voltage. The second case terminal IN is used as a control input terminal. The signal applied to the control input terminal IN turns on the power FET via the control circuit.
The third case terminal V DD is used to supply the supply voltage to the control circuit and is directly connected to the cooling body 13. The case terminal ST is used for remote display of a failure such as load current, overheat, overvoltage, or load loss. The source voltage for the power FET is supplied to the case terminal Source.

この装置はいわゆる高電位側スイッチであり、このス
イッチでは負荷がパワーMOSFETのソース電極と大地との
間に接続され、ドレーン電極はVDDに接続されている。This device is a so-called high-side switch, in which the load is connected between the source electrode of the power MOSFET and the ground, and the drain electrode is connected to V DD .

第３図では低電位側スイッチが示され、このスイッチ
では負荷はVDDとパワーMOSFETのドレーン電極との間に
接続され、ソース電極は接地される。符号は第２図の符
号に対応している。第２図に示す装置と異なって、この
装置は端子Sourceを有せず端子Drainを有し、この端子
はただ冷却体13に結合されているだけである。In FIG. 3 a low side switch is shown in which the load is connected between V DD and the drain electrode of the power MOSFET and the source electrode is grounded. The reference numerals correspond to those in FIG. Unlike the device shown in FIG. 2, this device does not have a terminal Source but a terminal Drain, which is only connected to the cooling body 13.

第４図には集積された制御回路を通る断面が著しく簡
略化した形で示されている。パワーMOSFETの半導体基体
１と半導体デバイスの残りの部分とは切断図示されてい
ない。制御回路はそれ自体周知の方法で自己絶縁形CMOS
技術により製造されている。一般にかなり複雑な構造の
代わりに、ここでは集積された相補形の二つの横形MOSF
ETだけが示されている。半導体基体２は強くｎ形にドー
プされた基体16上に構成されいる。基体16には弱くｎ形
にドープされたエピタキシャル層17が隣接している。こ
の層17の中にはｐ形にドープされた井戸が埋め込まれて
いる。井戸18の中にはｎ形にドープされたソース領域19
とｎ形にドープされたドレーン領域20とが埋め込まれて
いる。この横形ｎチャネルFETはゲート電極21を介して
制御される。更に領域17の中にはｐ形にドープされたソ
ース領域22とｐ形にドープされたドレーン領域23とが埋
め込まれている。この横形ｐチャネルFETはゲート電極2
4により制御される。図示され説明のために最も必要な
構成部分に限定された制御回路を電気的に冷却体に結合
するために、パワーMOSFETと反対側のその主面に強くｎ
形にドープされた領域25が埋め込まれている。この領域
は電極26を備えケース端子VDDに結合されている。その
際領域25の制御回路の集積された素子との間の間隔は領
域17の厚さより数倍大きい。端子VDDに給電電圧が印加
されると、領域17にも給電電圧が加わり、領域18と17と
の間に存在するpn接合と領域22,23と17との間に存在す
るpn接合とが、阻止方向にバイアス電圧を加えられる。
それにより制御回路の両MOSFETは電気的に相互に分離さ
れる。In FIG. 4, a section through the integrated control circuit is shown in a greatly simplified form. The semiconductor substrate 1 of the power MOSFET and the rest of the semiconductor device are not shown in the cutaway view. The control circuit is a self-isolated CMOS in a manner known per se.
Manufactured by technology. Instead of a generally rather complex structure, here two integrated complementary lateral MOSFs are used.
Only ET is shown. The semiconductor body 2 is constructed on a strongly n-doped substrate 16. Adjacent to the substrate 16 is a weakly n-doped epitaxial layer 17. A p-type doped well is embedded in this layer 17. In the well 18, an n-type source region 19 is doped.
And an n-type doped drain region 20 are buried. The lateral n-channel FET is controlled via the gate electrode 21. Furthermore, a p-type doped source region 22 and a p-type doped drain region 23 are buried in the region 17. This lateral p-channel FET has a gate electrode 2
Controlled by 4. In order to electrically couple the control circuit to the cooling body, which is limited to the components shown and shown which are the most necessary for the explanation, the power MOSFET is strongly connected to its main surface opposite to the main surface.
A region 25, which is doped in shape, is embedded. This region comprises the electrode 26 and is coupled to the case terminal V DD . The distance between the integrated elements of the control circuit in region 25 is then several times greater than the thickness of region 17. When the power supply voltage is applied to the terminal V DD , the power supply voltage is also applied to the region 17, and the pn junction existing between the regions 18 and 17 and the pn junction existing between the regions 22, 23 and 17 are formed. , A bias voltage is applied in the blocking direction.
As a result, both MOSFETs of the control circuit are electrically isolated from each other.

制御回路はいわゆる接合絶縁技術で構成することもで
き、この技術ではエピタキシャル層の中に埋め込まれた
種々の機能の部分が、逆に形にドープされた領域にまで
達する深い強く逆の形にドープされた領域により相互に
分離される。各機能単位を基板の中の絶縁材料により絶
縁された井戸の中に埋め込むことにより、制御回路の個
々の回路素子を誘電体絶縁により相互に分離することも
また可能である。The control circuit can also be constructed by means of so-called junction isolation technology, in which the parts of the various functions embedded in the epitaxial layer are deeply and strongly oppositely doped to reach the oppositely doped region. The separated areas are separated from each other. It is also possible to isolate the individual circuit elements of the control circuit from one another by means of dielectric insulation, by embedding each functional unit in a well insulated by an insulating material in the substrate.

過熱の際に信号を発するかかる回路装置は第５図に示
されている。この回路装置はｐチャネルFET T1とｎチ
ャネルMOSFET T2との直列回路から成る。FET T1はエ
ンハンスメント形でありFET T2はデプリーション形で
ある。トランジスタT1のソース電極は運転電圧VDDを印
加された端子１に結合されている。トランジスタT2のソ
ース側は端子２を介して大地GNDに接続されている。ト
ランジスタT2のゲート電極はそのソース電極に結合さ
れ、従ってトランジスタT2は電流源として働く。トラン
ジスタT1,T2にはバイポーラトランジスタT3とMOSFET T
4とから成る直列回路が並列に接続されている。その際
トランジスタT4のドレーン電極はトランジスタT3のエミ
ッタ電極に結合され、トランジスタT3のコレクタ電極は
端子１に結合されている。トランジスタT4のドレーン電
極又はトランジスタT3のエミッタ電極は電気的にトラン
ジスタT1のゲート電極に結合されている。トランジスタ
T1のゲート電極と端子１との間には、トランジスタT1の
ゲート・ソース間バイアス電圧を制限する第１のツェナ
ーダイオードD1が接続されている。トランジスタT2のソ
ースとドレーン電極との間には、出力電圧の制限するツ
ェナーダイオードD2が接続されている。Such a circuit arrangement which gives a signal upon overheating is shown in FIG. This circuit arrangement consists of a series circuit of a p-channel FET T1 and an n-channel MOSFET T2. FET T1 is an enhancement type and FET T2 is a depletion type. The source electrode of the transistor T1 is coupled to the terminal 1 to which the operating voltage V DD is applied. The source side of the transistor T2 is connected to the ground GND via the terminal 2. The gate electrode of transistor T2 is coupled to its source electrode, so that transistor T2 acts as a current source. Transistors T1 and T2 have bipolar transistor T3 and MOSFET T
A series circuit consisting of 4 and 4 is connected in parallel. The drain electrode of the transistor T4 is then connected to the emitter electrode of the transistor T3 and the collector electrode of the transistor T3 is connected to the terminal 1. The drain electrode of transistor T4 or the emitter electrode of transistor T3 is electrically coupled to the gate electrode of transistor T1. Transistor
A first Zener diode D1 that limits the gate-source bias voltage of the transistor T1 is connected between the gate electrode of T1 and the terminal 1. A Zener diode D2 that limits the output voltage is connected between the source and drain electrodes of the transistor T2.

温度センサはバイポーラトランジスタT3により構成さ
れている。他のすべての素子は、過熱を表示する信号の
発生のためのスイッチとして働く。パワーMOSFET １と
従ってトランジスタT3の温度が上がると、トランジスタ
T3の電流が増加する。トランジスタT3を流れる電流が電
流源としてのトランジスタT4を通って流れる電流よりも
大きくなると、トランジスタT4の内部抵抗が著しく増加
し、トランジスタT1のゲート電極の電圧が大地電位から
突然上昇する。その際トランジスタT1の電圧しきい値を
超えるとトランジスタT1はオフされ、端子３の電位は大
地電位に戻る。そのときこの電位は端子３と２に接続さ
れた論理回路により過熱信号として検出され、例えばパ
ワーMOSFETのオフをもたらす。The temperature sensor is composed of a bipolar transistor T3. All other elements act as switches for the generation of signals indicative of overheating. When the temperature of the power MOSFET 1 and thus of the transistor T3 rises, the transistor
T3 current increases. When the current flowing through the transistor T3 becomes larger than the current flowing through the transistor T4 as a current source, the internal resistance of the transistor T4 increases significantly and the voltage of the gate electrode of the transistor T1 suddenly rises from the ground potential. At that time, when the voltage threshold of the transistor T1 is exceeded, the transistor T1 is turned off and the potential of the terminal 3 returns to the ground potential. This potential is then detected by the logic circuit connected to terminals 3 and 2 as an overheat signal, for example turning off the power MOSFET.

自明のように制御回路は他の機能を満たすために設計
することができる。このための可能性は例えばドイツ連
邦共和国特許出願公開第3609235号明細書（特開昭62−2
2713号明細書）、同第3609236号明細書（特開昭62−227
215号明細書）、同第3624565号明細書（特開昭63−3131
31号明細書）に記載されている。Obviously, the control circuit can be designed to fulfill other functions. A possibility for this purpose is disclosed, for example, in German Patent Application DE 3609235 A1 (Japanese Patent Laid-Open No. 62-2).
2713) and 3609236 (JP-A-62-227).
215) and 3624565 (JP-A-63-3131).
No. 31).

【図面の簡単な説明】[Brief description of drawings]

第１図はこの発明に基づく半導体デバイスの一実施例の
側面図、第２図は第１図に示すデバイスの平面図、第３
図はデバイスの別の実施例を平面図、第４図は第１図又
は第３図に示す制御回路の断面図、第５図は第４図に示
す制御回路の部分回路図である。 １……パワーMOSFETの半導体基体、２……制御回路の半
導体基体、３……絶縁層、４……接着剤層、13……冷却
体、16……基板、25……領域、26……電極、T1,T2,T4…
…MOSFET（スイッチ）、T3……バイポーラトランジスタ
（温度センサ）。1 is a side view of an embodiment of a semiconductor device according to the present invention, FIG. 2 is a plan view of the device shown in FIG. 1, and FIG.
FIG. 4 is a plan view of another embodiment of the device, FIG. 4 is a sectional view of the control circuit shown in FIG. 1 or 3, and FIG. 5 is a partial circuit diagram of the control circuit shown in FIG. 1 ... Power MOSFET semiconductor substrate, 2 ... Control circuit semiconductor substrate, 3 ... Insulating layer, 4 ... Adhesive layer, 13 ... Cooling body, 16 ... Substrate, 25 ... Region, 26 ... Electrodes, T1, T2, T4 ...
... MOSFET (switch), T3 ... bipolar transistor (temperature sensor).

───────────────────────────────────────────────────── フロントページの続き (72)発明者 イエネ、チハニ ドイツ連邦共和国ミユンヘン70、ウイン デツクシユトラーセ１ (72)発明者 ローラント、ウエーバー ドイツ連邦共和国ミユンヘン40、ウイズ ラシユトラーセ５ (56)参考文献 特開 昭50−9071（ＪＰ，Ａ) 特開 昭57−40977（ＪＰ，Ａ) 実開 昭59−56759（ＪＰ，Ｕ) 実開 昭60−25160（ＪＰ，Ｕ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yene, Chihani Miyunchen 70, Federal Republic of Germany 1 Wyndeckshiyutrase 1 (72) Inventor Laurent, Weber Miyunchen 40, Federal Republic of Germany 5 Wise Raschyutrase 5 (56) References JP-A-50-9071 (JP, A) JP-A-57-40977 (JP, A) Actually opened 59-56759 (JP, U) Actually opened 60-25160 (JP, U)

Claims (8)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】パワーMOSFETを含む半導体基体（１）と、
このパワーMOSFETを制御するための制御回路を集積した
別の半導体基体（２）とを備え、制御回路の半導体基体
（２）はパワーMOSFETの半導体基体（１）の一主面上に
配置され、両半導体基体（1,2）は相互に電気絶縁層
（3,4）を介して熱的、機械的に結合され、制御回路は
温度センサ（T3）を備え、この温度センサ（T3）はスイ
ッチ（T1,T2,T4）と電気的に接続され、パワーMOSFET中
に生じる温度が所定の限界温度に達したとき前記スイッ
チが信号を発するようにしたことを特徴とする半導体デ
バイス。1. A semiconductor substrate (1) including a power MOSFET;
Another semiconductor substrate (2) in which a control circuit for controlling the power MOSFET is integrated, and the semiconductor substrate (2) of the control circuit is arranged on one main surface of the semiconductor substrate (1) of the power MOSFET, The two semiconductor bodies (1, 2) are thermally and mechanically coupled to each other via an electrically insulating layer (3, 4), and the control circuit has a temperature sensor (T3), which is a switch. A semiconductor device electrically connected to (T1, T2, T4), wherein the switch emits a signal when the temperature generated in the power MOSFET reaches a predetermined limit temperature. 【請求項２】絶縁層（３）がパワーMOSFETの半導体基体
（１）上に設けられていることを特徴とする特許請求の
範囲第１項記載の半導体デバイス。2. A semiconductor device according to claim 1, characterized in that the insulating layer (3) is provided on the semiconductor body (1) of the power MOSFET. 【請求項３】絶縁層（３）ガ制御回路の半導体基体
（２）上に設けられていることを特徴とする特許請求の
範囲第１項記載の半導体デバイス。3. A semiconductor device according to claim 1, wherein the insulating layer (3) is provided on the semiconductor substrate (2) of the control circuit. 【請求項４】両半導体基体（1,2）が相互に接着されて
いることを特徴とする特許請求の範囲第１項ないし第３
項のいずれか１項に記載の半導体デバイス。4. A semiconductor device according to claim 1, wherein the two semiconductor substrates (1, 2) are adhered to each other.
The semiconductor device according to any one of items. 【請求項５】接着剤層（４）が絶縁性接着剤からなるこ
とを特徴とする特許請求の範囲第４項記載の半導体デバ
イス。5. A semiconductor device according to claim 4, wherein the adhesive layer (4) is made of an insulating adhesive. 【請求項６】パワーMOSFETの半導体基体（１）の一主面
が冷却体（13）上に固定され、制御回路の半導体基体
（２）がパワーMOSFETの半導体基体（１）の他主面上に
設けられていることを特許とする特許請求の範囲第１項
記載の半導体デバイス。6. A power MOSFET semiconductor substrate (1) has one main surface fixed on a cooling body (13), and a control circuit semiconductor substrate (2) on the other main surface of the power MOSFET semiconductor substrate (1). The semiconductor device according to claim 1, wherein the semiconductor device is provided in the. 【請求項７】制御回路が強くドープした基板（16）上に
自己絶縁形CMOS技術により構成され、制御回路の半導体
基体（２）のパワーMOSFETと反対側の面上に電極（26）
が設けられ、この電極が基板（16）に電気的に結合され
ていることを特徴とする特許請求の範囲第１項ないし第
６項のいずれか１項に記載の半導体デバイス。7. A control circuit is constructed by means of a self-insulating CMOS technology on a strongly doped substrate (16) and an electrode (26) is provided on the side of the control circuit semiconductor substrate (2) opposite to the power MOSFET.
7. The semiconductor device according to claim 1, wherein the electrode is electrically connected to the substrate (16). 【請求項８】電極（26）が基板（16）と同じ導電性の形
を有する強くドープされた領域（25）上に設けられてい
ることを特徴とする特許請求の範囲第７項記載の半導体
デバイス。8. An electrode according to claim 7, characterized in that the electrode (26) is provided on a strongly doped region (25) having the same conductivity type as the substrate (16). Semiconductor device.
JP62234682A 1986-09-23 1987-09-18 Semiconductor device Expired - Lifetime JP2566207B2 (en)

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DE3632199.0 1986-09-23
DE3632199 1986-09-23

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EP0262530A1 (en) 1988-04-06
MY102712A (en) 1992-09-30
KR930009475B1 (en) 1993-10-04
KR880004580A (en) 1988-06-07
DE3786314D1 (en) 1993-07-29
EP0262530B1 (en) 1993-06-23
JPS6387758A (en) 1988-04-19
US4947234A (en) 1990-08-07

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