JP2565296B2 - Input circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit, and more particularly to an input circuit for an interface section of a high power supply voltage CMOS integrated circuit which receives a signal from a low power supply voltage CMOS integrated circuit.

[0002]

2. Description of the Related Art Power consumption increases with the increase in the degree of integration of integrated circuits and high-speed operation, and in order to reduce the power consumption, a lower power supply voltage is being promoted. In the process of lowering the power supply voltage, integrated circuits having different power supply voltages may be used in the same device. In this case, in the conventional integrated circuit, if the output terminal of the low power supply voltage system integrated circuit is directly connected to the input terminal of the high power supply voltage system, the high power supply voltage system integrated circuit is provided during the period when the signal potential to be delivered is at a high level. A current of about several mA may constantly flow in the input buffer circuit of the circuit. This phenomenon causes an increase in power consumption and becomes a serious problem when the high power supply voltage system integrated circuit is a large-scale integrated circuit having several tens or more input terminals. The above situation will be described in detail below with reference to FIG.

In FIG. 4, a p-channel MOSFET is shown.
(Hereinafter referred to as PMOST) QP ₁ and n-channel MOS
An output circuit of a low power supply voltage system integrated circuit ICL composed of a FET (hereinafter referred to as NMOST) QN ₁ is connected to an input terminal IN of a high power supply voltage system integrated circuit ICH.
The input circuit of the high power voltage system integrated circuit ICH is a PMOST
It is composed of a QP ₂ and NMOSTQN _2, the input terminal IN
The first stage CMOS inverter circuit with the input terminal as the input terminal, and the output signal thereof as the input signal of the PMOSTQP ₃ and the NMOST
And a second-stage CMOS inverter circuit composed of QN ₃ . The output terminal of the second-stage inverter circuit is connected to the output terminal OUT of this input circuit.

An output signal of the low power supply voltage integrated circuit ICL,
That is, when the signal at the input terminal IN of the high power supply voltage integrated circuit ICH is at the high level, the signal at the output terminal OUT of the input circuit is also at the high level, and when the signal at the input terminal IN is at the low level, the signal at the output terminal is also at the low level. Become. Input terminal IN
When the signal at the input terminal IN is at the high level, the voltage V _DL (that is, the power supply voltage of the low power supply voltage system integrated circuit ICL) is high when the signal at the low level is integrated. From the power supply voltage V _{DH of the} circuit ICH to the PMOST
When it is smaller than the value obtained by subtracting the absolute value of the threshold voltage of QP ₂ , the disadvantage that the PMOS TQP ₂ does not turn off occurs. For example, if the voltage V _DL is 3 V, the voltage V _DH is 5 V, and the threshold voltage of the PMOS TQP ₂ is −0.8 V, then there is 3 between the gate and source of the PMOS TQP _2.
Since the voltage of V-5V = -2V is applied, the PMOSTQP
₂ does not turn off. On the other hand, NMOS TQN ₂ is
Since a voltage of 3 V is applied between the sources, it is in the on state. Therefore, current flows from the power supply terminal 1H to the ground terminal through the NMOS TQN ₂ of the PMOS TQP ₂ . In particular, in an input circuit that requires high-speed operation, this current may reach several mA per input circuit, and an increase in power consumption becomes a problem in a large-scale integrated circuit having many input terminals.

In order to solve the above-described problems of the conventional input circuit, an input circuit having a level conversion function has been proposed. FIG. 5 is a circuit diagram of an example thereof. Referring to FIG. 5, this input circuit includes an input terminal IN and a PMOS TQ.
The drain electrode is connected to the input terminal IN between the input terminal of the first-stage inverter circuit composed of P ₂ and NMOS TQN _2.
, The gate electrode is connected to the high voltage side power supply terminal 1H, and the source electrodes are PMOSTQP ₂ and NMOSTQN.
_The NMOSTQN _E connected to the input end of the first-stage inverter circuit composed of ₂ and the drain electrode of the NMOSTQN _E
It is connected to the source electrode of N _E and the gate electrode is PMOST
A PMOSTQP _U having a source electrode connected to the input terminal of the first-stage inverter circuit composed of QP ₂ and NMOS TQN ₂ and having a source electrode connected to the high-voltage side power supply terminal 1H is inserted.

[0006] In this input circuit, when the signal input terminal IN is at low level, through NMOSTQN _E ON state, the input terminal of the first-stage inverter circuit constituted by PMOSTQP ₂ and NMOSTQN ₂ becomes low level, the first stage inverter circuit The signal at the output terminal of becomes high level and turns off PMOSTQP _U, and
The signal at the output terminal of the second-stage inverter circuit, which is composed of TQP ₃ and NMOS QN ₃ , that is, the signal at the output terminal OUT is set to low level.

On the other hand, when the signal at the input terminal IN is at high level, the PMOST is turned on through the NMOSTQN _{E in} the ON state.
Since the input terminal of the first-stage inverter circuit composed of QP ₂ and NMOSTQN ₂ becomes high level (≦ V _DL ), the output terminal of the first-stage inverter circuit becomes low level and PMO
STQP _U is turned on to raise the voltage at the input end of the first-stage inverter circuit to V _DH . As a result, the PMOS TQP ₂ is turned off, and the current path through the PMOS TQP ₂ and the NMOS TQN ₂ is cut off. This solves the problem of the conventional input circuit shown in FIG.

However, in the conventional input circuit shown in FIG. 5, when the difference between the voltages V _DL and V _DH is large, the conventional input circuit shown in FIG.
As indicated by the line with an arrow inside, the high voltage side power supply terminal 1
From H, PMOSTQP _U → NMOSTQN _E → PMO
A new problem arises in that a current may flow to the low-voltage side power supply terminal 1L on the path of STQP ₁ and the low-voltage side power supply voltage V _DL may fluctuate. Moreover, this case, the gate potential of PMOSTQP ₂ by the current flow can not be increased sufficiently, not become PMOSTQ ₂ is turned off, accompanied a problem that a through current from PMOSTQP ₂ through NMOSTQN ₂ occurs appear.

That is, when the voltage V _DH is higher than the voltage V _DL , the signal at the input terminal IN is at a high level (= V _DL ).
However, V _DH -V _DL > V _TN (V _TN is NMOS
(Threshold voltage of TQN _E ), the NMOS TQN _E maintains the ON state. As a result, the above current path is generated.

Next, FIG. 6 is a circuit diagram of another input circuit in which the problem in the conventional input circuit shown in FIG. 5 is improved. The input circuit shown in FIG. 6 is the NM in the input circuit shown in FIG.
OSTQN _E is a depletion type NMOS TQN _D
, And its gate electrodes are PMOS TQP ₂ and N
The configuration is such that it is connected to the output terminal of the first-stage inverter circuit composed of MOSTQN ₂ . Other than that, it is the same as the conventional input circuit shown in FIG. In the input circuit shown in FIG.
Since the signal input terminal IN depletion NMOSTQN _D is in the ON state when the low level, the input terminal of the first-stage inverter circuit is also at the low level. Therefore, the signal at the output end of the first-stage inverter circuit becomes high level,
PMOS TQP _U turns off. This is the same as in the conventional input circuit shown in FIG.

Next, when the signal to the input terminal IN becomes high level (= V _DL ), the PMOSTQP ₂ and the NMOST
The output terminal of the first-stage inverter circuit composed of QN ₂ becomes low level. Therefore, the PMOSTQP _U whose gate electrode is connected to the output terminal of this inverter circuit is turned on, and the voltage at the input terminal of the first-stage inverter circuit is changed from V _DL to V _DL.
Raise to _DH to turn off PMOS TQP ₂ . As a result, from the power supply terminal 1H to the PMOS TQP ₂ and the NMOS
A current path to the ground terminal can be cut off through TQN ₂ . This point is the same as in the conventional input circuit shown in FIG. However, Since the low level signal at the output terminal of the first stage inverter circuit is applied to the gate electrode of the depletion NMOSTQN _D simultaneously, the threshold voltage V _TD of depletion NMOSTQN _D is -V _TD <V _{If DL} is satisfied, this depletion type NMOS TQN _D is turned off. Thereby, from the high voltage side power supply terminal 1H, PMOSTQP _U → P
Power supply terminal 1 through MOSTQN _D → PMOSTQP ₁
The current path leading to L can be cut off.

However, in the conventional input circuit shown in FIG. 6, since the depletion type NMOST is newly required, the integrated circuit equipped with the depletion type NMOST has a large number of manufacturing steps, resulting in an increase in manufacturing cost. Is included.

[0013]

As described above, in the conventional input circuit shown in FIG.
There is a drawback that power consumption increases because TQP ₂ is not turned off.

On the other hand, in the conventional input circuit shown in FIG.
When the potential difference between the high-voltage power supply voltage V _DH and the low-voltage power supply voltage V _DL is large, the NMOS TQN _E will not turn off. As a result, not only the problem in the input circuit shown in FIG. 4 is not solved, but also the problem that the voltage fluctuation of the low-voltage side power supply voltage V _DL may be caused occurs.

Further, in the conventional input circuit shown in FIG.
Since the depletion type NMOST is required,
There is a problem that the manufacturing cost increases. ÷ Therefore, the present invention is an input circuit using a CMOS inverter circuit, which consumes less power even when the high level of the signal from the input terminal is lower than the power supply voltage, the operation is stable, and the manufacturing process is simple. It is intended to provide an input circuit.

[0016]

In the input circuit of the present invention, a current path is provided between an input point of a first-stage CMOS inverter circuit and a power supply voltage supply terminal for a two-stage CMOS inverter circuit connected in cascade. P channel MO to make
An SFET is provided, and an n-channel MOSFET is provided so as to form a current path between the input terminal and the input point of the first stage CMOS inverter circuit.
The conduction of the T and n-channel MOSFETs is controlled by the CM of the first stage.
By controlling the signal in phase with the output signal of the OS inverter circuit, when a high-level input signal is applied to the input terminal, the n-channel MOSFET causes the input terminal and the input point of the first-stage CMOS inverter circuit to be connected to each other. In the input circuit configured to cut off the current path between the two and to raise the input point potential of the first-stage CMOS inverter circuit to the power supply potential by the p-channel MOSFET, the n-channel MOSFET is configured by an enhancement-type MOSFET. A feedback inverter circuit for generating a signal having a low level potential between the power supply potential and the ground potential in an opposite phase to the output signal of the CMOS inverter circuit in the subsequent stage, and conducting the n-channel MOSFET by the feedback. Signal of inverter circuit An input circuit which is characterized by being configured to control.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to the drawings. First, the circuit configuration and operation of the input circuit of the present invention will be described. FIG. 1A is a circuit diagram of an example of the input circuit of the present invention. Referring to the figure, in the input circuit of the present invention, the drain electrode is the input terminal IN.
Connected to the NMOS TQN _E and the PMOS TQP ₂ and N connected in series between the power supply terminal 1H and the ground terminal.
A first-stage inverter circuit composed of MOSTQN _{2 in} which each gate electrode is commonly connected as an input end and each drain electrode is commonly connected as an output end, and similarly, is connected in series between the power supply terminal 1H and the ground terminal. Connected to the PMO
A second stage inverter circuit consisting of STQP ₃ and NMOS TQN ₃ , each gate electrode is commonly connected as an input end, and each drain electrode is commonly connected as an output end, and the source electrode is connected to the power supply terminal 1H. The drain electrode is connected to the input terminal of the first-stage inverter circuit, and the PMOSTQP _U is connected to the output terminal of the second-stage inverter circuit, and the output terminal is connected to the NMOSTQN.
_And an inverter circuit 2 for feedback connected to the gate electrode of _E.

The source electrode of the NMOS TQN _E is connected to the input terminal of the first stage inverter circuit. The output terminal of the first-stage inverter circuit is connected to the input terminal of the second-stage inverter circuit and also to the gate electrode of the PMOS TQP _U. The output terminal of the second-stage inverter circuit is connected to the output terminal OUT.

The PMOS TQP ₁ and the NMOS TQN
Reference numeral ₁ constitutes an output circuit on the low power supply voltage system integrated circuit ICL side, and is supplied with a power supply voltage V _DL lower than the power supply voltage V _DH of the input circuit of the present invention.

Next, the operation of the circuit shown in FIG. 1A will be described with reference to the timing chart of FIG. 1B. First, when the output signal of the output circuit of the low power supply voltage integrated circuit ICL including the PMOS TQP ₁ and the NMOS TQN ₁ is at the low level, that is, the ground level, the input terminal I
The signal potential of N is low level, and the voltage at the point A is also low level. Therefore, since the voltage at the point B is at the high level, that is, the level of the voltage V _DH , the PMOS TQP _U is in the off state. The output terminal OUT is at low level, and the point C is at high level, that is, the level of the voltage V _DH .

Next, PMOS TQP ₁ and NMOS TQN
_In the output circuit of the low power supply voltage integrated circuit ICL composed of ₁ and ₁ , when PMOS TQP ₁ is turned on and NMOS TQN ₁ is turned off, the voltage at the input terminal IN rises toward the voltage V _DL . Also, because NMOS TQN _E is on,
The voltage at the point also rises. Here, assuming that the threshold voltage of the NMOS TQN _E is V _TN , the voltage at the point C is V _DH, so V _DL ≧ V
For _DH -V _TN, the voltage at the point A is V _DH -V _TN N
MOSTQN _E turns off. Therefore, the voltage at point A is V
Once stagnant at _DH -V _TN. However, since the voltage at the point B changes to the low level and the PMOS TQP _U is turned on, the voltage at the point A again rises toward the level of the voltage V _DH . However, since the NMOS TQN _E is off, there is no current path from the high voltage side power supply terminal 1H to the low voltage side power supply terminal 1L, and the voltage at the point A becomes the level of V _DH .
PMOSTQP _U turns off and PMOSTQN ₂ and NMOS
There is also no current path through TQN ₂ .

Next, when the voltage at the point B becomes low level, in the input circuit of the present invention shown in FIG. 1, the output terminal OUT
Becomes high level, and the voltage at the output point C of the feedback inverter circuit 2 is inverted to a level (low level) of a certain voltage V _L lower than the voltage V _DH . On the other hand, FIG.
In the conventional input circuit shown in FIG.
The condition that a current path is generated toward L, that is, V _DL <V _DH
In the case of −V _TN , the voltage at the point A first rises to the voltage V _DL, but the NMOS TQN _E does not supply the power source voltage V to the gate electrode.
_{Since DH} has been applied, it does not turn off at this point and maintains the conductive state. Then, when the point B becomes low level, the PMOS TQP _U is turned on, so that the voltage at the point A rises and the PMOS TQP _U from the high voltage side power supply terminal 1H →
A current path that flows to the low-voltage side power supply terminal 1L is generated through NMOSTQN _E → PMOSTQP ₁ . Also, this current suppresses the voltage rise at point A, so PMO
STQP ₂ does not turn off, power supply terminal 1H to PMOS TQ
A current path is generated through P ₂ and NMOS TQN ₂ to the ground terminal.

However, in the input circuit of the present invention shown in FIG. 1, when the voltage at the point B becomes low level due to the signal propagation, the voltage at the output terminal OUT becomes high level. As a result, the voltage at the output point C of the feedback inverter circuit 2 drops to the low level _VL and the NMOS TQN _E turns off, so the voltage at the point A rises to the voltage V _DH level. As a result, both of the above-mentioned two current paths are cut off, and the problem that occurred in the conventional input circuit shown in FIG. 5 occurs only in a short time during the transition in the circuit of the present invention. . Other than that, the input terminal IN has the voltage V _DL.
Since the NMOS TQN _E remains in the off state during the period when it is at the level, the above two current paths do not substantially occur, which is not a problem.

Next, when the PMOSTQP ₁ of the output circuit of the low power supply voltage integrated circuit ICL is turned off and the NMOS TQN ₁ is turned on and the potential of the input terminal IN becomes low level (ground level), Since the voltage is a low level but a voltage V _L level higher than the ground level, the NMOS TQN _E is turned on when the voltage of the input terminal IN decreases, and the voltage at the point A is lowered to a low level. Therefore, the voltage at the point B rises to the high level, and the PMOSTQP
Turn off _U. Further, when the point B becomes high level, the voltage of the output terminal OUT becomes low level (ground potential).
As a result, the voltage at the output point C of the feedback inverter circuit 2 becomes the high level voltage (V _DH level), and the NMOS
Turn TQN _E on stronger.

The allowable range of the output low level V _L of the feedback inverter circuit 2 in the present invention is V _L <V _DL + V because the NMOS TQN _E must be turned off when the voltage of the input terminal IN is at V _DL level. It is _TN . Also,
In order that the voltage at the point A becomes low level when the voltage of the input terminal IN becomes low level, it is necessary that the NMOS TQN _E be in a sufficiently ON state. Therefore, V _L <2V _TN
Is at least necessary. Therefore, 2V _TN < _VL + V _TN
Becomes Further, it is desirable that the ON state of the NMOS TQN _E is strong when the point C is at the low level V _L within this range, so the voltage V _L is set to a voltage approximately the same as the power supply voltage V _DL of the low power supply voltage system integrated circuit ICL. Is appropriate.

A more specific description will be given below using examples. FIG. 2 is a circuit diagram of a first embodiment showing an example in which the low level V _L of the output of the feedback inverter circuit 2 in FIG. 1 is set using voltage division by resistors. The feedback inverter circuit 2A includes a resistor R ₁ provided between the power supply terminal 1H and a point C, and a PMOS TQP in parallel with the resistor R _1.
4 , a resistor R ₁ provided between the point C and the ground, a PMOSTQP _{4 in} parallel with the resistor R _1, and a series circuit of a resistor R ₂ and the NMOS TQN ₄ provided between the point C and the ground. PM
The gate electrode of the gate electrode and NMOSTQN ₄ of OSTQN ₄ is connected to the output terminal OUT.

Here, the resistance value of the resistor R ₁ is set to the PMOS TQ
V _L = V _DH × R ₂ / (R ₁ +, where P ₄ is much larger than the on-state resistance value, and resistance R ₂ is much larger than the NMOS TQN ₄ on-state resistance value.
R ₂ ) is set in the range of 2V _TN < _VL <V _DL + V _TN .

Input terminal IN is at low level (= ground potential)
From the low level to the high level (= V _DL ), the output terminal OUT also changes from the low level to the high level (= V _DH ).
TQP ₄ changes from on to off, and NMOS TQN ₄ changes from off to on. In response to this change, the point C changes from the high level voltage V _DH level to the low level voltage V _L. When the input terminal IN changes from the high level to the low level, the output terminal OUT also changes from the high level to the low level. By this, PMO
Since STQP ₄ is turned on and NMOS TQN ₄ is turned off, the level at point C becomes the level of the voltage V _DH .

When the point C is at a low level, in the feedback inverter circuit 2A shown in FIG. 2, a current flows from the power supply terminal 1H through the resistor R ₁ → the resistor R ₂ → the NMOS TQN ₄ toward the ground terminal. _{If 1} and resistor R ₂ having a large resistance value are used, the current consumption can be reduced. Therefore, it is possible to significantly reduce the power consumption as compared with the conventional input circuit shown in FIG.

The gate voltage of the NMOS TQN _E is
In the conventional input circuit shown in FIG. 5, the power supply voltage V _DH itself was used, whereas in the present embodiment shown in FIG. 2, the low level of the voltage at the point C _VL = R ₂ × V _DH / (R ₁ + R ₂ ), even if the voltage V _DH is raised to a high voltage, the rise level of the low level voltage V _L is smaller than that in the conventional input circuit shown in FIG. Therefore, the high level (= V
The allowable range of the voltage V _DH for maintaining the NMOS TQN _E in the OFF state when _DL ) is input is wide, and stable operation is possible.

The resistor R ₁ is a PMOST whose gate electrode is grounded, and the resistor R ₂ is a gate electrode connected to the power supply terminal 1.
Since it can be replaced with the NMOST connected to H, this embodiment can be configured only with the enhancement type PMOST and NMOST. That is, since the depletion type NMOST as in the conventional input circuit shown in FIG. 6 is not required, the manufacturing process can be simplified and the manufacturing cost can be reduced.

Next, FIG. 3 is a circuit diagram of a second embodiment showing an example in which the feedback inverter circuit 2 in FIG. 1 is constructed by using resistors and diodes. The resistor R ₁ and the PMOS TQP ₄ are connected in parallel between the power supply terminal 1H and the point C. Between the point C and the ground terminal, a plurality of MOS diodes QN _a , QN _b , ..., QN _i and NMOSTQN each of which has a gate electrode and a drain electrode connected to each other are formed.
₄ and ₄ are connected in series. The gate electrode of the PMOS TQP _{4 and} the gate electrode of the NMOS TQN ₄ are both connected to the output terminal OUT, and the point C is connected to the gate electrode of the NMOS TQN _E.

Input terminal IN is at low level (= ground potential)
The output terminal OUT also changes to a high level when the signal goes to a high level (= V _DL ), the PMOS TQP ₄ turns off and the NMOS TQN ₄ turns on. As a result, the power supply terminal 1H
Therefore, the resistance R ₁ → NMOS QN _a → QN _b ... QN _i → Q
A current flows through N ₄ , and the potential at point C is low level (=
_VL ). The low level V _{L at} point C is NMOSTQ
The threshold voltage of each of N _a , QN _b , ..., QN _i is set to V _TN.
And the number of MOS diodes formed by the NMOST is i, then V _L = i × V _TN . As described in the explanation of the operation of the circuit diagram shown in FIG. 1, the condition necessary for the circuit of the present invention to operate normally is 2V _TN <V _L <V _DL + V _TN. Therefore, the above equation, V _L = i × V _TN together with M required for normal operation
The number i of OS diodes is 2 <i <(V _DL / V _TN ) +
It becomes 1.

When the potential of the input terminal IN changes from the high level to the low level, the output terminal OUT also changes from the high level to the low level, so that the PMOS TQP ₄ is turned on and the NMOS TQN ₄ is turned off, so that the voltage at the point C is high level. It becomes the level of the voltage V _DH .

As described above, the second embodiment shown in FIG. 3 performs almost the same operation as the circuit of the first embodiment shown in FIG. 2, but differs in the following points. That is, the output low level V _L of the feedback inverter circuit 2B is determined by the number i of MOS diodes. Therefore, the value of the output low level V _L does not change even if the voltage V _DH of the power supply terminal 1H changes, and a wider range than that of the first embodiment shown in FIG. It has an advantage that it operates stably even when the power supply voltage fluctuates.

In the second embodiment shown in FIG. 3, the resistor R
₁ can be replaced with, for example, a PMOST whose gate electrode is grounded. Furthermore, by setting the resistance value of the resistor R ₁ to a sufficiently large value, when the point C is at the low level V _L , the resistor R ₁ → i MOS diodes → N from the current terminal 1H.
Power consumption can be reduced by reducing the current flowing through MOSTQN ₄ .

[0037]

As described above, according to the present invention, the input circuit is provided with the feedback inverter circuit, and when the voltage of the output terminal is at the high level, the NMNOST inserted between the input terminal IN and the first-stage inverter circuit. The gate voltage is lowered to a level lower than the power supply voltage to turn it off.
Therefore, the PMOST of the first-stage inverter circuit is completely turned off to prevent the generation of shoot-through current.

Further, it is possible to stably operate even when the power supply voltage is high.

Furthermore, since it can be manufactured by a normal CMOS manufacturing process without adding a special element such as a depletion type NMOST, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a basic configuration of an output circuit of the present invention and a timing chart diagram during operation.

FIG. 2 is a circuit diagram of the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram of an example of a conventional input circuit.

FIG. 5 is a circuit diagram of another example of a conventional input circuit.

FIG. 6 is a circuit diagram of still another example of the conventional input circuit.

[Explanation of symbols]

 1H, 1L Power supply terminal 2, 2A, 2B Feedback inverter circuit ICH, ICL Integrated circuit IN input terminal OUT output terminal

Claims (6)

(57) [Claims] 1. A p-channel MOSFET is provided so as to form a current path between an input point of a first-stage CMOS inverter circuit and a power supply voltage supply terminal with respect to two-stage CMOS inverter circuits connected in cascade. An n-channel MOSFET is provided so as to form a current path between the terminal and the input point of the first-stage CMOS inverter circuit, and the conduction of these p-channel MOSFET and n-channel MOSFET is in phase with the output signal of the first-stage CMOS inverter circuit. By controlling with a signal, when a high level input signal is applied to the input terminal, the n-channel M
The input terminal and the CMOS of the first stage by the OSFET
The current path to the input point of the inverter circuit is cut off, and the p-channel MOSFET is used to connect the C of the first stage.
In an input circuit configured to raise an input point potential of a MOS inverter circuit to a power supply potential, the n-channel MOSFET is an enhancement type MO
The n-channel MOSFET is provided with a feedback inverter circuit which is composed of an SFET and which generates a signal having a low level potential between the power supply potential and the ground potential in a phase opposite to that of the output signal of the CMOS inverter circuit in the subsequent stage. The input circuit is characterized in that the conduction of is controlled by the output signal of the feedback inverter circuit. 2. A first inverter circuit having a CMOS structure provided between a power supply voltage supply terminal and a ground terminal, and provided between the power supply voltage supply terminal and the ground terminal, wherein the input point is the first A second inverter circuit having a CMOS structure connected to the output point of the first inverter circuit; and an n-channel MOSFET having a drain electrode connected to the input terminal and a source electrode connected to the input point of the first inverter circuit. A p-channel MOSFET having a drain electrode connected to an input point of the first inverter circuit, a source electrode connected to the power supply voltage supply terminal, and a gate electrode connected to an output point of the first inverter circuit, The input point is connected to the output point of the second inverter circuit, and the output point is connected to the gate electrode of the n-channel MOSFET. Input circuit, comprising a feedback inverter circuit which receives an output signal of the capacitor circuit outputs a signal that is between the low potential and the power supply potential and the ground potential provided as the gate potential of the n-channel MOSFET. 3. The input circuit according to claim 1, wherein the low-level output potential of the feedback inverter circuit is substantially connected to the power supply voltage supply terminal and the ground terminal by two resistors connected in series. An input circuit characterized in that the voltage between the two is obtained by resistance division. 4. The input circuit according to claim 3, wherein the feedback inverter circuit includes a parallel circuit in which a resistor and a p-channel MOSFET for signal inversion are connected in parallel, and a resistor and an n-channel MOSFET for signal inversion. And a series circuit in which is connected in series with each other, the series circuit being connected in series between the power supply voltage supply terminal and the ground terminal, and a signal inversion p-channel MOSF forming the parallel circuit.
The gate electrode of ET and the gate electrode of the signal inversion n-channel MOSFET forming the series circuit are connected as an input point, and the series connection point of the parallel circuit and the series circuit is set as an output point. Input circuit to be. 5. The input circuit according to claim 1, wherein the low-level output potential of the feedback inverter circuit is substantially determined by the sum of forward threshold voltages of a plurality of diodes connected in series. An input circuit having the above-mentioned configuration. 6. The input circuit according to claim 5, wherein the feedback inverter circuit includes a parallel circuit in which a resistor and a p-channel MOSFET for signal inversion are connected in parallel, and a gate electrode and a drain electrode are common. Connected at least one or more diode-connected n-channel MOSFETs and n-channel M for signal inversion
A series circuit in which an OSFET is connected in series is connected in series between the power supply voltage supply terminal and the ground terminal, and a P-channel MOSF for signal inversion forming the parallel circuit is formed.
The gate electrode of ET and the gate electrode of the signal inversion n-channel MOSFET forming the series circuit are connected as an input point, and the series connection point of the parallel circuit and the series circuit is set as an output point. Input circuit to be.