JP2561800B2 - Computer system equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to computer systems, and more particularly to shared memory parallel computer systems having multiple processors accessing shared memory.

[0002]

This application is an application related to the following patent applications.

[0003] David B. Rolf, entitled "Interconnect Method and Interconnect Processing Element System", 19
Filed May 13, 1991, US Patent Application No. 07/69
8,866.

T. Barker et al., US Patent Application No. 07 / 888,684, filed May 22, 1992, entitled "N-Dimensional Deformed Hypercube".

US Patent Application 07 / 887,630, filed May 22, 1992, entitled "Improved Parallel Array Processor" by T. Barker et al.

US Patent Application No. 07 / 887,258, filed May 22, 1992, entitled "APAP Input / Output Programmable Router" by M. Dup et al.

No. 07 / 887,259 filed May 22, 1992, entitled "APAP Input / Output Zipper Connection" by T. Barker et al.

T. Barker et al., US Pat. Appl. No. 07 / 887,508, filed May 22, 1992, entitled "Completely Distributed Processing Storage Element".

These applications are owned by IBM Corporation of Armonk, NY.

The statements in these patent applications are incorporated herein by reference.

Some words used in this application are used in a dictionary sense, but some words or terms are defined below.

HPPI High Speed Communication Link A high performance parallel interface (High P) that meets the standards of interface standards defined by the Institute of Electrical and Electronics Engineers (IEEE), American National Standards Institute (ANSI) or other standards accreditation bodies.
erformance Parallel Interface).

Hedgehog Shared Memory System A Hedgehog is a device that integrates shared memory and processing functions used for communication between distributed computer system elements.

Computer system element or computing system element Computer system element or computing system
System elements include elements that can be data-sourced, synchronized, or modified.

Interrupt Processing Routine The interrupt processing routine is a system element that determines the state of the computer immediately after the interrupt.

Link Bandwidth Link bandwidth is the capacity of a line link element to transfer information, usually measured in bytes / second.

ALU ALU (Arithmetic Logic Unit) is a logical operation mechanism part of a processor.

Array An array relates to the arrangement of elements in one or more dimensions. An array can include a side-by-side set of data items (array elements) identified by a single name in languages such as Fortran. In other languages, the name of a side-by-side set of data items represents a side-by-side set or set of data elements that all have the same attributes. Program arrays usually have a dimension specified by a number or dimension attribute. Array declarators also specify the size of each dimension of the array in some languages. In some languages,
An array is the arrangement of elements in the table. In a hardware sense, an array is a set of generally identical structures (functional elements) in a massively parallel structure. An array element in a data parallel computer is an element that, when assigned an operation and parallelized, can perform the required operation independently and in parallel. An array is generally considered a grid of processing elements. Section data can be assigned to sections of an array so that the section data fits in a regular grid pattern. However, the data can be indexed or assigned anywhere in the array.

Array Director An array director is a device programmed as a controller for an array. It performs the function of a main controller for the grouping of the functional elements arranged in an array.

Array Processors Array processors come in two main types. They are,
Multiple instruction multiple data (MIMD) and single instruction multiple data (SIMD). In the MIMD Array Processor, each processing element in the array executes its own instruction stream with its own data. In the SIMD array processor, each processing element in the array is restricted to the same instruction via the common instruction stream, but the data associated with each processing element is unique to each processing element. The preferred array processor of the present invention has other characteristics. Here, it is an advanced parallel array process
r) and use the acronym APAP.

Asynchronous Asynchronous means repeating without the same cycle or time relationship. The results of the execution of one function are unpredictable with respect to the results of the execution of other functions that occur in a regular or unpredictable time relationship. In the control situation, the controller addresses the location to which control is passed when data is waiting for a free element to be addressed. This means that while the operation does not match the event in time,
Allow to remain in order.

Intervention A mechanism by which an I / O port initiates a processor transparent context exchange and uses processor data flow and control paths for self-managed data transfers.

Circuit Switching / Store Switching These terms describe two mechanisms for moving data packets through a node network. Store-and-forward is a mechanism by which data packets are received by each intermediate node, stored in memory, and forwarded to their destination. Circuit switching is a mechanism in which an intermediate node is instructed to logically connect an input port to an output port so that a data packet can pass directly through the node to its destination without going into the intermediate node's memory. is there.

-Intermediate PM so that the circuit-switched message can travel through the intermediate PE towards its final destination without additional processing by the intermediate PME.
A method of data transfer between PMEs in an array, where E logically connects an input port to an output port.

Cluster A cluster is a station (or functional unit) consisting of a control device (cluster control device) and the hardware (terminal, functional unit, or virtual component) coupled to it. The cluster of the present invention comprises a PME array, sometimes called a node array. Usually, the cluster has 512 PMEs. The entire PME node array of the present invention consists of a set of clusters, each cluster supported by a cluster controller (CC).

Cluster Control Device The cluster control device is a device that controls input / output operations for one or more devices or functional units connected to it. The cluster controller is typically controlled by programs stored and executed within the device, as in the IBM 3601 financial communications controller, but can also be fully controlled by hardware, as in the IBM 3272 controller.

Cluster Synchronizer The cluster synchronizer operates all or some of the clusters in order to maintain the synchronized operation of the elements so that the functional unit can maintain a specific time relationship with the execution of the program. It is a functional unit to be managed.

Control Device The control device is a device that manages data and instruction transfer on the links of the interconnection network. The operation is controlled by a program executed by a processor to which the control device is connected or a program executed in the device.

○ CMOS CMOS is a complementary metal oxide semiconductor.
l-Oxide Semiconductor) is an acronym for technology. It is commonly used to fabricate dynamic direct access storage devices (DRAM). N-channel MOS is another technology used to fabricate DRAM. CMOS is preferred here, but the technology used to fabricate APAP is
It does not limit the scope of semiconductor technology used.

DRAM DRAM is a dynamic direct access storage device (Dynamic Random Acces) used in a computer for a main storage device.
s Memory) is an acronym for general memory device. However, the term DRAM is sometimes used as a storage device that is not a cache or main memory.

Floating Point Floating point numbers are represented by two parts, a fixed point or fractional part and an exponent part to an apparent radix or base number. The exponent indicates the actual position of the decimal point. In a typical floating point representation, the real number 0.0001234 is
It is represented as 0.1234-3. 0.1234 is the fixed decimal part and -3 is the index. In this example, the floating point radix or base number is 10, with 10 representing an absolute fixed positive integer base number greater than one. The radix is expressed exponentially in floating-point representation, or raised to the power of the number represented by the index in floating-point representation, and multiplied by a fixed fraction to determine the real number. Numeric literals can be represented in floating point notation and real numbers.

Functional Unit A functional unit is a component of hardware, software, or both capable of achieving the purpose.

Gigabyte Gigabyte represents 1 billion bytes. Gigabytes / sec is 1 billion bytes / sec.

Input Transfer Complete Interrupt A program context exchange request that occurs when an I / O message word is received and it is with a transfer complete tag.

ISA ISA (Instruction Set Architecture) means an instruction set structure.

○ Link A link is a physical or logical element. A physical link is a physical connection for connecting elements or devices. In computer programming, a link is an instruction or address that conveys control and parameters between separate parts of a program. A link in a multiple system is a connection between two systems specified by program code that identifies the link as a real or virtual address. Thus, a link typically includes physical media, communication protocols, associated devices and programs. It is logical and physical.

MIMD In MIMD, each processor in the array has its own instruction stream, that is, a multiple instruction stream, and multiple data (MultipleData) for each processing element.
Used to represent a processor array structure that has to implement.

Modules Modules are discrete, definable program units, or hardware functional units designed for use with other components. A group of PEs included in one electronic chip is also called a module.

O Node Generally, a node is a junction of links. In the general arrangement of PEs, a PE can be a node.
A node can also include a collection of PEs called modules. In the present invention, a node is formed by an array of PMEs, and here, a set of PMEs is called a node. Node is 8P
ME is preferred.

○ Node Array A set of modules formed by PME is sometimes called a node array. A node array usually consists of several PMEs, here containing multiple arrays.

PME or Processor Memory Element PME is a processor memory element (Processor Memory Element).
used to represent t). The term PME is used herein to refer to a processor, memory, I / O capable system element or device that forms one of the parallel array processors. Processor storage element is a term that includes pickets. A processor storage element is a Nth of an array of processors that includes a processor, a memory associated therewith, a control interface, and a portion of an array communication network facility. This element can have processor storage elements with regular array connectivity as in a Pique processor. Alternatively, processor storage elements can be included as part of the sub-array, as in the multiprocessor storage element node described above.

Route Selection Route selection is the assignment of a physical route through which a message reaches its destination. A route selection assignment has a source or origin and a destination. These elements or addresses have temporary relationships or similarities. Often, message routing is based on a key obtained by looking up an assignment table. A destination in a network is a station or network addressable device as the destination for information transferred by a routing address that identifies a link. The destination field identifies the destination with the message header destination code.

Run-time software Software that executes on the processing element. This includes operating systems, monitoring programs, application programs, service programs, etc.

○ All the processors in the SIMD array have one instruction (Single
Instruction) A processor array structure that is instructed to execute a multiple data stream for each processing element.

Swapping Swapping is the exchange of the data content of a storage area with the data content of another storage area.

Synchronous Operation Synchronous operation in MIMD machines is an operating mode in which each action is related to an event (usually a clock). The event may be a specified event that occurs regularly in the program order. Operations are dispatched to multiple PEs that perform their functions independently. Control does not return to the controller until the operation is complete. If the request is for a functional unit array, the request is made by the controller to an element in the array, which element must complete its operation before control returns to the controller.

VLSI VLSI is a very large scale integration (very
Large scale integration).

Zipper Zipper is a newly provided function. The zipper allows linking from an external device to an array of standard interconnects. This feature allows dynamic blocking of a group of network rings. When the network is "zipped", data can cross the ring without entering or leaving the network. When the network is "not zippered", the ring is broken, forming the edge of the network through which data traverses the ring as it enters and leaves the network. The zipper provides the functionality for a broken ring, forming the edge of the network where data traversing the ring enters and leaves the network. Zipper node
A node adjacent to a zipper.

A search of the literature reveals several computer systems with one shared memory and multiple processors. These processing units or functional units and shared memory must be interconnected. Interconnection is through exchange. In this way of interconnecting computers, data enters the exchange at one port and is consumed at another port after a short delay. This transfer, mutual exchange, shift, exchange or route selection function is provided by the exchange. The implementation of the exchange involves buffering the data in the exchange, but the implementation is essentially memory free. When multiple processors are used with shared memory, the data objects are stored in the shared memory device. Those computer systems that have access to the device can share the objects that are there. If some of the computer systems sharing an object have write access to the object, various coherence and legitimacy problems arise. State-of-the-art technology recognizes these problems and there are several solutions.
However, they cannot handle the problem properly in a massively parallel system.

The distributed shared memory computer systems published to date in publications and patents have not addressed the issue of inter-computer communication with shared data in a consistent manner. Some of these publications and patents are cited herein.

Prior Art: Publications 1. In the Transputer Data Book, First Edition 1989, a single chip Inmos system with a processor, memory and communication links available in a network is shown. It has also been cited in previous patent applications, as prior art is again referred to herein to indicate chips that may be used in the network. The elements described in this Inmos publication are:
It can be used to carry out the present invention. However, it does not mean that a transputer chip can be implemented with the present invention. The present invention is preferably implemented with the chips described in the cited related applications. 2. T.A.Clitz et al., IBM Technical Disclosure Bulletin Vol. 27, No. 10X, 1
In March 985, a multi-port bus structure with high speed shared memory is described which allows the construction of distributed systems with networks of any type. 3. IBM Technical Disclosure Bulletin, Vol. 33, No. 11, April 1991, Bacoguri's paper, describes a second-level shared cache and a second-level dedicated implementation to implement a tightly coupled shared-memory multiprocessor. It describes an implementation of a second level shared cache for a multi-processor computer with a common interface to the cache. 4. It must also be taken into account that there are several systems under development with intelligent switching equipment. Previous studies did not mention what is at stake here. Prior Art: Patents The European, Japanese and US patent documents differ from the present invention. 1. Submitted December 19, 1989, Issue No. 429
733 A2, European patent application 893132252.
No. 2 discloses a multiprocessor system and method, with an image graphics processor as an example. The crossbar switch helps establish the processor memory link and the entire image processor is on one silicon chip. However, the exchange is not intelligent and the machine is a SIMD machine, not a SIMD / MIMD machine like the system of the present invention. 2. IBM's Robin Chan, issued October 8, 1991, US Pat. No. 5,056,000, is a shared memory SPMD.
Discloses the use of interconnect switching with. 3. IBM Anderson et al., September 1990
U.S. Pat. No. 4,958,273, issued May 18, discloses a redundancy technique for protecting data. U.S. Pat. No. 5,006,978 issued April 9, 1991, by Philip Nettis of Teradata, Inc. discloses a basic active logic intelligent network without data modules. Both patents disclose memory access / switch networks that support parallel processing between various memory modules. 4. Bolt Veranek, Newman, Carvey and others, US Patent 5,04, issued August 20, 1991.
1,971 discloses a parallel processing computer without an intelligent switching device. IBM Corp.'s Georgeo et al., US Pat. No. 5,072, issued Dec. 10, 1991.
217 discloses a one-sided crosspoint exchange for control of the exchange matrix. Both patents disclose a memory access / switching network that supports parallel processing between different processors and different memory modules. 5. There are other patents on distributed / multi-port memory. For example, U.S. Patents 4,394,726; 4,809,
159; 4,956,772.

When a computer system connection in a parallel system is provided by switching, the number of processors sharing memory makes switching more complex and latency increases non-linearly. This effect limits the use of shared memory to systems with a small number of processors.

Using shared objects in shared memory means that they can change state only through write access by the system's processing units. Write access contention easily grows to unacceptable levels. As processing units are added, the number of processors requesting access to shared memory simultaneously increases. As contention occurs and the number of processors increases, the amount of contention increases. When connections in the system and competitive arbitrators take the form of exchanges, the complexity of competitive arbitration is geometrically proportional to the number of processors.

Alternatives, such as the Thinking Machine CM-5, provide dedicated memory to each system in some way, such as the Inmos chip, and use various interchanges to interconnect them. It is to connect. These systems help avoid problems with shared memory systems. However, the sharing of objects by multiple computers becomes very complex, and the overhead associated with maintaining a consistent view of the shared objects grows non-linearly with the number of processors.

Typically in the prior art, computer systems sharing a DASD or other device are interconnected by various switching or switching networks. Again, as the number of devices increases, sharing complexity and overhead geometrically increases.

All that is required is a processor, shared memory, DASD
And a method for connecting a plurality of functional units to each other, including other devices. It is desirable to connect a large number of diverse system or enterprise components without the tremendous overhead or complexity of adding a device to a computer system.

[0057]

SUMMARY OF THE INVENTION The present invention is directed to the use of a computer system device that provides a multi-port intelligent memory that can be used to connect (swap) various computer system elements (CSEs). Multiport intelligent shared memory is organized into a collection of cells, or nodes referred to herein as hedgehogs. Each node contains a finite amount of computer memory and processing units, and at least K of the links interconnecting the devices have zipper ports. The hedgehog system combines the characteristics of exchange and shared memory. Moreover, objects in the Hedgehog shared memory can change state without CSE interference. Our goal is achieved by implementing the memory and processing elements on the chip with the exchange function. Hedgehog solves the contention and coherence issues that occur in some CSEs that share the hedgehog in the communication network, and these issues do not require explicit communication.

[0058]

The system provides transparent data transfer. The data is sourced from the zipper by the CSE attached to the zipper, and this data can be exchanged for other zippers in the system and thus for the CSE attached to that zipper. The exchange is thus accomplished under the control of processing elements in shared memory. This provides a wide variety of exchanges and allows applications to use the packet header in communications across the network, although this is not required.

The system provides a data reorganization mode. In this mode data is transferred from one CSE to another CSE and the data can be reorganized during this transfer. In this mode of operation, the rows and columns of the matrix may be swapped and the list of elements may be sorted.

A data modification mode of the system is also provided. In this mode, data is changed when it is transferred between CSEs. In this mode of operation, the matrix elements can be scalar multiplied or similarly deformed.

The transparent data sharing mode provides the system with the ability to share data objects by the CSE coupled to the hedgehog. The communication protocol for maintaining the required level of data coherence can be implemented in the Hedgehog chip memory. And these communication protocols do not have to be processed external to the chip. Therefore no external resources are required.

In addition, data sharing can be combined with reorganization. The data in the Hedgehog Chip can be reorganized without the interference of shared systems. The connection system can initiate the reorganization by sending a message to the object on the Hedgehog chip. The shared system does not need to maintain an intermediate state by the communication protocol that executes the communication protocol in the hedgehog, but is unaware of this protocol.

The system also provides changes to data sharing. The data in the Hedgehog chip can be reorganized without the direct interference of the shared system. The connection system can initiate the change by sending a message to the hedgehog object. The shared system does not need to maintain an intermediate state by the communication protocol that executes the communication protocol in memory, but is unaware of this protocol.

Within the Hedgehog Chip, various security / integrity measures can be implemented by associating the chip object with a security token known only to the Hedgehog Chip Processor. Only processes linked to those tokens have access to the object.
This likewise does not require the use of external processing resources of the Hedgehog chip.

Hedgehog chip objects can send messages to each other and initiate state transitions for those objects without the use of external processing resources. In this mode of operation, the Hedgehog CSE element becomes a shared computer resource. By integrating memory, communication and processing functions within the Hedgehog, the communication to ensure coherency between CSEs is dramatically reduced.

Unauthorized access to data can be prevented by the memory itself. Memory latency for all computers is uniform for shared objects. Then, the data format conversion can be executed by the memory of the chip itself.

These improvements are described in detail below. To understand the advantages and features of the present invention, refer to the description and drawings.

[0068]

DETAILED DESCRIPTION Before describing the preferred embodiment in detail, the hedgehog system of the present invention may be described by way of example. Hedgehog devices are high performance switching devices with processing and memory functions. This is the PME described in US patent application 07 / 887,630 filed May 22, 1992, entitled "Improved Parallel Array Processor".
It is realized using the device. 3 hedgehog devices
Shared electronic storage provided by a chip with a 2 kilobyte 16-bit processing element. Each PE can address 64 kilobytes on the Hedgehog chip, or 64 kilobytes of hedgehog memory, which is a collection of shared memory portions on the chip. As described in the above related application, the hedgehog
There are 8 PEs on the chip. This memory / PE chip is called a node.

Each node connects to eight other nodes by an 8x8 bit bidirectional data path. These nodes can be interconnected in various network configurations. One such network configuration is by Rolf,
US patent application Ser. No. 07 filed May 13, 1991, entitled "Interconnect Method and Interconnect Processing Element System"
/ 698,866 and is hereby incorporated by reference. Another such network configuration is
4 is a four-dimensional torus in the preferred embodiment as illustrated by FIG. On the chip, the PEs are connected in an 8-bit unidirectional duplex data path in a cube-bonded network. Therefore, there is one PE for each data path away from the chip, and this data path has a zipper connection port interface. The PE executes the same fixed-point instruction set as illustrated in the improved parallel array processor. It is a known add instruction set.

A set of 64 nodes is called a cluster, and a cluster control device is connected to each cluster. The 64 cluster set can be the entire system or machine, and coupled to the machine is a cluster synchronizer. The control unit and the synchronizer are for input / output operations,
Related to opening network warps with zipper connections for SIMD control, error detection or isolation.
The physical connection to the CSE element is through a high speed communication link, such as HPPI, and the machine performing the link connection can connect to the hedgehog.

Each hedgehog processor has its own instruction counter. The processor can run in MIMD mode. In addition, the cluster controller can broadcast an instruction or instruction address to the PE of the communication network for SIMD mode operation.
Broadcasting the instruction address enables an operating mode that gradually transitions from pure SIMD operating mode to pure MIMD operating mode.

Input / output data travels through high speed communication links, such as HPPI or other links, to hedgehog memory. By presenting data from one link to more than one hedgehog node at the same time, the bandwidth of these links and the input / output bandwidth of the hedgehog node are matched. A hedgehog node bound to a link in this way is called a zipper node. The number of zipper nodes in the Hedgehog memory is set to match the link bandwidth. Therefore, the number of zipper nodes in hedgehog shared memory is K, and K is K =
Required by Bl / Bn. Here Bl is the bandwidth of the link and Bn is the bandwidth of the node. Therefore, K for the preferred chip in the preferred embodiment is 8. This can also be stated in terms of zipper length. Zipper nodes are placed along one dimension of the network. The second zipper is designed to increase the efficiency of certain applications, especially matrix transposition.
Performed along the other dimensions of the system. By using the zipper node and appropriate interrupt handling routines in the node, data can be transferred at the link speed to the hedgehog memory provided the host computer can maintain the link bandwidth. More complex I / O operations are possible as well.

Programming Model The hedgehog shared memory system is MIMD and SIMD.
Can move in mode. MIMD mode is provided by having a program counter in each processing element in the Hedgehog. Hedgehog is basically a multiple instruction, multiple data machine. No operating system is required in each node. All code running in the PE, including interrupt handling routines, can be viewed as application-specific code. this is,
Allows application designers to take advantage of all the properties of the application to optimize efficiency. Certain applications, such as Sort (SORT) or Fast Fourier Transform (FFT), have a deterministic message delivery pattern, thereby eliminating the need to query the packet header to determine the destination of the message.

The SIMD (Single Instruction Multiple Data) machine is implemented by the cluster controller and machine synchronizer in addition to the PE and interconnect network. 64 nodes
Each cluster has one cluster controller, for a total of 6
There are four controllers. There is only one machine synchronizer for the Hedgehog shared memory system. The control bus connects the controller to the node and uses the control bus to
MD operation mode is executed.

In SIMD mode, the same instruction is broadcast to each PE on the control bus and the machines are synchronized on each end operation. In addition, each node directs the fetch and executes the instruction sequence from the memory of each processor. At the end of the order,
The machine is resynchronized. If each order is the same, then this machine is SIMD machine type at the execution macro level. However, if the order of instructions at each node gradually changes during the execution of the application, the system will gradually return to MIMD mode. In this way, the hedgehog shared memory
It turns out that the system begins to make it difficult to distinguish between the MIMD and SIMD modes of the computer.

The present invention is described in detail herein. Figure 1
A preferred embodiment of a shared memory switching device referred to herein as a hedgehog is illustrated. The device includes a communication network that interconnects multiple CSEs as nodes of the device. Each of these CSEs has a multi-port intelligent memory used to connect (exchange) various computer system elements, including computers and direct access storage devices (DASD). Multi-port intelligent shared memory is organized into a collection of cells or nodes. Each node contains a finite amount of computer memory and a processor, with at least K of the device's nodes adjacent to the zipper port. The CSE combines the characteristics of exchange and shared memory. In addition, objects in shared memory can change state without the interference of computers that are now interconnected to hedgehog chips (CSEs and ports). Our objectives are accomplished by implementing the memory and handling elements on the chip along with exchange functionality. PME Hedgehog solves the contention and coherence problems that occur in some computing devices sharing a Hedgehog in a communication network, and these problems do not require explicit communication.

With the system shown in FIG. 2, the transparent data transfer is sourced from the zipper by the CSE whose data is bound to the zipper, and this data is switched to another zipper in the system and thus to the CSE which is bound to that zipper. Provided by. In this way, the exchange is accomplished in shared memory under the control of the processing elements. This provides a variety of switching and application-dependent packet packets in communications across the network.
Allows the use of headers, although not required.

FIG. 3 illustrates the data reorganization mode of the present invention. In this mode, data is transferred from one CSE to another and the data can be reorganized between transfers. In this mode of operation, the rows and columns of the matrix can be swapped and the list of elements can be sorted.

FIG. 4 illustrates the data modification mode. In this mode, the data is modified as it is transferred between CSEs. In this mode of operation, the elements of the matrix can be multiplied by a scalar.

The transparent data sharing mode is illustrated by FIG. In this mode, the data object is shared by the CSE attached to the hedgehog. The communication protocol for maintaining the required level of data coherency can be implemented in the Hedgehog chip memory. And these communication protocols do not have to be processed external to the chip. Therefore no external resources are required.

In addition, data sharing can be combined with reorganization. The data in the Hedgehog Chip can be reorganized without the interference of shared systems. The connection system can initiate the reorganization by sending a message to the hedgehog tip object. The shared system does not need to maintain an intermediate state by the communication protocol that executes the communication protocol in the hedgehog, but is unaware of this protocol.

In addition, the system provides changes to data sharing. The data in the Hedgehog chip can be reorganized without the direct interference of the shared system. The connection system can initiate the change by sending a message to the hedgehog object. The shared system does not need to maintain an intermediate state by the communication protocol that executes the communication protocol in memory, but is unaware of this protocol.

Within the Hedgehog Chip, various security or integrity measures can be implemented by associating the chip object with a security token known only to the Hedgehog Chip Processor. Only processes linked to those tokens have access to the object. This likewise does not require the use of processing resources outside the hedgehog system.

Hedgehog system objects can send messages to each other and initiate state transitions for those objects without the use of external processing resources. In this mode of operation, the hedgehog system becomes a shared computer resource as shown in FIG.

As a result of the development of this system, it is possible to dramatically reduce the communication requirement between computer shared data that guarantees coherence.

Unauthorized access to data can be prevented by the memory itself. The memory latency of all computers is uniform for any shared object. Then, the data format conversion is executed by the memory of the chip itself.

Zipper Description T. Barker et al., US Pat. App. No. 07 / 887,259, filed May 22, 1992, entitled "APAP Input / Output Zipper Connection," changes the network coupling. A method for breaking network coupling is disclosed and a high speed input / output zipper for multiple PME computer systems is disclosed. The system coupling is called a zipper.

The I / O zipper concept of the present invention is that the port to the node is driven by the port from the node or the data coming from the system bus. Also, data located outside a node can be input to both other nodes or the system bus. The output of data to the system bus and other nodes is performed at different cycles rather than simultaneously. Coupling dynamically joins networks between endless networks and networks with ends. When active, the data passes into or out of the network through the edges. Coupling allows the distribution of data that enters the network or the collection of data that leaves the network, with the data rate passing through the edge being consistent with the maximum data rate maintained by systems outside the network.

Zipper allows dynamic destruction of a group of network rings. When "zipped", data can cross the ring without entering or leaving the network. When "unzipped", the ring breaks, forming an edge in the network through which data traverses the ring.

Zipper is described in US patent application Ser. No. 611,594, entitled "Parallel Associative Processor System". This patent application describes the idea of integrating computer memory and control logic in one chip, making a replica of the memory and control logic in the chip and making a processor system from a copy of one chip. There is. This method provides the system with massive parallel processing capability at the cost of developing and manufacturing one chip type,
At the same time, it increases efficiency by reducing chip boundary crossings and line lengths.

The underlying patent describes a one-dimensional input / output structure and the use of multiple SIMD processing memory elements (PMEs) coupled to that structure in a chip. This application and reference-related applications extend the concept to more than one dimension and include a full I / O system with data transfer and program interrupts. The following description is
This is done from the perspective of a four-dimensional input / output structure with 8 SIMD / MIMD PME per chip. However, US Patent Application No. 61
It can be extended to larger dimensions or more PMEs, as described in 1,594.

The above applications and related applications extend the concept from inter-processor communication to external input / output devices. In addition, it describes the interfaces and elements needed to control the processing array. In summary, three types of inputs and outputs are described. (A)
Between processors, (b) Between processor and external device, (c)
Broadcast / control. Massive parallel processing systems require all these types of I / O bandwidth requirements to be balanced with processor computer functionality. Within the array, these requirements are accomplished by making a replica of a 16-bit instruction set structure computer with fast interrupt state exchange capability, referred to below as PME. The characteristics of PME are unique when compared with other processing elements on massively parallel machines. It allows processing, routing, storage and I / O to be fully distributed. This is not a property of any other design.

A block diagram of the improved parallel array processor (APAP) hedgehog array disclosed in detail in the above referenced application is shown in FIG. Hedgehog is included in the set of CSE1s. Data and instructions are CSE
Issued by the communications and control programs running above. These data and instructions are provided by the Array Director's application program interface (AP
I) Received in 2 and translated. The API passes data and instructions to the cluster 5 through the cluster synchronizer 3 and the cluster controller 4. The cluster provides memory for the hedgehog, concurrency and exchange routing. The function provided by the cluster synchronizer and cluster controller is to route data and instructions to the appropriate clusters and to provide load balancing between the clusters.

A cluster consists of a number of PMEs interconnected as a deformed hypercube. In the hypercube, each cell is
Any cell whose address differs by 1 bit can be addressed as adjacent. Two cells whose addresses differ by ± 1 in any cell in the ring can be addressed as their neighbors. The deformed hypercube used for hedgehog combines these methods of making a hypercube from a ring. The intersection of the rings is defined as a node. The nodes are 2n in the preferred embodiment shown in FIG.
PME 20 and Broadcast Control Interface (BCI) 2
Including 1. The PME is configured in the node as a 2Xn array. n represents the number of dimensions or rings that characterize the array and are constrained by the physical chip package. For the preferred embodiment, n is 4. “N”, which increases as chip technology advances, increases the dimensionality of the array.

FIG. 9 shows the formation of PMEs into sequences. 8
The two PMEs interconnect to form node 151. A group of eight nodes interconnect in an X-dimensional ring (16 PME), and another group that overlaps eight nodes interconnects in a Y-dimensional ring 152. This is the node (512
PME) 8 × 8 array with one 2D cluster. The clusters are combined up to an 8x8 array to form a four-dimensional array element 153. Every group of eight nodes across the array elements interconnect in the W and Z dimensions. Interconnects in all four dimensions for one node are shown at 154. Note that the arrays need not be constant or orthogonal. A particular application or machine configuration can redefine the number of nodes in any dimension.

Each PME resides in the only ring of nodes 26 (FIG. 2). The ring is represented by W, X, Y and Z.
The PMEs 20 in the chip are paired (ie + W and -W),
One moves the data clockwise along the ring of nodes and the other moves the data counterclockwise outward along the ring of nodes 23, 26. Thus, PME is provided to the external port of each node. Two PMEs in each ring are designated by their external input / output ports (+ W, -W, + X, -X, + Y, -Y, + Z, -Z). Also within the node are two rings 22 interconnecting four + n and four -n PMEs. These inner rings provide a path for messages to travel between outer rings. Since APAP is considered a four-dimensional orthogonal array 151-154, the inner ring allows messages to move through the array in all dimensions. This is an addressing scheme where any PME can send a message to an object by addressing the PME into a ring of nodes or by addressing adjacent PMEs within a node.

In FIG. 10, each PME has four input ports and four output ports (85, 92 on the left and 8 on the right).
6, 95, vertical 93, 94, and external 80, 81). Three of the output ports and three of the input ports are full-duplex point-to-point connections to other PMEs on the chip. The fourth port provides a full-duplex point-to-point connection for off-chip PMEs. Due to the pin and power constraints in the preferred implementation physical package, the actual input / output interface is a 4-bit wide path 97, 98, 99 which is used to multiplex 4 nibbles 96, 100 of inter-PME data words. used. These are illustrated in FIG.

In the preferred embodiment, the PME I / O design provides three I / O modes of operation.

Normal mode: Used to transfer data between two adjacent PMEs. Data transfer is PME
Started by software. Data that is assigned a PME farther than the adjacent PME must be received by the adjacent PME and sent as if it was sent by the adjacent PME. Normal mode is described in detail in a related application entitled "PME Store and Exchange / Circuit Exchange Mode".

Circuit switching mode: Enables data and control to pass to the PME. This enables high speed communication between PMEs that are not directly adjacent. The circuit switching mode is described in detail in the relevant application entitled "PME Store and Switch / Circuit Switching Mode".

Zipper mode: Used by the array controller to load or read data from the nodes in the cluster. Zipper mode uses normal and circuit-switched mode mechanisms for fast transfer of data from PME arrays on cluster cards.

Each ring in the arrays W, X, Y and Z is continuous. There are no "edges" in the sequence. Conceptually, a zipper is a logical break in the ring at the interface between two nodes to form a temporary end. If the zipper is inactive, the array has no edges. When the zipper is activated, all interfaces between the two columns of nodes are broken so that the "edge" is used for data transfer between the array and array controller. Referring to FIG. 11, if, for example, a zipper connection is placed on the -X interface along the node's X = 0 line, the node's X = 8 (PME
The interface between line xl5) 250 and line X = 0 (PME xO) 253 has a third (host) interface 251 which is no longer a point-to-point connection. Normal data is PME xO as if the host interface was not there.
Cross between 253 and PME xl5 250. However, when the zipper is activated under PME runtime software control, the data will be stored in arrays 250, 253 and host 251
Transfers through the temporary ends of the array. A zipper along one row in one cluster breaks the ring at eight nodes. The preferred embodiment, based on modern technology, can transfer approximately 57 megabytes per second through one zipper in one cluster. Future scientific and technological advances, including optical connections, are expected to significantly increase this data rate.

FIG. 12 illustrates how this concept can be expanded to place zips at the two "edges" 255, 256 of the cluster. This method increases the I / O bandwidth to approximately 114 megabytes / second when different data is transferred to each zipper. Alternatively, if the same data were transferred to each zipper, it would support approximately 57 megabytes / second of orthogonal data manipulation in the array. Orthogonal data manipulation supports fast transposition within arrays and multiple matrix manipulation. In theory, a zipper can exist on any internode interface. As a practical matter, each PME with a zipper interface must be able to transfer array I / O data to another PME so that it can avoid filling the memory and receive more data. The number of zippers is
The memory capacity of the PME and the zipper data are limited by techniques that determine the rate at which it can be transferred between the PME on the zipper and other PMEs in the array.

The preferred embodiment of the zipper has two modes of operation: zipper input and zipper output. The zipper input operation transfers data from the array controller to any group of PMEs on the cluster. Zipper input operation,
Started by array controller run-time software.
The array controller run-time software first sends a PME SIMD mode broadcast command to set the PME to one of two modes: normal zipper (ZN) or zipper circuit exchange (ZC) along the zipper interface. (See "SIMD / MIMD processing memory element" above). The array controller run-time software then puts the SIMD PME software in ZN mode and provides word count.
In ZN mode, the PME uses the X interface 80 (Fig. 1
0) can receive data. But before that, you must set up an input buffer in memory for that interface. Two locations in memory are reserved to contain the starting address 232 of each input data buffer and the number of words 233 contained in the buffer. In addition, the PME control register 2 (Fig. 14)
Includes mask bit, 173, enabling input interface, 172 enabling I / O interrupts. Broadcast SI
The MD PME software loads the reserved memory location to define the output data block and the PME control register 2 to allow the input data transfer. In ZN mode, the PME waits for an I / O interrupt in the empty state or shifts to ZC mode.

The zipper input operation for one possible mechanical configuration of the PME is shown in FIG. here,
An example of 8-word transfer to three different PMEs is shown. Data interface (zipper)
Transfer to PME 260 and move from PME to PME through array. In the preferred embodiment, the array controller first
PE A 260, B 261, D 263 in ZN mode, PE C
Set the 262 in ZC mode. "Z" 163 and "CS" 1 of PME control register 1 for zipper input operation
Set 70 bits to set PME to ZC mode.
Setting the "Z" 163 bit and resetting the "CS" 170 bit puts the PE in ZN mode. PEA, B, D
Are assigned initial counts of 3, 4, and 1, respectively. PE A receives three data words using the normal receive order. When the word count reaches zero, PE A
The hardware is "CS" 170 of PME control register 1.
Reset the bit and put PE A 264 in ZC mode. P
The same order occurs for EB 269 and D 271. (PE D
Upon the final word transfer 271 (to), the alignment controller may insert a transfer complete tag (TC) bit 224. When the TC bit is set, PE A-D will detect the bit and generate an I / O interrupt 171 request. TC2
If the 24 bit is not set, PE A-D will remain in ZC mode 272-275 upon completion of the transfer.

When the request 240 is detected on the zipper interface, the receiving PME sends a response 241 to load the input register 87 with the data. The reception sequence then begins. It subtracts count 233, adds input buffer address 232, and stores the data word in PME memory 41. The reception order is similar to the transmission order. The reception order is I / O address and count
Waiting to cycle steal access to memory 41 and ALU 42 to update fields and load memory 41 with input data words, free
Intervene in PME. This sequence continues until the count reaches zero and the mode is swapped to ZC, or until a TC tag is received and the corresponding input interrupt register bit 171 is set with an interrupt code 190 indicating "transfer complete". .

The PME responds to the request and generates a response if the following conditions are met: The input registers 87 and 100 are not set. ○ The request is not prohibited 174. The interrupt 182 is not pending for the request input. ○ The request input has not been replaced. O The request has the highest priority of all current requests.

The input registers 87, 100 have a response 226.
Is generated and is in use until the reception order stores the data word in memory. Responses are prohibited when the input register is busy. The usage state prevents the input register from being overwritten before the receive order occurs (since the receive order may be delayed due to memory refresh).

When the TC tag bit 224 is sent out of the transmit zipper, the I / O interrupt latch 171 is set for that interface. The next response 226 on that interface will not be generated until the interrupt latch is reset by the PME runtime software. For example, if the TC tag bit 224 is set during a data transfer from the X interface 82, the next request from X will be inhibited until an L interrupt occurs and the L interrupt latch is reset.

If the data word is transferred with the TC tag 224 bit set and the receiving PME is in ZN mode:
An I / O interrupt 171 is generated for the external interface and an interrupt code 190 is set reflecting TC. In addition, if the buffer count reaches zero before the TC tag is sent from the transmit zipper, the PME goes into ZC mode.

When the PME is in ZN receive mode, it
Only memory refresh order and receive order for zipper inputs can be performed. This is necessary to allow zipper data transfers at maximum PME clock speeds. No time is given to the receiving order for PME command execution or non-zip input. In ZN mode
PE hardware prohibits all input requests except zipper input requests. The ZC mode PME can perform all the operations of the PME in the circuit switching mode. This includes the ability to use the split submode on zipper data.

The zipper output operation is performed on any PM of the cluster.
Transfer data from group E to the array controller. The zipper output operation is initiated by the array controller run-time software. And it first uses the SIMD mode broadcast command to place the PME around the zipper interface in one of two modes: zipper normal mode, zipper circuit exchange mode. The array controller run-time software provides the word count to send to the PME SIMD software in ZN mode.

Conceptually, data is transferred from the source PME's main memory to the CSE's buffer memory.
2 for each interface in the preferred embodiment
A location in one memory is reserved to have the starting address 230 of the output data block and the number of words 231 contained in the block. In addition, PME control register 1
(See FIG. 14) controls the destination and mode of data output. Broadcast SIMD PME software loads PME control register 1 to define the transfer mode. Broadcast SIMD PME software or PME runtime software loads a given memory location with the data to transfer to the host. The broadcast SIMDPME software then loads the address and count into the predetermined memory location. Then it loads the PME control register 1 and finally executes the output instruction which starts the data transmission sequence.

The zipper output operation for one possible mechanical configuration of the PME is shown in FIG. Here, an example of 8-word transfer to three different PMEs is shown. The data interface (zipper) transfers data from the PME 280 and moves through the array from PME to PME.

In this example, the array controller first
Set PE A 280, B 281, D 283 to ZN mode and PE C 282 to ZC mode. For zipper output operation, set "Z" 163 and "CS" 170 bits of PME control register 1 to put PME in ZC mode. Setting "Z" 163 and resetting "CS" 170 puts the PME in ZN mode. PMEs A, B, D are assigned counts 3, 4, 1. PME A sends three data words using the normal transmission order. When the word count reaches zero, the PME A hardware is
Reset "CS" 170 bit of control register 1 to PM
The EA 284 goes into ZC mode. PME B 289 and
The same sequence occurs at D 295. On the last word transfer (from PME D), PME D inserts a 224 bit transfer complete (TC) tag if the "TC" 164 of PME D's PME control register is set. When the TC tag is set, PME A-D will detect the bit and generate an I / O interrupt 171 request. If the TC tag is not set, the PME A-D will remain in ZC mode when the transfer is complete.

When each data word is transmitted, the transmission order is such that the count 231 is subtracted, the start address 230 is added, and the data word is read from the memory 41. The data word is loaded into the transmit registers 47, 96 and stored in any PME.
97, 161 to the interface. The transmit order intervenes in the free PME waiting for cycle steals to access the memory 41 and ALU 42 to update the I / O address and count fields and load the transmit registers 47, 96. For zipper transfers, CX bit 165 of the PME control register is set so that the PME processor remains idle until the transmission order is complete. This sequence continues until the count reaches zero.

The data transfer interface has a 4-bit width of 97. Therefore, each 16-bit data word 220 is transmitted by 4 bits (1 nibble). Also, the tag nibble 221 and the parity nibble 222
Is transmitted with the data. The transfer format is shown at 223. The transmission order is shown in FIG. On the interface, the sending PME makes a request 225 to the receiving zipper interface. When the response 226 is received, the sending PME initiates the data transfer and another order of transmission occurs. The next transmission order does not occur until the response is received.

When TC bit 164 is set in PME Control Register 1, TC bit 224 is set in the tag field of the last data word transferred. This bit informs the receiving zipper that the data transfer is complete.

When the PME is in ZN transmit mode, it can only perform transmit and memory refresh order. This is necessary to allow zipper data transfers at maximum PME clock speeds. Time is not given to the receive order for PME command execution or non-zip input. In ZN transmission mode, PME hardware prohibits all input requests. PME in ZC mode
Is capable of all PME operation in circuit-switched mode. This includes the ability to use the split submode on zipper data.

The zipper interface connects the array controller to the nodes on the cluster, as shown at the top and bottom of FIG. The normal interface is
It consists of a two nibble (8-bit) unidirectional point-to-point interface that provides bidirectional full duplex transfer between two PMEs. The process described for 6 nibble transfers from one PME to another PME in "PME store and switch / circuit switch mode" is used here. Information is essentially 20 on the left.
Transferred from PME on 0 using data path 202, request line 203 and response line 204. At the same time, information is transferred from the PME on the right 201 using data path 210, request line 211 and response line 212. When the zipper is installed on the interface, the data path 214, the request line 215, and the reply path 21.
6 is added to transfer the data to the array. The data path 217, request line 218 and response path 219 are then added to retrieve the data from the array. The array controller runtime software causes the PME 200 runtime software to disable 202, 203, and 204 when it wants the PME 201 to perform the zipper transmission order. Similarly, when the array control device runtime software wants the PME 200 to execute the zipper reception order, the runtime software of the PME 201 is
The use of 0, 211 and 212 is prohibited.
Note that the placement of the zipper logic is completely arbitrary in its implementation. It's easily + X and -X on the same node
It can be placed on the interface or on any or all of the W, Y, Z node interfaces.

System Architecture The advantage of the system architecture used in the preferred embodiment is the ISA system. This will be easily understood by those skilled in the programming of APAP. The PME ISA consists of the data and instruction format shown in the table below.

Data Format The basic (operand) size is a 16 bit word. In PME storage, operands are placed on integer word boundaries. In addition to the word operand size, other operand sizes are 1 to support additional functionality.
A multiple of 6 bits is obtained. Everywhere in the operand length, the bit positions of the operands are numbered consecutively, starting from 0, from left to right. References to the most or most significant bit always represent the leftmost bit position. References to the least significant or least significant bit always represent the position of the rightmost bit.

Instruction Format The length of the instruction format is 16 bits or 32 bits. In PME storage, instructions must be on 16-bit boundaries. The following general instruction format is used. Usually, the first 4 bits of an instruction define the instruction code and are called OP bits. Additional bits may be needed to extend the definition of an instruction or to define instruction-specific conditions. These bits are called OPX bits.

[0124]

Format Code Manipulation RR Register to Register DA Direct Addressing RS Register Storage RI Register Immediate SS Storage to Storage SPC Special All formats have one field in common. The fields and their descriptions are shown below. Bits 0-3 Op Code: This field, together with the Op Code Extension field, sometimes define the operation to be performed.

A detailed table for each format is given below, along with a description of the fields. For some instructions, the two formats are combined to form a variety of instructions. These mainly include addressing modes for instructions. For example, storage to storage instructions have the form including direct addressing or register addressing.

RR Format The Register to Register (RR) format provides the addresses of two general purpose registers and is 16 bits long as shown.

[0127]

[Table 2] The RR format has the following areas in addition to the instruction code. Bits 4-7 Register Address 1: The RA field is used to specify which of the 16 general purpose registers are used as operands or destinations. Bits 8-11 Zero: A zero in Bit 8 defines that this format is an RR or DA format, and a zero in Bits 9-11 indicates that the operation is a register-to-register operation (direct address format). Special case). Bits 12-15 Register Address 2: The RB field is used to specify which of the 16 general purpose registers are used as operands.

DA Format The Direct Address Format (DA) provides a general register address and a direct storage address, as shown.

[0129]

[Table 3] The DA format contains the following areas in addition to the opcode field. Bits 4-7 Register Address 1: The RA field is used to specify which of the 16 general purpose registers are used as operands or destinations. Bit 8 Zero: This bit, which is zero, defines that the operation is a direct address operation or a register-to-register operation. Bits 9-15 Direct Storage Address: The Direct Storage Address field is used as an address to a level-specific or common storage block. Bits 9-11 of the direct address field must be non-zero to define the direct address format.

RS Format Register Store Format (RS) provides one general purpose register address and an indirect store address.

[0131]

[Table 4] The RS format contains the following areas in addition to the opcode field. Bits 4-7 Register Address 1: The RA field is used to specify which of the 16 general purpose registers are used as operands or destinations. This bit, which is Bit 8 1: 1, defines that the operation is a register storage operation. Bits 9-11 Register Data: These bits are considered signed values used to modify the contents of the register specified by the RB field. Bits 12-15 Register Address 2: The RB field is used to specify which of the 16 general purpose registers will be used as the storage address for the operand.

RI Format The Register Immediate Value Format (RI) provides one general purpose register address and 16 bits of immediate data. The RI format is 32 bits long as shown.

[0133]

[Table 5] The RI format includes the following areas in addition to the opcode field. Bits 4-7 Register Address 1: The RA field is used to specify which of the 16 general purpose registers are used as operands or destinations. This bit, which is Bit 8 1: 1, defines that this operation is a register storage operation. Bits 9-11 Register Data: These bits are considered signed values used to modify the contents of the program counter. Normally, this field has a value of 1 in the register immediate format. Bits 12-15 Zero: This field, which is zero, is used to specify that the updated program counter, which points to the immediate data field, is used as the storage address for the operand. Bits 16-31 Immediate Data: This field is a 16-bit immediate data operand for register immediate instructions.

SS Format The storage to storage (SS) format provides two storage addresses: an explicit address and an implicit address. The implicit storage device address is contained in general register 1. Register 1 is updated during the execution of the instruction. SS
There are two types of instructions: direct address format and storage address format.

[0135]

[Table 6]

[0136]

[Table 7] The SS format includes the following areas in addition to the opcode field. Bits 4-7 Extended Op Code The OPX field, together with the op code, defines the instruction to be executed. Bit 4
-5 defines an operation type, such as addition or subtraction.
Bits 6-7 control how carry, overflow, and condition codes are set. When bit 6 is 0, overflow is ignored and when bit 6 is 1, overflow is allowed. When bit 7 is 0, the carry state during operation is ignored, and when bit 7 is 1, the carry state during operation is included. Bit 8 Zero: Defines that the format is a direct address format. 1: Define that the format is a storage device address format. Bits 9-15 Direct Address (Direct Address Format): The direct storage address field is used as an address to a level-specific or common storage block. Bits 9-11 of the direct address field must be non-zero to define the direct address format. Bits 9-11 Register Delta (Storage Address Format): These bits are used to modify the contents of the register specified by the RB field,
Considered a signed value. Bits 12-15 Register Address 2 (Storage Address Format): The RB field is used to specify which of the 16 general purpose registers is used as the storage address for the operand.

SPC Format 1 The special (SPC1) format provides one general purpose register storage operand address.

[0138]

[Table 8]

[0139]

[Table 9] The SPC1 format includes the following areas in addition to the opcode field. Bits 4-7 Extended OP: The OPX field is used to extend the opcode. Bit 8 Zero or 1: When this bit is zero, this operation defines a register operation. When this bit is 1, it defines that the operation is a register storage operation. Bits 9-11 Operation Length: These bits are considered unsigned values used to specify the operand length of a 16-bit word. A value of zero corresponds to a length of 1 and a value of B "111" corresponds to a length of 8. Bits 12-15 Register Address 2: The RB field is used to specify which of the 16 general purpose registers will be used as the storage address for the operand.

SPC Format 2 The special (SPC2) format provides one general register storage operand address.

[0141]

[Table 10] The SPC2 format contains the following areas in addition to the opcode field. Bits 4-7 Register Address 1: The RA field is used to specify which of the 16 general purpose registers are used as operands or destinations. Bits 8-11 Extended OP: The OPX field is used to extend the instruction code. Bits 12-15 Register Address 2: The RB field is used to specify which of the 16 general purpose registers will be used as the storage address for the operand.

The ISA instruction list is shown below.

[0143]

[Table 11]

[0144]

[Table 12]

[0145]

[Table 13]

[0146]

[Table 14]

[0147]

[Table 15]

[0148]

[Table 16]

[0149]

[Table 17] While a preferred embodiment of this invention has been described above, it will be appreciated by those skilled in the art that various modifications and extensions can now and in the future be made within the scope of the invention.

[0150]

Since the present invention is constructed as described above, it is possible to provide a multi-port intelligent memory which can be used for connection (exchange) of various computer system elements.

[Brief description of drawings]

FIG. 1 shows multiple hedgehog CSE elements and zipper ports as part of a connection network with multiple network nodes for various data operations.
FIG. 3 is a schematic diagram of a preferred embodiment.

FIG. 2 is a diagram showing a data transparent mode for simple data transfer.

FIG. 3 shows a data reorganization mode for data transfer in space.

FIG. 4 illustrates a data modification mode that provides scale and image rotation functions.

FIG. 5 is a diagram showing a data sharing mode of a zipper interface and a hedgehog chip.

FIG. 6 is a diagram showing how a hedgehog CSE element with memory and zipper interface shares active data objects and provides object state changes in a chip without the interference of external resources. is there.

FIG. 7. In particular, the main elements of the hedgehog and a set of CSE
FIG. 3 is a functional block diagram of an exemplary hedgehog array showing the hedgehog interface to the.

FIG. 8 is a schematic diagram of a processing storage element node showing the interconnection of the various elements that form the node.

FIG. 9 is a schematic view of a modified binary hypercube.

FIG. 10 is a schematic diagram of a circuit switching path.

FIG. 11 is a schematic diagram of a zipper connection on one PME-to-PME interface.

FIG. 12 is a schematic diagram of two orthogonal connection zipper connections to a cluster.

FIG. 13 is a schematic diagram of a reserved storage area for interrupt and input / output processing.

FIG. 14 is a schematic diagram of PME control registers supporting the implementation of interrupt and interconnect networks.

FIG. 15 is a schematic diagram of a zipper receiving order.

FIG. 16 is a schematic diagram of input interface ordering between PME inputs and outputs.

FIG. 17 is a data flow diagram of a processing storage element (PME). The data flow principles section includes main memory, general registers, ALUs and registers, and parts of the interconnection network.

FIG. 18 is a schematic diagram of data words transferred between tags, parity, PME input and output.

FIG. 19 is a schematic diagram of a zipper transmission order.

FIG. 20 is a schematic diagram of a PE input / output data flow.

FIG. 21 is a schematic diagram of output interface ordering between PME inputs and outputs.

FIG. 22 is a schematic diagram of a physical zipper interface.

[Explanation of Codes] 1 Computer System Element 2 Application Processor Interface 3 Cluster Synchronizer 4 Cluster Controller 5 Cluster

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Clive Alan Collins United States 12601 Pokey Sis Monroe Drive, New York 9 (72) Inventor Kristin Marie Desnoyer United States 12566 Pine Bush, Upper Maun Ten Road 858 (72) Inventor Donald George Grice United States 12401 Kingston Sawkill Ruby Road, New York 2179 (72) Inventor David Bruce Rolf United States 12491 West Harley Box, New York 215 A

Claims (4)

(57) [Claims] 1. A plurality of functional units each having an ALU, a memory connected to the ALU, and a communication interface; and a functional unit in which the various functional system units including a computer and a direct access storage device are combined with each other. A cell or node having means for interconnecting to a collective network of cells or nodes thereof, wherein the memory of the functional unit is used for switching connection of various computer system elements including the computer and the direct access storage device. Means for providing a function for exchanging the shared memory defined in paragraph 5, K of the nodes for which the shared memory exchanging function is defined are adjacent to zipper ports, and the network and the functional unit are connection switching. Memory and the functions of a shared memory processor And means for providing a processor, the computer system unit. 2. The computer system device of claim 1, wherein the contents in the shared memory can be modified independently of the computer system elements interconnected to the device. 3. The computer system device of claim 2, wherein each of the K nodes of the device comprises a hedgehog having memory and processing capabilities. 4. The device provides transparent data transfer, wherein data is exchanged by a computer system element that is coupled to the zipper from any zipper to a computer system element that is coupled to another zipper. Being accomplished under control of a processing element in shared memory, and providing, but not requiring, various exchanges, authorizations of packet header usage in communications across the network. Item 4. The computer system device according to item 3.