JP2558769B2 - Bit synchronization circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization circuit that extracts a clock component using an NRZ (Non-Return-to-Zero) signal.

2. Description of the Related Art Generally, in data communication, a transmission clock is regularly generated on the transmission side, but it is not possible to separate the data and the transmission clock into two lines for the convenience of the communication line. Only the line is transmitted.
Then, on the receiving side, from this received data signal sequence, "01, 1
The change point of "0" is detected, and the data and the reproduction clock are separated and extracted.

However, when the data signal is continuously transmitted like "1111" and "0000", this recovered clock is
Alternatively, if noise is mixed in, the change point of “01, 10” cannot be correctly detected, so that there is a problem that the data and the reproduction clock cannot be synchronized.

Therefore, a bit synchronization circuit is required to synchronize this data with the reproduction clock.

FIG. 5 shows a conventional bit synchronization circuit, 31 is NRZ.
The signal input terminal, 32 is an edge differentiating circuit that differentiates the NRZ signal and generates pulses at the rising edge and the falling edge of the NRZ signal, and 33 is composed of a plurality of stages of flip-flops, etc. This is an up-down counter that outputs an up-carry 35 or a down-carry 36 according to a pulse from 32 and an up command or a down command from a D flip-flop 37 described later. The number L of stages of the up-down counter 33 is set from an input terminal 34. To be done.

The up / down counter 33 outputs the up carry 35 when the outputs of the L + 1th stage flip-flops are “1” and outputs the down carry 36 when the outputs of all the flip-flops are “0”. Is configured.

38 is an input terminal for the reference clock signal (frequency fo), 37
Is a frequency divider circuit described later in synchronization with this reference clock signal.
A D flip-flop (D-FF) 39 for latching the reproduced clock signal from 40 and comparing the phases of both signals is provided with a reference amount every time the up carry 35 or the down carry 36 from the up / down counter 33 inputs. A variable frequency divider circuit that divides the reference clock signal by increasing or decreasing the frequency number n by a predetermined frequency difference number Δn, and 40 is a signal that is frequency-divided by the variable frequency circuit 39 and is divided by a fixed frequency number m. Frequency and playback clock signal (frequency
The frequency _{dividing circuit} outputs f _T ) to the output terminal 41 and the D terminal of the D flip-flop 37.

 Next, the operation of the above conventional example will be described.

In FIG. 5, the variable frequency dividing circuit 39 divides the reference clock signal into 1 / n when the up / down counter 33 does not output the correction command, and the frequency dividing circuit 40 divides this frequency-divided signal. Outputs the recovered clock signal divided by a fixed ratio (1 / m). In this case, when the transmission rate of the NRZ signal is f _T , the frequency f _T of this reproduced clock signal is obtained.

Here, the frequency dividing number m of the frequency dividing circuit 40 is set in advance to an even number so that the pulse occupancy rate of the reproduced clock becomes 50%.
Further, the frequency dividing number n of the variable frequency dividing circuit 39 is set to n = f _O / mf _T , and the up / down counter 33 is set to its initial value 2 ^L according to the number of stages L set via the terminal 34. Is set.

The D flip-flop 37 compares the phase of the reference clock signal with the phase of the reproduced clock signal from the frequency dividing circuit 40. For example, when the phase of the reference clock signal is later than that of the transmission clock, the up / down counter 33 is operated. When the up-down counter 33 is set to the up-count mode and therefore the up-down counter 33 outputs the up-carry 35, the variable frequency divider circuit
39 increases the frequency division number n by a predetermined frequency division number difference Δn to match the phase of the reference clock signal with the phase of the reproduction clock signal.

Further, when the phase of the reference clock signal is ahead of that of the transmission clock, the up-down counter 33 is set to the down-count mode, so that the up-down counter 33 outputs the down carry 36 each time the variable frequency divider circuit is output. 39 reduces the frequency division number n by a predetermined frequency division difference Δn, and matches the phase of the reference clock signal with the phase of the reproduction clock signal.

Here, the operation of FIG. 5 will be described in detail. Figure 6 shows
FIG. 9 is a timing diagram of a conventional bit synchronization circuit shown in FIG. 5.

For convenience of explanation of FIG. 6, the number of stages L of the up-down counter (33) of FIG. 5, the standard frequency division number n of the variable frequency dividing circuit (39) n = 18, and the frequency division of the frequency dividing circuit (40). Number m = 1, frequency difference Δ
Let n = ± 1.

First, in FIG. 5, a reference clock (38) and received data (31) are input. Point A in FIG. 6 shows that the phase of the received recovered clock is advanced by (1/18) × 2 bits with respect to the transmission phase.

The edge differentiating circuit (32) displays the received data (31) as "01,
Every time the change point of 10 ”is detected, a signal is output and is output to the up / down counter (33). Since the recovered clock signal (41) is “1” at point A in FIG.
(37) gives a countdown instruction.

In the up-down counter (33), when the signal from the essie differentiating circuit (32) arrives, the down carry signal (36) is immediately transferred to the variable frequency dividing circuit (39) because the counter (33) has one stage. Output. The variable frequency dividing circuit (39) uses the down carry signal (36) to change the frequency dividing number n to "n-Δ.
Change to "17" based on the calculation of n = 18-1. This is shown in the sections (a) and (b) of FIG.

However, since there are 2/18 bits from the start point A to the section (a), it is not possible to correct only with the sections (a) and (b), and the section (c) in the next section (c) and (d) Similar to (a) and (b), the frequency dividing number n of the variable frequency dividing circuit (39) is changed to "17" based on the calculation of "n-Δn = 18-1".

In sections (e) and (f), since the received data (31) remains unchanged at "11", the edge differentiation signal (32) is not output and the up / down counter (33) is up carry signal, down carry signal. No signal is output.

In the sections (g) and (h), the edge differentiation circuit (3
When the signal of 2) comes, since the reproduction clock (41) is "0", the up carry signal (35) is output to the variable frequency dividing circuit (39).

Then, in the sections (ri) and (nu), when the signal from the edge differentiating circuit (32) arrives, the recovered clock (41)
Is "1", the down signal (35) is divided by the variable frequency divider (3
Output to 9).

In this way, the rising edge of the reproduction clock (41) is configured to be synchronized with the rising edge of the received data (31) even in the conventional bit synchronization circuit.

In the conventional example, as shown in FIG. 5, when there are 2/18 bits from the start point A to the section (a), 2-bit sections (a) to (d) are required. It will be synchronized.

Thus, in the above conventional example, the up / down counter is
As the number of stages of 33 increases, the correction frequency decreases and the jitter of the reproduced clock decreases, but the rising characteristics of the circuit deteriorate.

On the other hand, as the number of stages of the up / down counter 33 decreases, the correction frequency increases and the jitter of the reproduced clock increases, but the rising characteristics of the circuit are improved.

Therefore, in the above-mentioned conventional example, when the NRZ signal rises, the number of stages L of the up / down counter 33 is set to be small to speed up the rise of the circuit, and when the circuit rises, the number of stages L of the up / down counter 33 is set to be large. It is possible to reduce the jitter of the reproduced clock.

As a signal for setting the number of stages L of the up / down counter 33, a bit synchronization establishment signal, a frame synchronization establishment signal, or the like is used.

Further, as a second conventional example, as disclosed in Japanese Patent Application No. 58-139944 (Japanese Utility Model Application No. 60-47357), the phase of the phase can be changed by changing the correction width of the synchronous pull-in. There is one that speeds up the pull-in and reduces the jitter in the synchronized state.

However, in the conventional bit synchronization circuit described above, the correction frequency of the reproduction clock can be changed by switching the number of stages L of the up / down counter 33, but the correction width Δn in one switching is There is a problem in that it is not possible to obtain a reproduction clock signal that is constant and highly stable.

Further, in the second conventional example, when an erroneous correction signal is generated due to noise after the synchronization pull-in, the correction frequency is the same as that during the synchronization pull-in, so that it is easily affected by this noise and becomes unstable. There was a flaw.

Further, even if the first and second conventional examples are combined, the number of stages of the up / down counter and the frequency division ratio of the variable frequency dividing circuit may be changed in association with each other at the time of synchronous pull-in and after the synchronous pull-in. Because it is not
There is a problem that it is not possible to solve both the early start-up at the time of synchronization pull-in and the suppression of jitter after the synchronization pull-in at the same time.

In view of the above problems, it is an object of the present invention to provide a bit synchronization circuit capable of reducing the jitter of a reproduced clock signal and obtaining a highly stable reproduced clock.

Means for Solving the Problems In order to solve the above problems, the present invention controls so that the frequency division number of a variable frequency dividing circuit is changed at a rising time with a relatively large frequency division difference, and after the rising time, the variable frequency dividing The frequency division number of the frequency circuit is changed with a relatively small frequency division number difference.

Effect The present invention, which has the above-described configuration, can realize a fast rising characteristic because the frequency dividing number of the variable frequency dividing circuit is changed at a rising time with a relatively large fractional difference, and after the rising, a relatively small frequency dividing number difference. Therefore, the jitter of the reproduction clock signal can be reduced, and the reference clock signal and the reproduction clock signal can be stably bit-synchronized.

Embodiments Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a bit synchronization circuit according to the present invention, FIG. 2 is an operation explanatory diagram of the bit synchronization circuit of FIG. 1, and FIG. 3 is a bit synchronization circuit of FIG. 3 is a timing chart showing the main signals of FIG.

In FIG. 1, 1 is an input terminal for an NRZ signal transmitted as shown in FIG. 3 (b) in synchronization with a transmission clock CC as shown in FIG. 3 (a), and 2 is this NRZ signal. The edge differentiating circuit 3, which generates pulses at the rising edge and the falling edge of the NRZ signal by differentiating the NRZ signal, is composed of a plurality of stages of flip-flops and the like.
Is an up-down counter that outputs an up-carry 5 or a down-carry 6 in response to a pulse from the D flip-flop 7 and an up command or a down command from the D flip-flop 7, which will be described later. The number L of stages of the up-down counter 3 is set from the input terminal 4. It

The up / down counter 3 outputs the up carry 5 when the output of the L + 1th stage flip-flop is "1", and outputs the down carry 6 when all the flip-flop outputs are "0". Is configured.

9 is the correction value Δn ₀ , Δn _{1 of the} frequency division number input from the terminal 8.
A frequency division number switching circuit for switching the frequency division number n of the variable frequency division circuit 10 described later by (Δn ₀ <Δn ₁ ) and the up carry 5 or the down carry 6 from the up / down counter 3.

From the terminal 8, as shown in FIG. 2, in the high stability mode after the rise of the circuit, the correction value ± of the frequency division number n is relatively small.
Δn ₀ is input, and a correction value ± Δn ₁ having a relatively large frequency division number n is input in the high-speed mode when the circuit rises.

12 is an input terminal for the reference clock signal (frequency f ₀ ), 7
Is a frequency divider circuit described later in synchronization with this reference clock signal.
A D flip-flop (D-FF) 10 that latches the signal from 11 and compares the phases of both signals is a variable divider that divides the reference clock signal by the division number set by the division number switching circuit. The frequency dividing circuit 11 divides the signal frequency-divided by the variable frequency dividing circuit 10 by a fixed frequency dividing number m, and FIG.
It is a frequency dividing circuit for outputting a reproduced clock signal (frequency f _T ) as shown in (d) to the output terminal 13 and the D terminal of the D flip-flop 7. The waveform of FIG. 3 (d) is an enlarged view of the waveform of FIG. 3 (c).

 Next, the operation of the embodiment having the above configuration will be described.

The variable frequency dividing circuit 10 divides the reference clock signal from the terminal 12 into 1 / n when there is no correction command from the frequency dividing number switching circuit 9, and the frequency dividing circuit 11 changes this signal into 1 / m. The divided clock signal is output. In this case, when the transmission rate of the NRZ signal and f _T, the frequency of the reproducing clock signal is f _T.

Here, the frequency dividing number m of the frequency dividing circuit 11 is set in advance to an even number so that the pulse occupancy rate of the reproduced clock becomes 50%.
Further, the frequency dividing number n of the variable frequency dividing circuit 10 is set to n = f ₀ / mf _T , and the up / down counter 33 has its initial value 2 ^L according to the number of stages L set via the terminal 34. Is set.

The D flip-flop 7 compares the phase of the reference clock signal with the phase of the reproduced clock signal from the frequency dividing circuit 10. For example, when the phase of the reference clock signal is behind that of the transmission clock, the up-down counter 3 is operated. The up count mode is set, and therefore the up / down counter 3 outputs the up carry 5.

The frequency division switching circuit 9 receives a relatively large correction value ± Δn _{1 in the} high speed mode from the terminal 8, and the up / down counter 3
When Up carry 5 is input from, Up carry 5
The frequency division number n of the variable frequency dividing circuit 10 is increased to a relatively large correction value n + Δn ₁ every time the input signal is input to match the phase of the reference clock signal with the phase of the reproduction clock signal.

Further, the D flip-flop 7 sets the up-down counter 3 in the down-count mode when the phase of the reference clock signal leads that of the transmission clock,
Therefore, the up / down counter 3 outputs the down carry 6.

The frequency division switching circuit 9 receives a relatively large correction value ± Δn _{1 in the} high speed mode from the terminal 8, and the up / down counter 3
When down carry 6 is input from, down carry 6
The frequency division number n of the variable frequency dividing circuit 10 is reduced to a relatively large correction value n-Δn ₁ each time the input is input, and the phase of the reference clock signal and the large correction width are increased as shown in FIG. 3 (d). Match the phases of the recovered clock signals at high speed.

Here, the operation of FIG. 1 will be described in detail. FIG. 4 is a timing chart of the bit synchronization circuit of FIG. 1 of the present embodiment.

For convenience of explanation of FIG. 4, the number of stages L of the up-down counter (3) of FIG. 1, the standard division number n of the variable frequency dividing circuit (10) n = 18, and the frequency division of the frequency dividing circuit (40). Number m = 1, frequency division switching circuit (9), frequency division difference in high-speed mode Δn ¹ = ±
2. The frequency difference Δn ⁰ = ± 1 in the high stability mode.

First, in FIG. 1, a reference clock (12) and received data (1) are input.

The edge differentiating circuit (2) receives "01,
Every time the change point of 10 ”is detected, a signal is output and is output to the up / down counter (3). Since the recovered clock signal (13) is "1" at point A in Fig. 4, DFF
(7) Give a countdown instruction.

In the up / down counter (3), when the signal from the edge differentiating circuit (2) arrives, the down signal (6) is immediately sent to the frequency dividing number switching circuit (9) because the counter (3) has one stage. Output.

Here, since the correction value signal (8) is in the high speed mode, the frequency dividing number switching circuit (9) switches to the frequency dividing number difference Δn ¹ = ± 2, and the down signal of “2” is variable frequency divided. Output to circuit (10).

The variable frequency divider circuit (10) receives the down signal of "2",
Dividing number n is “16” based on the calculation of “n-Δn ¹ = 18-2”
Change to The situation is shown in Fig. 4, sections (i) and (ro).
Is shown in.

In the next sections (ha) and (ni), the recovered clock (13) and the received data (1) have already been synchronized in the previous sections (i) and (ro), so the correction value signal ( 8) becomes high stability mode, and frequency division switching circuit (9)
Switches to the frequency division number difference Δn ⁰ = ± 1 and outputs an up signal of “1” to the variable frequency dividing circuit (10).

The variable frequency dividing circuit (10) receives an up signal of "1",
Dividing number n is “19” based on the calculation of “n + Δn ⁰ = 18 + 1”
Change to The situation is shown in Fig. 4 (ha), (ni)
Is shown in.

In the sections (ho) and (to), since the received data (1) remains unchanged at "11", the edge differential signal (2) is not output and the up / down counter (3) outputs both up and down signals. Do not output.

In the sections (and) and (c), when the signal of the edge differentiating circuit (2) comes, the down clock (6) is sent to the frequency dividing number switching circuit (9) because the reproduction clock (13) is "1". Output. Then, the variable frequency dividing circuit (10) changes the frequency dividing number n to "17" based on the calculation of "n-Δn ⁰ = 18-1".

Then, in the sections (ri) and (n), when the signal of the edge differentiating circuit (2) arrives, the reproduction clock (1)
Is 0, the up signal (5) is output to the frequency dividing number switching circuit (9). Then, the variable frequency dividing circuit (10) changes the frequency dividing number n to "19" based on the calculation of "n + Δn ⁰ = 18 + 1".

In this way, the rising edge of the reproduction clock (13) is divided by the correction value signal (8) by the correction value signal (8) in the high-speed mode of the sections (I) and (B) so that the division number difference Δn ¹ =
By switching to ± 2, the up or down signal of “2” is output to the variable frequency dividing circuit (10).

After that, after the section (ha), it becomes high stability mode,
The correction value signal (8) is used to switch to the frequency division number difference Δn ⁰ = ± 1 of the frequency division number switching circuit (9), and an up or down signal of “1” is output to the variable frequency division circuit (10). As the correction value signal, for example, a unique word detection signal inserted in the received bit string is used.

Further, if the switching is performed in common with the stage number switching signal (34) of the up / down counter, it is possible to create a more stable mode.

As described above, in the bit synchronization circuit of the present invention, the frequency division switching circuit (9) changes the frequency division number of the variable frequency division circuit (10) drastically in the high-speed mode and in the high-stable mode to a small range. Is configured to be synchronized with the rising edge of the reception data (1) at an early stage.

In the embodiment, as shown in FIG. 4, even if the phase values of the transmission clock and the reception reproduction clock from the point A at the start to the section (i) are 2/18 bits, the 1-bit section (i.e. ) ~ (Ro) will be synchronized only.

Thus, at the rising edge of the NRZ signal, the bit synchronization establishment signal, the frame synchronization establishment signal, etc. are input to the terminal 4 to set the number of stages L of the up / down counter 3 to a small number, and the carry 5, 6 output by the up / down counter 3 is output. By increasing the frequency, the jitter of the reproduced clock increases, but the bit synchronization can be pulled in earlier.

On the other hand, when the circuit starts up and a relatively small correction value ± Δn _{0 in the} high stability mode is input from the terminal 8 and the up carry 5 or the down carry 6 is input from the up / down counter 3, the frequency division switching circuit 9 Is the frequency division number n of the variable frequency division circuit 10 each time carry 5 or 6 is input.
Is increased or decreased to a relatively small correction value n + Δn ₀ or n−Δn ₀ , and the phase of the reference clock signal and the phase of the reproduction clock signal are stably matched with a small correction width as shown in FIG. 3D.

In this case, the number of stages L of the up / down counter 33 is set to be large, and the carry 5 output by the up / down counter 3,
By reducing the frequency of 6, the jitter of the reproduced clock signal can be reduced.

Therefore, according to the above-described embodiment, at the time of rising, the frequency of correction of the variable frequency dividing circuit 10 is increased by setting the number L of stages of the up / down counter 3 to be small, and the frequency dividing number switching circuit 9 changes the frequency of the frequency dividing number n. By setting a relatively large correction value ± Δn ₁ , it is possible to speed up the rise of the circuit. On the other hand, after the rise, the number of stages L of the up / down counter 3 is set to be large so that the correction of the variable frequency dividing circuit 10 can be performed. By reducing the frequency and setting the correction value ± Δn ₀ of the frequency division number n by the frequency division number switching circuit 9, it is possible to reduce the jitter of the reproduced clock signal, and to stabilize the bit synchronization. Can be realized.

In the above embodiment, the case where the correction value of the frequency division number is set to two has been described, but more precise bit synchronization can be realized by increasing the number of the correction values.

As described above, according to the present invention, the frequency division number of the variable frequency dividing circuit is controlled at the time of rising so as to be changed with a relatively large frequency division difference and at a relatively high frequency, and after the rising, the frequency dividing number is different from that at the rising time. The reproduction clock jitter can be reduced, and the reference clock signal and the reproduction clock signal can be stably bit-synchronized with each other because the control is performed so as to change with a relatively small frequency difference and with a relatively small frequency. be able to. Therefore, it is strong against fading of radio waves, and even if an erroneous correction signal is generated due to noise after the synchronization pull-in, the correction frequency is low, and it is possible to maintain synchronization for a certain period of time.
It is possible to obtain a stable state.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a bit synchronization circuit according to the present invention, FIG. 2 is an operation explanatory diagram of the bit synchronization circuit of FIG. 1, and FIG. 3 is a bit synchronization circuit of FIG. 4 is a detailed timing diagram of the bit synchronizing circuit of the present embodiment, FIG. 5 is a block diagram showing a conventional bit synchronizing circuit, and FIG. 6 is a conventional bit synchronizing circuit. FIG. 6 is a detailed timing diagram of the circuit. 2 ... Edge differentiation circuit, 3 ... Up-down counter,
9: Dividing frequency switching circuit, 10: Variable dividing circuit, 11: Dividing circuit

Claims (1)

(57) [Claims] 1. An up-carry signal or a down-carry signal when a change point of "0" or "1" of a received data signal is input as a clock and a predetermined number of counter stages are counted based on an up / down command signal. An up / down counter to output, a frequency division number switching circuit that outputs a correction value of the frequency division number specified in the correction value designation terminal corresponding to each input of the output signal of this up / down counter, and this frequency division number switching A variable frequency divider circuit that divides the reference clock signal based on the frequency division number that is increased or decreased by the correction value specified by the output signal of the circuit and outputs it as the reception clock of the reception data signal, and the variable frequency division circuit A flip-flop that compares the phases of the output signal and the reference clock and outputs the up / down command signal depending on whether they match or not, and a high-speed mode And a control means for outputting a large correction value to the correction value designating terminal in the case of and a small correction value to the correction value designating terminal in the high stability mode.