JP2553728B2 - Arithmetic unit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a plurality of arithmetic units in a processor, identifies the data dependency of a plurality of instructions, and simultaneously or sequentially operates the plurality of arithmetic units. The present invention relates to an arithmetic unit for executing the above.

Conventional technology Conventionally, VLIW has been used as an arithmetic unit with multiple arithmetic units.
(Very Long Instruction Word Very L
ong Instruction Word) An architecture called a computer is known.

FIG. 4 is a block diagram of the same architecture of the related art, and the register file 401 writes data read ports rs1d and rs2a for supplying data to the first arithmetic unit 402 and the arithmetic result of the first arithmetic unit 402. It has a port rda for. The register file 401 also has data read ports rs1b and rs2b for supplying data to the second arithmetic unit 403 and a port rdb for writing the operation result of the second arithmetic unit 403. Instruction register 404
Has a bit length capable of storing two instructions in order to operate the two arithmetic units 402 and 403 at the same time.
The data is stored in this instruction register 404 via. The two instructions in the instruction register 404 are control signals 406 and 407.
The command is sent to the first computing unit 402 and the second computing unit 403 via each of them.

If such an architecture is adopted, it is possible to execute up to two instructions in parallel inside the processor, and it is possible to achieve speeding up of instructions that are not vectorized.

FIG. 5 is a diagram showing an example of the contents of an instruction storage memory for a conventional processor.
This is a memory in which two instructions of a column and a second column are stored. The processor sequentially fetches the instruction word designated by the instruction pointer, stores it in the instruction register 404, and executes the instruction stored in the instruction register 404. Instruction R0 = R1 + R2
For example, the instruction execution is as follows. The contents of the registers R1 and R2 read from the register file 401 are sent to the first arithmetic unit 401, and R1 and R2 are added. Then, R0 of this operation result is input and stored in the register file 401.

FIG. 5 also shows a state in which instructions that cannot be simultaneously executed are stored. That is, the instruction R3 = R0-R3 in the first entry in the first column and the fourth entry is
It cannot be executed until after the instruction R0 = R1-R2 of the entry is executed. At the same time, the instruction R5 = R3 in the 1st column, 5th entry
-R2 can be executed only after execution of the fourth entry instruction R3 = R0-R3 in the same column. The reason why the simultaneous execution is not possible is that the operation result of the instruction is used in the next instruction, and unless the operation result is stored in the register file 401, the reading of the register file 401 by the next instruction cannot be executed.

Therefore, as shown in FIG. 5, the nop instruction is stored in the instruction storing memory, and the memory is wasted.

FIG. 6 is a timing chart when the processor of FIG. 4 executes the instructions shown in FIG.
12 ... 16 correspond to the instructions stored in the first to fifth entries in the first column of FIG. 5, and 11, 13 ... 17 are stored in the first to fifth entries of the second column. Corresponds to an instruction. Here, “I” indicates the time until the instruction is read from the instruction storage memory and stored in the instruction register 404,
“E” indicates the time from reading data from the register in the register file 401, performing the operation, and storing the operation result in the register file 401.

As can be understood from this timing chart, when the first and second arithmetic units 402 and 403 are provided, the parallel operation can be expressed by increasing the one word length of the instruction.
A major feature of the VLIW calculator is that it can achieve higher performance than executing instructions one by one.

Problems to be Solved by the Invention By the way, in the conventional VLIW calculator described above, no
Since there are p instructions, it is not possible to fill the instruction storage memory with instructions at the highest density, which also includes the following problems. That is, there is no connectivity between the processor for two arithmetic units and the processor for one, and the compiled code of the program that operates on the processor of the arithmetic unit 1 will not operate normally on the processor of the two arithmetic units, and A recompile operation is required. Further, since the number of stages of the pipeline is two, that is, the instruction stitch and the execution, there is a problem that the ratio of the execution time of the nop instruction to the execution time of the whole instruction is large.

The present invention has been made in view of the above-described conventional problems, and an object thereof is a processor having a plurality of arithmetic units, which can operate even in a compiled code for one arithmetic unit. , A recompilation operation is unnecessary, a code can be compressed, and an operation device capable of accelerating operation operation is provided.

In order to achieve the above object, the arithmetic unit of the present invention has a plurality of data read ports and a plurality of write ports for storing a plurality of operation results, and these ports operate independently at the same time. A register file having a possible function, an input latch for storing read data from each port of the register file, and an operation determined by a control signal using the data stored in two of these input latches as inputs, In a configuration in which a plurality of arithmetic units having a function of performing between these two data, an output latch for storing the output of each arithmetic unit, and a configuration in which the output latch is connected to the write port of the register file, the input data to the arithmetic unit Is specified by the register number, the storage location of the operation result is specified by the register number, and the operation type is specified by the control code. It has an instruction register that can hold multiple instruction codes to specify, fetch stage that fetches the instruction stored in memory to the instruction register, decodes the content of the instruction register, and writes it to the input latch of the arithmetic unit. In the 4-stage pipeline execution of the decode stage for reading out, the execution stage for computing these data by the arithmetic unit and storing the output data in the output latch, and the write stage for storing the contents of the output latch in the register The two instructions to be stored and executed subsequently store the register number designated as the storage location by the multiple instruction code executed at the same time and the operation input data designated by the multiple instruction code executed at the same time. Has a first determination mechanism that detects that the register number is Based on the detection result, a selector is provided which enables the input to the arithmetic unit to use the data stored in the output latch of the arithmetic unit, and further when a plurality of instruction codes in the instruction register are simultaneously executed, It has a second determination mechanism for detecting the existence of data dependency between these instruction codes, whereby the data dependency is detected in the instruction decode stored in the instruction register at the decode stage of the pipeline. In this case, the instruction code to be executed first causes each stage to be executed sequentially, and the instruction code with the subsequent dependency has the operation stage as no operation and moves to the execution phase at the next timing. Repeatedly applied to the dependent instruction code, and the instruction code executed next to this instruction is executed last with the instruction code of the above instruction. When the instruction code becomes execution stage, it is intended to shift the decode phase.

Operation With such an arithmetic unit, it is possible to guarantee the same performance as when one instruction is pipelined when multiple instructions cannot be executed simultaneously.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

Although the present embodiment describes the case where two instructions are simultaneously executed, this can be realized by expanding the following idea even when simultaneously executing three or more instructions.

FIG. 1 is a block diagram of an arithmetic unit according to the present invention when two arithmetic units are used. Register file 101
Is the data read port for rs1a, rs2a, rs1b, rs
It has 4 independent ports of 2b, and the write port is rd
It has two independent ports, a and rdb. Input latch 10
Read data from the register file 101 is stored in 2, 103, 108, and 109. First and second arithmetic units 106, 112
The calculation result of is stored in the output latches 107 and 113, respectively. The output of the output latch 107 is the selectors 104 and 105 for selecting the inputs of the first and second arithmetic units 106 and 112, respectively.
It is connected to 110 and 111 as well as to the port rda of the register file 101. Similarly, the output of the output latch 113 is also connected to the selectors 104, 105, 110 and 111, and is also connected to the port rdb of the register file 101.

The instruction bus 116 has a bit width that allows the first and second arithmetic units 106 and 112 to operate simultaneously, and the result read from the instruction storage memory is stored in the instruction register 114. The two stored in the instruction register 114
The two instructions are transmitted through the decode signal 118 to the first arithmetic unit 106.
And a command for the second computing unit 112 through the decode signal 117. The data dependence determination circuit 115 has a function of determining whether or not the instructions stored in the instruction register 114 can be simultaneously executed, and if the instructions cannot be simultaneously executed, the instructions are sequentially executed.

FIG. 2 shows an example of the contents of the instruction storage memory, and FIG. 3 shows a timing chart when this instruction is executed. In the timing chart, "I" is the instruction storage time from the instruction storage memory to the instruction register 114, "D" is the data read from the register file 101 and the input latches 102 of the first and second arithmetic units 106 and 112, Data transfer time to transfer to 103, 108, 109, "E" is the first and second arithmetic units 10
It is assumed that the data for 6 and 112 are input and the calculation result is stored in the output latches 107 and 113, and “W” is the time until the contents of the output latches 107 and 113 are stored in the register file 101.

Instruction I0 (R0 = R1 + R read from the instruction storage memory
2) and I1 (R3 = R1-R2) execution proceeds as follows. First, the instructions of I0 and I1 are stored in the instruction register 114 at time t1. Next, the contents of the registers R1 and R2 in the register file 101 which is the operation source indicated by the instruction I0 are read out and held in the input latches 102 and 103 of the first operation unit 106. Similarly, the contents of R1 and R2, which are the operation sources of instruction I1, are
Are held in the input latches 108 and 109 of the arithmetic unit 112. This work corresponds to the D phase and ends at time t2, but in the E phase, addition and subtraction are simultaneously performed by the two first and second arithmetic units 106 and 112, and the arithmetic result is output at time t3. It is stored in 107 and 113. In the W phase, the contents of these output latches 107 and 113 are stored in R0 and R of the register file 101.
Written to 3 at the same time. This work ends at time t4.
Two instructions can be executed simultaneously because the destination register of I0 is different from the source register of I1.

Similarly, in the case of executing I2 (R4 = R1 + R2) and I3 (R5 = R3 + R2), these two instructions can be executed simultaneously.
However, in the E phase of I3, the contents of the register R3 updated by the instruction of I1 are used as the source data, so the execution of the E phase of I3 proceeds at the same time as the execution of the W phase of I1. Therefore, immediately before the execution of the E3 phase of I3, the contents of the register R3 have not been updated,
In the D phase of I3, the data dependence determination circuit 115 in the figure operates, and the second arithmetic unit holds the data to be written in R3.
The input data used in the subsequent E phase may be obtained from the output latch 113 of 112. That is, in this way, not only the instructions I2 and I3 can be executed at the same time, but also the instructions can be executed without disturbing the instruction execution pipeline between the immediately preceding instructions I0 and I1.

The function of this data dependence determination circuit is to copy the contents of the instruction register into this circuit, and match the source register number in the two instructions in this with the destination register number in the instruction of the new instruction register. Can be realized by detecting.

Next instruction is I4 (R0 = R1-R2), I5 (R3 = R0-R3)
Concerning execution of, since the result of I4 is used by I5, it cannot be executed simultaneously. This can be detected and judged in the D phase by using the data dependence judgment circuit 115. More specifically, this process is performed by delaying the E5 phase of I5 by one stage (that is, between time t5 and time t6). Achieving this one-stage delay depends on the output latch of FIG.
It is realized by not storing the calculation result data in 113,
In FIG. 3, this operation is described as nop. Then t5-t6
At the time of, I4 nopization is performed. This means that the register file is not stored. When such a data dependency occurs, t4−
Setting t5, t5-t6 as the E phase means that the E phase is 2
It can be realized with a circuit for continuing.

After time t5, the normal phase execution starts. As a result, the subsequent instructions I6, I7, I8 and I9 are affected. This is because the execution of one cycle was delayed in the pipeline. In Figure 3, the time when the dependency was discovered is
At the time of executing the D phase of I4 and I5, t4 of I6 and I7
The operation performed at time t5 is the nop operation. At this point, I6 and I7 are stored in the instruction register, and this is realized by prohibiting data storage in the input latch of the arithmetic unit as the D phase execution result.

In this example, since I6 (R5 = R3-R2) and I7 (R6 = R1-R) can be executed simultaneously, no pipeline delay has occurred. Further, regarding the instructions I8 and I9, the start of the I phase is suppressed. This is realized by stating the start of memory fetch at the next timing. In this way, the drooping of the pipeline is made normal.

By such processing, even if the instruction stored in the subsequent instruction register and the multiple instructions stored in the instruction register have a data dependency relationship, even if they cannot be executed at the same time, they are executed while observing the data dependency relationship. It In this case, the instruction having the data dependency has the same execution time as that of the case where the instruction is sequentially executed, and no useless cycle occurs.

Effects of the Invention As described above, according to the present invention, the arithmetic unit 1
Even an object compiled for one purpose can be operated by a processor having a plurality of arithmetic units, and a recompilation operation is unnecessary. Further, according to the present invention, it is not necessary to insert an instruction for converting the instruction field of a non-parallel-executable arithmetic unit into a nop in the compiled code, so that the code can be compressed. Further, in the present invention, since a plurality of arithmetic units operate simultaneously, the operation speed becomes higher than that of a processor of one arithmetic unit.

[Brief description of drawings]

FIG. 1 is a block connection diagram of an arithmetic unit according to the present invention, and FIG.
FIG. 3 is a conceptual diagram showing an example of contents of an instruction storage memory, FIG. 3 is a timing chart of an instruction execution pipeline, FIG. 4 is a block connection diagram of a conventional arithmetic unit, and FIG. 5 is an example of contents of an instruction storage memory. The conceptual diagram shown in FIG. 6 is a timing chart of instruction execution. 101 ... Register file, 102, 103, 108, 109 ... Input latch, 106 ... First arithmetic unit, 112 ... Second arithmetic unit, 107, 113 ... Output latch, 114 ... Instruction register, 1
15 …… Data dependence discrimination circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Sakushima 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor, Miwa Fukino 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Incorporated (56) References Japanese Patent Laid-Open No. 62-55736 (JP, A)

Claims (1)

(57) [Claims] 1. A read port for a plurality of data, and a write port for storing a plurality of operation results,
A register file having the function of enabling these ports to operate independently at the same time, an input latch for storing read data from the individual ports of the register file, and input of data stored in two of these input latches A configuration in which a plurality of arithmetic units having a function of performing an operation determined by a control signal between these two data, an output latch storing the output of each arithmetic unit, and an output latch connected to the write port of the register file In, the input data to the arithmetic unit is specified by the register number, the storage location of the operation result is specified by the register number, and the operation register that can hold a plurality of instruction codes that specify the operation type by the control code is provided. Fetch stage that fetches the instruction stored in Cord, decode stage for reading the contents of the specified register to the input latch calculator calculates these data the arithmetic unit, execution stage for storing the output data in the output latch
Furthermore, in the execution of a write stage that stores the contents of the output latch in a register in a 4-stage pipeline, two instructions that are continuously stored and executed in the instruction register are:
Make sure that the register number specified as the storage location by the multiple instruction code that is executed at the same time is the same as the register number that stores the operation input data specified by the multiple instruction code that is executed at the same time. A first determination mechanism for detecting, and based on the detection result, a selector that enables the input to the arithmetic unit to use the data stored in the output latch of the arithmetic unit, Of the instruction code stored in the instruction register, the second determination mechanism detects that there is a data dependency between these instruction codes when the plurality of instruction codes of the instruction code are simultaneously executed. If a dependency is detected at the decode stage of the pipeline, the first instruction code to be executed causes each stage to be executed sequentially, The instruction code to be executed does not operate the execution stage, and the operation to shift to the execution phase at the next timing is repeatedly applied to the instruction code having the sequential data dependency. An arithmetic unit that enables simultaneous execution of instructions by shifting to the decode phase when the last executed instruction code of the instruction reaches the execution stage.