JP2553695B2 - Speed control device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed control device that controls a rotation speed of a rotating body to a desired value.

2. Description of the Related Art Conventionally, as a method of controlling the rotation speed of a rotating body to a desired value, an alternating voltage induced in a stator winding of a rotating body is waveformd into a rectangular wave without connecting a speed generator to the rotating body. Method using shaped signal (FG signal) (For example, "Brushless DC motor drive method without position detection element" National Technical Report P614 Vol.33 No.5 OCT.1
987), the speed is controlled by using only the frequency of the FG signal or the repetition cycle as speed information, and the speed of the rotating body can be controlled relatively stably with a simple structure.
(For example, it is disclosed in Japanese Examined Patent Publication No. S57-18434.) By the way, this frequency or period detection method sufficiently amplifies the alternating voltage induced in the stator winding to a rectangular wave signal, An error output signal is generated assuming that a predetermined edge of the wave signal has velocity information.

For example, in a typical cycle detection method, the clock pulse is counted in the period from the leading edge (leading edge) of the rectangular wave signal of the amplified alternating voltage to the next leading edge, thereby depending on the rotation speed of the rotating body. By obtaining the counted value and generating a pulse width modulation signal (used when searching for a chopper type driving method) based on this counted value, or by converting the counted value into an analog voltage. You are getting the error output.

Therefore, in order to realize more precise control, it is necessary to make the alternating voltage induced in the stator winding the same at a constant rotation speed and make the period of the rectangular wave signal more accurate.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above-described configuration, for example, a rotor having 12 poles (6 pole pairs) and a stator having 9 coils is rotated using a three-phase half-wave drive method. At this time, the period of the rectangular wave signal obtained by amplifying the alternating voltage induced in the stator winding is every 1 period due to variations in the rotor magnetizing accuracy, rotor / stator mounting accuracy, etc. Since a cycle longer than the normal cycle and a cycle shorter than the regular cycle appear alternately, it appears as a disturbance having a frequency half the frequency of the rectangular wave signal in the control system, and there is a problem that the control characteristic deteriorates. Especially, in a control system such as a cylinder motor of a video tape recorder (VTR) that requires a highly accurate rotating body, the frequency of disturbance is a problem regardless of the inertial region of the control system. In addition, since preparation is rarely performed during mass production, it was difficult to accurately control the cycle of the FG signal for all units.

In view of the above problems, the present invention determines whether the period of the rectangular wave signal is constant even if the period of the rectangular wave signal obtained from the alternating voltage induced in the stator winding is different at the time of constant speed rotation. Thus, it is intended to realize a speed control device that corrects the deviation of the period of the rectangular signal and performs highly accurate control.

Means for Solving the Problems In order to solve the above problems, the speed control device of the present invention is
Cycle detecting means for detecting a cycle of an alternating current signal having speed information of a rotating body, memory means for storing a detected value of the cycle detecting means, an arithmetic unit for calculating an error output from the detected value and a reference value, Driving means for supplying driving power to the rotating body based on the error output, and first and second deviations from the continuous first and second cycle detection values and the reference value stored in the memory means. Correction amount calculating means for calculating the correction amount of the reference value from the calculation result when the subtraction value of the first and second deviation amounts is substantially constant, and The present invention is characterized by comprising a reference value correcting means for correcting the reference value of the cycle, and a gain switching means for making the gain of the control system smaller during the operation of the correction value calculating means than during the normal operation. Further, it is characterized by further comprising monitor means for monitoring that the error output calculated by the arithmetic unit is substantially constant based on the reference value corrected by the reference value correction means and the detection value of the cycle detection means. Is.

Action The present invention has the above-described structure so that even if the period of the rectangular wave signal obtained from the alternating voltage induced in the stator winding is different at the time of constant speed rotation, the period of the rectangular wave signal is constant. Since the deviation of the period of the rectangular wave signal is corrected by the arithmetic unit, even if the period of the rectangular wave signal obtained from the induced alternating voltage is deviated, it does not appear as a disturbance in the control system and is highly accurate. Various controls can be performed.

Embodiment Hereinafter, a speed control device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, which is realized by using a processor here. An alternating voltage signal induced in a stator winding (not shown) of the rotating body 1 is input to the waveform shaper 2. The output signal of the waveform shaper 2 is a channel selector 3a, a calculator 3b, and a memory.
It is supplied to the channel selector 3a of the processor 3 including the 3c, the period detector 3d and the data buses 4, 5 and 6. The channel selector 3a generates an address update signal for the memory 3c of the processor 3, and the address update signal is supplied to the memory 3c of the processor 3 via the control bus 4.

The output signal of the waveform shaper 2 is supplied to the period detector 3d. The cycle detector 3d measures the cycle of the output signal of the waveform shaper 2 and supplies it to the memory 3c of the processor 3 via the data bus 6. The memory 3c stores the cycle detection value at an address based on the address update signal of the channel selector 3a.

Here, a configuration example of the period detector 3d will be described.
The cycle detector 3d is composed of a count circuit for counting the reference clock signal and a latch circuit. When the rising edge of the output signal of the waveform shaper 2 is input to the cycle detector 3d, the count value of the counter is latched in the latch circuit. , Then the counter is immediately reset. That is, the count value obtained by counting the period from the rising edge of the waveform shaper 2 to the next rising edge with the reference clock signal is stored in the latch circuit. This is the period of the output signal of the waveform shaper 2 using the reference clock signal,
That is, it is measured digitally.

Next, in the processor 3, the arithmetic unit 3b causes the rotating body 1 to move from the period detector 3d via the data bus 6 to the period detection value stored in the memory 3c of the processor 3 and the preset speed reference value. Calculate the speed error output of
The calculation result is supplied to a digital-analog converter (denoted as DA converter in the drawing) via the data bus 5. The output of the digital-analog converter 7 is amplified by a power amplifier (denoted as a power amplifier in the figure) 8 and supplied to the rotating body 1 as driving power.

FIG. 2 is a signal waveform diagram for explaining the operation of the period correction, and is a signal waveform diagram when the rotating body 1 is rotating at a constant speed. 2a shows the signal waveform (FG signal) of the alternating voltage induced in the stator winding, FIG. 2b shows the output signal waveform of the waveform shaper 2, and FIG. 2c shows the waveform shaper. It is a rising signal waveform created from the output signal of No. 2, and its period is measured and used as speed information. FIG. 2d shows the speed error signal waveform calculated by the computing unit 3b. Even though the rotation speed of the rotating body 1 is constant, the speed error signal is not a constant value but is input every time the FG signal is input. It is larger or smaller than 0 '. This is because the cycle of the FG signal is not always constant but changes every cycle, and becomes larger or smaller than the normal value. For example, when the rotating body 1 is rotating at the set speed,
The period after waveform shaping of the FG signal is P1, P2, and the ratio of P1: P2 is 9
If it is 8: 102, the detected value of the cycle P1 of the cycle detector 3d is the time interval from time t1 to time t2 in FIG. 2, which is 2% shorter than the normal value. Also a period detector
The detected value of the period P2 of 3d is the time interval from the time t2 to the time t3, and the value of the period is 2% longer than the normal value.

Furthermore, the same applies to the next cycle from time t3 to time t5, the time interval from time t3 to time t4 is 2% shorter than the normal value, and the time interval from time t4 to time t5 is the normal value. 2% longer than that. Therefore, the period of the continuous FG signal alternates between a shorter period and a longer period than the value of the regular period.

That is, by using a signal in which a section in which the cycle value of the FG signal is shorter and a section in which it is longer than the normal value appears, the calculator 3b of the processor 3
Calculates the speed error output, it becomes the speed error output when the speed increases by 2% because the cycle is 2% shorter in the section where the time interval from time t1 to time t2 is measured. Since the period is 2% longer in the section up to t3, the speed error is output when the speed is 2% slower. Therefore, the error output increases or decreases even though the rotating body 1 rotates at the set speed, which is not preferable for the control system.

However, in the embodiment of the present invention shown in FIG. 1, when the rotating body 1 is rotating at a constant speed, even if the cycle ratio of the FG signal is not exactly 100: 100, there is a deviation in cycle. By correcting, it is possible to secure a sufficient cycle ratio,
It is configured so that highly accurate control can be realized, which will be described below.

The section of the first FG signal of continuous FG signals is section A, the section of second
If the section of the FG signal is B section, the rotating body 1 is controlled in one cycle of the FG signal, and the control is performed in a state where the cycle of the FG signal is alternately shifted. At this time, 1 / of the FG signal
The control characteristic of the rotating body 1 at the frequency of 2 is in the inertia region, and the control region is about 1/12 of the frequency of the FG signal. Therefore, the disturbance suppression characteristic at the frequency of 1/2 of the FG signal is higher than that of the control region. It is about 1/6. Nevertheless, F
Due to the deviation of the cycle of the G signal, the error signal is larger than the value obtained by the original response of the rotating body 1. Normally, the response of the rotating body 1 at the frequency of 1/2 of the FG signal is hardly affected by the disturbance, and as a result, the value of the error output becomes almost constant.

However, since the period of the FG signal is measured with high accuracy while operating the control system, the control system affects the measurement system. Therefore, in order to measure the period of the FG signal with higher accuracy, it is necessary to lower the gain of the control system so that the influence of the control system does not easily appear in the measurement system. Therefore, when the cycle of the FG signal is measured with high accuracy, the gain of the control system is lowered by the gain switching means, and the correction value is obtained by the correction value calculating means. After the correction value is obtained by the correction value calculation means, the gain is returned to the original value by the gain switching means so that normal control characteristics can be obtained.

The gain switching means can be realized by software of the processor 3, for example, by multiplying the obtained speed error by a gain constant. If the gain constant is smaller than '1', the gain will be small, and if it is larger than '1', the gain can be large.

The deviation of the cycle of the FG signal is detected by using the characteristic that the value of the error output of the rotating body 1 at half the frequency of the FG signal is almost constant. That is, when the cycle of continuous FG signals alternately increases or decreases, it is determined that the cause is not the response of the rotating body 1 but the deviation of the cycle due to the FG signal, and the correction is performed.

When the rotation speed of the rotator 1 is constant and there is no deviation in the cycle ratio of the FG signal, the values of the cycles of the A section and the B section are the same. However, since the ratio of the cycle of the FG signal is deviated from 100: 100 when the FG signal is created, the values of the cycles of the A section and the B section are not the same, but deviated by a value according to the deviation of the cycle. When the period shift amount in the A section is −ΔA, the period shift amount in the B section is ΔA. That is, the shift amount of the period of the FG signal can be obtained from the difference between the shift amounts of the A section and the B section, and is represented by the equation (1).

Here, A and B are the values of the periods of the A section and B section, respectively, and D is the speed reference value. At this time, the gain of the control system is set smaller than that in the normal state by the gain switching means. Further, the selection of the address of the memory 3c according to the A section and the B section is performed based on the address update signal of the channel selector 3a.

Therefore, the deviation of the FG signal cycle ΔA
Then, the deviation of the cycle of the FG signal can be corrected by calculating + ΔA for the speed reference value in the A section and calculating -ΔA for the speed reference value in the B section.

FIG. 2e shows a correction value of the speed reference value obtained by the above method, which has a negative value in the A section and a positive value in the B section.

Here, the operation of the channel selector 3a will be described with reference to FIG.

In the branch 301 of FIG. 3, it is determined whether the FG signal of the rotating body 1 is input to the processor 3,
If the FG signal is not input, the branch 301 is executed again, and the arrival of the FG signal is waited for. If the FG signal is input, the process moves to the processing block 302, and the processing block 302 increments the channel counter C. Then, the process proceeds to branch 303, and it is determined whether the channel counter C is an even number or an odd number. If the channel counter C is an even number, the process moves to the processing block 304, and the address of the memory 3c is set to the address of section A. If the channel counter C is an odd number in the branch 303, the process moves to the processing block 305, and the address of the memory 3c is set to the address of section B. As described above, the address of the memory 3c corresponding to the section A and the section B is determined by the channel selector 3a.

Next, by the processor 3 based on the calculation formula (1)
FIG. 4 shows a flowchart for correcting the FG signal period deviation.

Here, in order to improve the detection accuracy of the period detection of the A section and the B section (because one measurement is weak against noise etc.), it is assumed that several measurements are averaged, and if the cycles are significantly different, Exclude from average data. If the number of times of averaging is n, the average values of the deviation amounts in the A section and B section are respectively It is represented by. Here, Ai is the detection period of section A, and Bi is B
The detection cycle of the section is shown. Therefore, the equation (1) becomes the equation (2).

First, in the processing block 401, the cycle of continuous FG signals is calculated, and in the branch 402, the deviation amount is obtained from the cycle of the FG signal, and it is determined whether the difference between the deviation amounts of the continuous FG signals is substantially constant. . If the difference between the deviation amounts is not substantially constant, the rotation speed of the rotating body 1 is changing, and the rotating body 1 is based on the value of one cycle without correcting the cycle of the FG signal until the speed becomes constant.
Control. If the rotating body 1 starts to rotate at a constant speed,
In processing block 403, the gain of the control system is reduced by the gain switching means.

Next, in the processing block 404, the deviation amount of each of the A section and the B section designated by the channel selector 3a is calculated, and it is judged whether or not the branch 405 ends n times.
If it has not ended, the process returns to the processing block 404. When the processing is completed n times, the deviation amounts of the A section and the B section are averaged in the processing block 406, and then A is calculated from the average value of the B section.
The average value of the interval is subtracted, the subtraction result is halved, and the correction value ΔA
Seeking the value of.

After the correction value ΔA of the speed reference value is obtained, the gain of the control system is returned to the normal value by the gain switching means in processing block 407.

Next, in processing block 408, the speed reference value D is corrected using the correction value ΔA obtained in processing block 406. That is, in section A, the speed reference value D is -Δ
A is calculated, and in section B, speed reference value D is + Δ
If the calculation of A is performed, the deviation of the cycle of the FG signal can be corrected. The correction of the speed reference value D is expressed by equations (3) and (4).

D _A = D−ΔA (3) D _B = D + ΔA (4) where D _A and D _B are the corrected speed reference values for the A section and the B section, respectively, and are stored in the memory 3c. It

Then, the process shifts to the FG period correction control of the processing block 409. The calculation formula of the quick start error output by the calculator 3b after shifting to the FG cycle correction control is to use the corrected speed reference values D _A and D _B obtained by the formulas (3) and (4) (5) , Equation (6) is obtained.

O _A = A−D _B (5) O _B = B−D _B (6) where O _A is the speed error output of section A and O _B is the speed error output of section B.

In this way, the deviation of the period of the FGS signal is corrected using the correction value ΔA obtained from the equation (2) as in the equations (3) and (4), so that highly accurate control is possible. It will be possible. After shifting to the FG cycle correction control, the reference value D
Changes only to the corrected reference values D _A and D _B , so the processing as a processor is no different from normal processing.
Furthermore, since the correction operation is performed with a fixed value after shifting to the FG cycle correction control, it does not adversely affect the control system like a compensation filter (for example, a trap filter).

In the flowchart of FIG. 4, the correction value ΔA is obtained from the deviation amounts of the A and B sections, but it is also possible to obtain it from each cycle. That is, if the speed reference value D is not taken into consideration in the equations (1) and (2), the correction value is obtained only from the detected values of the periods A and B.

Next, a speed control device according to a second embodiment of the present invention will be described. In the second embodiment, a speed control device in which the FG cycle correction function operates normally even if the correction value deviates for some reason after shifting to the FG cycle correction control will be described.

In the second embodiment, the correction value of the speed reference value is calculated, and FG
Since the operation is the same as that of the first embodiment until the operation for the period correction is started, the description thereof will be omitted. Therefore, the operation after shifting to the FG cycle correction operation will be described here.

FIG. 5 shows a flow chart for explaining the operation of the monitor means for monitoring whether or not the FG cycle correction operation is operating normally after shifting to the FG cycle correction operation.

In processing block 501, error outputs O _A and O _B in the A section and the B section are calculated. (This processing block is carried out at a rate control process may be used and the results.) Then, determined in process block 502, A section, B section of each error output O _A, the absolute value of the difference between O _B, It is determined whether or not the value is less than or equal to a threshold value S. Error output O _A, the absolute value of the difference between O _B is transitions to processing block 503 if more than the threshold value S, and ends by substituting "0" to the monitor counter R. In branch 502, if the absolute value of the difference between the error outputs O _A and O _B is greater than or equal to the threshold value S, the process proceeds to processing block 504, and the monitor counter R is incremented. In the branch 505, if the value of the monitor counter R is smaller than N _R (threshold value of the monitor counter R), the process ends. If it is larger than N _R , the process proceeds to the processing block 506, and the process of recalculating the correction value ΔA is performed. , (3) and (4) are used to correct the speed reference value D to obtain the corrected speed reference values D _A and D _B , and the FG accuracy correction operation is performed again.

As described above, even if the correction value ΔA is deviated, the correction value is calculated again by providing the monitor means, so that it is possible to cope with the problem without any problem.

As described above, according to the present embodiment, the deviation of the cycle of the FG signal is detected when the deviation amount of the cycle value of the continuous FG signal becomes substantially constant, the speed reference value D is corrected, and the correction is performed. The corrected speed reference values D _A , D _B are stored in the memory 3c of the processor 3 as the subsequent speed reference values D _A , D _B , and are corrected at the time of constant speed rotation.
Since the speed error is calculated by using, the error output that is not affected by the deviation of the cycle of the FG signal can be output, and highly accurate control can be realized. Further, even if the correction value ΔA is deviated, the correction value is calculated again by providing the monitor means, so that it can be dealt with without any problem.

In this example, the alternating voltage induced in the stator winding of the rotating body was used to create the FG signal, but an FG signal created by another method has a cycle of half the frequency of the FG signal. If there is a deviation, the present invention exerts a sufficient effect.

Further, although the processor is used to configure the channel selector, the arithmetic unit, the memory, the cycle detector, the speed reference value correcting means, the gain switching means, and the monitoring means, it does not matter even if they are configured by individual hardware.

EFFECTS OF THE INVENTION As described above, according to the present invention, cycle detecting means for detecting a cycle of an AC signal having speed information of a rotating body, memory means for storing a detected value of the cycle detecting means, the detected value and a reference value. An arithmetic unit for calculating an error output from the drive unit, and a drive unit for supplying drive power to the rotating body based on the error output,
The first and second deviation amounts are calculated from the consecutive first and second cycle detection values stored in the memory means and the reference value, and the first and second deviation amounts are subtracted. Correction value calculating means for calculating a correction value of the reference value from the calculation result when the value is substantially constant, reference value correcting means for correcting the reference value of each cycle by the correction value, and the correction value It is characterized in that it comprises a gain switching means for making the gain of the control system smaller during the operation of the calculation means than during the normal operation, and the reference value corrected by the reference value correction means and the period detection means. The FG is characterized by comprising monitor means for monitoring that the error output calculated by the arithmetic unit is substantially constant based on the detected value. The deviation amount of the period value of the signal becomes almost constant. Is detected, the speed reference value D is corrected, and the corrected speed reference values D _A , D _B are stored in the memory 3c of the processor 3, and at the time of constant speed rotation, the corrected speed reference values D, D Since the speed error is calculated using
It is possible to output an error output that is not affected by the deviation of the signal cycle, and it is possible to achieve highly accurate control, which is a great effect. Further, when the correction value of the speed reference value is calculated, the gain of the control system is lowered by the gain switching means, so that the correction value can be obtained with higher accuracy.

Further, since the monitoring means constantly monitors whether or not the correction operation is normally performed, the correction value is calculated again even if the correction value is deviated due to a load change or the like. Control can be maintained.

[Brief description of drawings]

FIG. 1 is a block diagram of a speed controller in one embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the circuit operation, FIG. 3 is a flow chart for explaining the operation of a channel selector, and FIG. FIG. 5 is a flow chart for explaining the operation of the speed reference value correcting means, and FIG. 5 is a flow chart for explaining the operation of the monitor means. 1 ... motor, 2 ... waveform shaper, 3 ... processor,
3a …… Channel selector, 3b …… Calculator, 3c …… Memory, 3d …… Cycle detector, 4,5,6 …… Data bus, 7 ……
Digital-analog converter, 8 ... Power amplifier.

Continuation of front page (56) Reference JP-A-55-141817 (JP, A) JP-A-60-226784 (JP, A) JP-A-61-1286 (JP, A) JP-A-61-266086 (JP , A) JP 62-126882 (JP, A) JP 62-236372 (JP, A) JP 1-101721 (JP, A) JP 1-103183 (JP, A) JP 1-126182 (JP, A) JP-A 1-144378 (JP, A) JP-A 1-298975 (JP, A) JP-A 64-26385 (JP, A)

Claims (4)

(57) [Claims] 1. A cycle detecting means for detecting a cycle of an AC signal having speed information of a rotating body, a memory means for storing a detected value of the cycle detecting means, and an error output calculated from the detected value and a reference value. An arithmetic unit, a driving unit that supplies driving power to the rotating body based on the error output, and a first from the consecutive first and second cycle detection values and the reference value stored in the memory unit. Correction value calculation means for calculating a second deviation amount, and calculating a correction value for the reference value from the calculation result when the subtraction value of the first and second deviation amounts is substantially constant,
A speed control device comprising a reference value correction means for correcting the reference value of each cycle by the correction value, and a gain switching means for making the gain of the control system smaller when operating the correction value calculating means than during normal operation. . 2. The address of the memory means for storing the detected value of the cycle detecting means is updated every time the cycle detecting means detects the cycle over at least two cycles of the AC signal having the speed information of the rotating body, and the arithmetic unit is further provided with the above-mentioned means. 2. The speed control device according to claim 1, further comprising a channel selector which compares the cycle data stored in the corresponding address of the memory means with a reference value and sends an error output corresponding to the magnitude to the drive means. 3. A cycle detecting means for detecting a cycle of an AC signal having speed information of a rotating body, a memory means for storing a detected value of the cycle detecting means, and an error output calculated from the detected value and a reference value. An arithmetic unit, a driving unit that supplies driving power to the rotating body based on the error output, and a first from the consecutive first and second cycle detection values and the reference value stored in the memory unit. Correction value calculation means for calculating a second deviation amount, and calculating a correction value for the reference value from the calculation result when the subtraction value of the first and second deviation amounts is substantially constant,
Reference value correction means for correcting the reference value of each cycle by the correction value, and the error output calculated by the calculator based on the reference value corrected by the reference value correction means and the detection value of the cycle detection means are substantially A speed control device comprising monitor means for monitoring a constant value. 4. The speed control device according to claim 3, wherein the correction value of the reference value is calculated again when the monitor means determines that the error output is not substantially constant.