JP2553135B2 - Base current compensation circuit for variable gain circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of use) The present invention relates to a variable gain circuit used in, for example, a television receiver or the like, and more particularly to improvement of a base current compensation circuit thereof.

(Prior Art) As is well known, for example, a variable gain circuit used in a high frequency section of a television receiver is constructed as shown by a portion surrounded by a dotted line in FIG. That is, 11,1 in the figure
Reference numeral 2 denotes a pair of input terminals to which input signals are supplied, which are respectively connected to the bases of NPN type transistors Q ₁ and Q ₂ . These transistors Q ₁ and Q ₂ have their emitters connected in common via a resistor R ₁ and are grounded via constant current sources I ₁ and I ₂ to form a differential amplifier 13. are doing.

Each of the collectors of the transistors Q ₁ and Q ₂ is a differential amplifier 1
They are connected to each emitter common connection point of the transistors Q _3, Q ₄ and Q _5, Q ₆ of the NPN type which constitutes the 4,15. The collectors of the transistors Q ₃ and Q ₆ are connected to the output terminals 16 and 17, respectively.
DC voltage + V via resistors R ₂ and R ₃
It is connected to the power supply terminal 18 to which _CC is applied. The collectors of the transistors Q ₄ and Q ₅ are both connected to the power supply terminal 18.

Here, it is the non-inverting input terminals of the differential amplifiers 14 and 15. The bases of the transistors Q ₃ and Q ₆ are both connected to the control input terminal 19. It is also the inverting input terminal of the differential amplifiers 14 and 15. The bases of the transistors Q ₄ and Q ₅ are both connected to the control input terminal 20. The differential amplifier 13
~ 15 constitutes a double-balanced variable gain circuit 21, which amplifies the input signal supplied to the input terminals 11 and 12 with a gain corresponding to the gain control signal supplied to the control input terminals 19 and 20. , Output terminals 16 and 17.

Specifically, the gain of the variable gain circuit 21 is controlled by the magnitude of the voltage level applied between the control input terminals 19 and 20. That is, as the potential of the control input terminal 19 is made higher than the potential of the control input terminal 20, the amount of signals distributed to the resistors R ₂ and R ₃ is increased and the gain is increased. On the contrary, as the potential of the control input terminal 19 is made lower than the potential of the control input terminal 20, the gain is reduced.

Here, in the variable gain circuit 21 as described above, when used in a high frequency region, generally, the collector current of the transistor is increased in order to lower the impedance of the circuit and to increase the transition frequency _T of the transistor. Designed. However, if the transistor collector current is designed to be large, the grounded emitter AC current amplification factor β of the transistor decreases and the base current increases, so the current input via the control input terminals 19 and 20 is controlled. An external circuit (not shown) installed at the input terminals 19 and 20 is adversely affected, and the maximum gain of the variable gain circuit 21 is lowered, and the control range is narrowed.

Therefore, conventionally, a base current compensation circuit shown outside the frame shown in FIG. 4 the dotted lines, in addition to the variable gain circuit 21 compensates the base current of the transistor Q ₃ to Q _6, it has disadvantages described above do not occur I am trying. That is, the control input terminals 19 and 20 are connected to the collectors of the PNP type transistors Q ₇ and Q ₈ , respectively. These transistors Q ₇ and Q ₈ are
The base is connected together with another PNP type transistor Q ₉ to form a current mirror circuit 22, and the emitters of the transistors Q _{7 to} Q ₉ are connected to the power supply terminal 18 via resistors R _{4 to} R ₆ , respectively. It is connected.

The collector and the base of the transistor Q ₉ are commonly connected, and the connection point is connected to the base of the NPN transistor Q ₁₀ . This transistor Q ₁₀ has its collector connected to the power supply terminal 18 and its emitter a constant current source.
Grounded through I ₃ .

In the base current compensation circuit configured as described above, the transistor Q ₁₀ is for monitoring the sum of the base currents of the transistors Q ₃ and Q ₆ and the sum of the base currents of the transistors Q ₄ and Q _{5. If 1} = I ₂ = I ₃ , then control input terminals 19, 2
When the potential difference between the 0 is "0", the base current of the transistor Q ₁₀ is equal to the sum of the base currents of the transistors Q _3, Q ₆ and Q _4, Q _5. The base current of the transistor Q ₁₀ is turned back by the current mirror circuit 22 are added respectively to the respective bases of the transistors Q _3, each base and the transistor Q ₄ of Q _6, Q _5, here the transistor Q ₃ to Q The base current of ₆ is compensated, and the input current to the control input terminals 19 and 20 seen from the outside can be made "0".

Mathematically analyzing the above base current compensation action,
It looks like this: First, the differential output v of the variable gain circuit 21
₀ is the potential difference between the control input terminals 19 and 20, ΔV, the input signal between the input terminals 11 and 12 is v _i , the emitter resistance of the transistor is re, and R ₂ = R ₃ = R, R ₁ ＝ R _E , I ₁ ＝ I ₂ ＝
I Becomes However, in equation (1), And (K: Boltzmann constant, q: elementary electron content, T: absolute temperature).

On the other hand, in the base current compensation circuit, ΔV = 0, R ₄ =
If R ₅ = R ₆ and I ₃ = I and the base currents of the transistors Q _{3 to} Q ₆ are I _{B3 to} I _B6 , Becomes Also, the base current I _B10 of the transistor Q ₁₀ is Becomes Here, the transistors Q ₈ , Q ₉ and the transistor Q
_{When the} current ratios of ₇ and Q ₉ are set to 1: 1 respectively, the collector currents I _C7 and I _C8 of the transistors Q ₇ and Q ₈ are I _C7 = I _C8 = I _B10 (5). Then, if the formula (2) is subtracted from the formula (4), Similarly, if you subtract equation (3) from equation (4), Becomes Since (1 + β) ² >> 0, the above equations (6) and (7) can be expressed as I _B10 I _B3 + I _B6 (8) I _B10 I _B4 + I _B5 (9) it can. Therefore, the above (5),
From the equations (8) and (9), I _B10 = I _C8 = I _C7 = I _B3 + I _B6 = I _B4 + I _B5 (10), and the transistors Q ₃ and Q ₆ and the transistors Q ₄ and Q ₅ are The base current can be compensated.

However, the conventional base current compensation circuit as described above has the following problems. That is, the current I _B10 for base compensation described above is constant regardless of the gain control of the variable gain circuit 21, and its current value is set so that complete base current compensation is performed when ΔV = 0. ing.

On the other hand, on the variable gain circuit 21 side, if the potential of the control input terminal 19 is higher than the potential of the control input terminal 20, the transistor
The sum of the base currents of Q ₃ and Q ₆ is larger than the sum of the base currents when ΔV is “0”, and the sum of the base currents of transistors Q ₄ and Q ₅ is when the ΔV is “0”. It is smaller than the sum of base currents. On the contrary, the control input terminal 19
Is lower than the potential of the control input terminal 20, the sum of the base currents of the transistors Q ₃ and Q ₆ is smaller than the sum of the base currents when ΔV is “0”, and the transistors Q ₄ and Q ₅
Is larger than the sum of the base currents when ΔV is “0”.

Therefore, in the conventional base current compensation circuit, complete base current compensation can be performed only when the potential difference ΔV between the control input terminals 19 and 20 is “0”, and when ΔV is other than “0”, The problem arises that accurate base current compensation cannot be performed.

(Problems to be Solved by the Invention) As described above, the conventional base current compensation circuit of the variable gain circuit has a problem that accurate base current compensation cannot be performed depending on the gain control state of the variable gain circuit. ing.

Therefore, the present invention has been made in consideration of the above circumstances, and provides an extremely good base current compensating circuit for a variable gain circuit that can always perform accurate base current compensation regardless of the gain control state of the variable gain circuit. The purpose is to

[Structure of the Invention] (Means for Solving the Problems) The present invention relates to a first differential pair transistor which has emitters commonly connected and whose bases serve as a pair of signal input terminals.
A common emitter is correspondingly connected to each collector side of the first differential pair transistor, and non-inverting input terminals and bases serving as inverting input terminals are commonly connected to form a pair of control input terminals. A double-balanced variable gain circuit that includes a second differential pair transistor and a third differential pair transistor, and that amplifies the input signal supplied to the signal input terminal with a gain according to the gain control signal supplied to the control input terminal. Is intended for.

A fourth differential pair transistor, which is commonly connected to the emitters and has a base to which a gain control signal is supplied to monitor collector outputs of the second and third differential pair transistors, and a fourth differential pair transistor. It is configured to include a converting means for converting the collector output current of the transistor into a compensating base current, and an adding means for adding the compensating base current output from the converting means to the pair of control input terminals.

(Operation) According to the configuration as described above, the collector output current of the fourth differential pair transistor for monitoring the collector outputs of the second and third differential pair transistors is converted into the compensating base current, and paired. Since it is added to the bases of the second and third differential pair transistors, which are the control input terminals of, the base current compensation can always be performed accurately regardless of the gain control state of the variable gain circuit.

(Embodiment) Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, since the variable gain circuit 21 has the same configuration as that in FIG. 4, the same signals are given to the same portions and the description thereof will be omitted. That is, control input terminal 1
Reference numerals 9 and 20 are connected to the bases of NPN type transistors Q ₁₂ and Q ₁₁ , respectively. The emitters of the transistors Q ₁₁ and Q ₁₂ are commonly connected, and the connection point is a constant current source.
The differential amplifier 23 is configured by being grounded via I ₄ .

The differential amplifier 23 is connected in parallel to the variable gain circuit 21 to monitor the output currents of the differential amplifiers 14 and 15. That is, a current substantially equal to the sum of the collector currents of the transistors Q ₃ and Q ₆ flows to the collector of the transistor Q ₁₂ and
_A current approximately equal to the sum of the collector currents of ₄ and Q ₅ flows into the collector of the transistor Q ₁₁ .

Here, the collector output current of transistor Q ₁₁ is PNP
Through a current mirror circuit 24 composed of transistors Q ₁₃ and Q ₁₄ and resistors R ₇ and R ₈ and a current mirror circuit 25 composed of NPN transistors Q ₁₅ and Q ₁₆ and resistors R ₉ and R ₁₀ . NP
It is supplied to the emitter of the N-type transistor Q ₁₇ . In this transistor Q ₁₇ , the collector current of the transistor Q ₁₁ , which is approximately equal to the sum of the collector currents of the transistors Q ₄ and Q ₅ , is used as its emitter current via the current mirror circuits 24 and 25, so that the transistor Q ₄ , A base current equal to the sum of the base currents of Q ₅ is generated.

Then, the base current of the transistor Q ₁₇ is added to the bases of the transistors Q ₄ and Q ₅ via the current mirror circuit 26 including the PNP transistors Q ₁₈ and Q ₁₉ and the resistors R ₁₁ and R _12. , The base currents of the transistors Q ₄ and Q ₅ are compensated.

The collector current of the transistor Q ₁₂ is the current mirror circuit 27 composed of PNP type transistors Q ₂₀ and Q ₂₁ and resistors R ₁₃ and R ₁₄ , and the NPN type transistors Q ₂₂ and Q ₂₃ and resistor R ₁₃ .
Via the current mirror circuit 28 composed of ₁₅ and R ₁₆ ,
Shaped transistor Q ₂₄ is supplied to the emitter. In this transistor Q ₂₄ , the collector current of the transistor Q ₁₂ which is approximately equal to the sum of the collector currents of the transistors Q ₃ and Q ₆ is used as its emitter current via the current mirror circuits 27 and 28, so that the transistor Q ₃ , A base current equal to the sum of the base currents of Q ₆ is generated.

Then, the base current of the transistor Q ₂₄ is added to the bases of the transistors Q ₃ and Q ₆ via the current mirror circuit 29 including the PNP transistors Q ₂₅ and Q ₂₆ and the resistors R ₁₇ and R _18. , The base currents of the transistors Q ₃ and Q ₆ are compensated.

Here, the sum of the collector currents of the transistors Q ₃ and Q ₆ is the voltage level between the control input terminals 19 and 20 and the constant current source I ₁ and
It is given as a function of the current flowing in I ₂ . The sum of the collector currents of the transistors Q ₄ and Q ₅ is also given as a similar function. And each transistor Q ₃ ~
The base of Q ₆ requires a current corresponding to each collector current.

Therefore, when the currents flowing through the constant current sources I ₁ and I ₂ are equal and the current flowing through the constant current source I ₄ is set to be (1 / n) times the current flowing through the constant current sources I ₁ and I ₂ , The current (1 / n) times the sum of the collector currents of the transistors Q ₃ and Q ₆ is the transistor Q ₁₂
Of the transistor Q ₄ and Q _{5, and} a current (1 / n) times the sum of the collector currents of the transistors Q ₄ and Q ₅ flows to the collector of the transistor Q ₁₁ .

Then, the collector currents of the transistors Q ₁₁ and Q ₁₂ are
Via the current mirror circuits 24, 25 and 27, 28, respectively,
It is converted into a compensating base current by the transistors Q ₁₇ and Q ₂₄ and added to each base of the transistors Q ₃ , Q ₆ and Q ₄ , Q ₅ via the current mirror circuits 26, 29. , The mirror ratio of the current mirror circuits 26 and 29 is set to be 1: n + 1, taking into consideration the base currents required for the transistors Q ₁₁ and Q ₁₂ . Therefore, the transistors Q ₁₇ and Q
N times the current of the base current of _24, the transistors Q _3, Q ₆ and Q _4, Q together with the base current compensation is performed is added to the base _5, the transistors Q _17, Q base current transistor Q ₁₁ of the ₂₄ , Q ₁₂ will be supplied to the base.

Next, a mathematical analysis of the above-described base current compensation action is as follows. First, I ₁ = I ₂ = I, I ₄ = (2 /
n) I, the base currents I _B3 , I of the transistors Q ₃ , Q ₆
The sum of _B6 is And the sum of the base currents I _B4 and I _B5 of the transistors Q ₄ and Q ₅ is Becomes Also, the collector current I of transistor Q _12
C12 is And the collector current I _C11 of transistor Q ₁₁ is Becomes In addition, the base current I of transistor Q _24
B24 is And the base current I _B17 of transistor Q ₁₇ is Becomes

Here, the mirror ratio of the current mirror circuits 26 and 29 is 1: n.
Therefore, the collector currents I _C26 and I _C19 of the transistors Q ₂₆ and Q ₁₉ are Becomes Then, the first item on the right side of the equation (17) is equal to the equation (11), and the second item is equal to the equation (15), that is, the base current of the transistor Q ₁₂ . In addition, (1
The first item on the right side of equation (8) is equal to equation (12) above,
The item is equal to the above equation (16), that is, the base current of the transistor Q ₁₁ . Then, the above equation (17) and (1
Since each base current given by the equation (8) is a function of the voltage level ΔV between the control input terminals 19 and 20, the base current can be accurately compensated regardless of the gain control state.

Next, FIG. 2 shows the collectors of the transistors Q ₃ and Q ₄ when a current of ₂ mA is applied to each of the constant current sources I ₁ and I ₂ to change the voltage level ΔV between the control input terminals 19 and 20. It shows a change in current. The curve shown by the solid line in FIG. 2 shows the characteristic when the base current compensation is performed using the base current compensation circuit according to the embodiment shown in FIG. 1, and the curve shown by the dotted line in the same figure is FIG. The characteristics of the conventional base current compensating circuit shown in Fig. 4 are shown when the base current is compensated, and it can be seen that the circuit of the embodiment compensates the base current more accurately than the conventional circuit. .

FIG. 3 shows another embodiment of the present invention. That is, the signals supplied to the control input terminals 19 and 20 are supplied to the differential amplifier 30 from the NPN type transistors Q ₂₇ and Q ₂₈ and the constant current source I _5.
To monitor the collector output currents of the differential amplifiers 14 and 15. And the transistors Q ₂₇ , Q
Each collector output current of ₂₈ can be directly converted to NPN transistor Q.
_The current mirror circuit 31 is composed of PNP type transistors Q ₃₁ and Q ₃₂ and resistors R ₁₉ and R ₂₀ and is converted into a compensation base current by ₂₉ and Q ₃₀ , and PNP type transistors Q ₃₃ and Q ₃₄ and resistor R _21. , R
_A current mirror circuit 32 composed of ₂₂ is added to the bases of the transistors Q ₄ , Q ₅ and Q ₃ , Q ₆ .

According to such a configuration, compared to the embodiment shown in FIG. 1, it is necessary to set the DC voltage V _CC higher by the amount of the base-emitter voltage V _{BE of} the transistor, but the configuration is simplified. Accurate base current compensation can be realized.

The present invention is not limited to the above-described embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide an extremely good base current compensation circuit for a variable gain circuit that can always perform accurate base current compensation regardless of the gain control state of the variable gain circuit. can do.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a characteristic curve diagram for explaining the effect of the same embodiment, and FIG. 3 is a circuit configuration diagram showing another embodiment of the present invention. FIG. 4 is a circuit configuration diagram showing a conventional base current compensation circuit. 11,12 …… Input terminals, 13 to 15 …… Differential amplifier, 16,17 ……
Output terminal, 18 …… Power supply terminal, 19,20 …… Control input terminal, 2
1 ... Variable gain circuit, 22 ... Current mirror circuit, 23 ...
Differential amplifier, 24-29 …… Current mirror circuit, 30 …… Differential amplifier, 31,32 …… Current mirror circuit.

Claims (1)

(57) [Claims] 1. A first differential pair transistor having emitters commonly connected to each other and having bases as a pair of signal input terminals, and a common emitter corresponding to each collector side of the first differential pair transistor. A pair of second and third differential pair transistors that are connected to each other and have their bases serving as non-inverting input terminals and inverting input terminals commonly connected to each other to form a pair of control input terminals. In a double-balanced variable gain circuit for amplifying an input signal supplied to the signal input terminal with a gain according to a supplied gain control signal, the emitters are commonly connected and the gain control signal is supplied to each base, A fourth differential pair transistor that monitors the collector outputs of the second and third differential pair transistors, and a collector output current of the fourth differential pair transistor are complemented. Base current of the variable gain circuit, comprising: a converting means for converting into a base current for conversion; and an adding means for adding the compensating base current output from the converting means to the pair of control input terminals. Compensation circuit.