JP2543870B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a dynamic semiconductor memory device having a one-transistor / one-capacitor memory cell structure.

(Prior Art) In recent years, the density and capacity of semiconductor memory devices have been remarkably increased. This is especially noticeable in MOS dynamic RAM (dRAM). In the case of dRAM, the memory cell capacity, which was 70fF or more at 64k, decreases as the capacity increases to 256k, 1M, and at 1M and 4M, it is difficult to secure 40fF even if the conventional planar capacitor is changed to a trench capacitor. Has become. Therefore, it is becoming more and more difficult to increase the data retention time of the memory cell according to the specifications.

However, in the actual dRAM, the data retention time becomes longer as the capacity increases. This is because there is a strong demand from the user side to keep the duty ratio the same as before even if the capacity of the dRAM is increased. Here, the duty ratio of the dRAM means the ratio of the access time excluding the refresh time to the total operation time. In order to meet such demands, in 64kdRAM, 128 refresh cycles are provided every 2msec to refresh all word lines, whereas in 256kdRAM, 256 refresh cycles are performed every 4msec, and 1mdRAM is 8m. The refresh cycle is increased to 512 refresh cycles per sec.
This lengthens the data retention time.

That is, in the conventional dRAM, the number of word lines selected at the time of read or write access and at the time of refresh is the same as one or two. Therefore, when the capacity is increased, all word lines are sequentially selected. It took time, and the time required for refreshing increased accordingly.

(Problems to be Solved by the Invention) As described above, increasing the refresh period together with increasing the capacity in order to keep the duty ratio of the dRAM small does not increase the data retention capacity when the memory cell is further miniaturized. It's a matter of relationship.

An object of the present invention is to provide a dRAM in which such a problem is solved.

[Configuration of the Invention] (Means for Solving the Problems) The present invention reduces the time required to refresh all memory cells by setting the number of word lines selected at the time of refreshing to a plurality. Therefore, in the present invention, the divided bit line system is adopted. That is, a plurality of pairs of divided bit lines are connected to the main bit lines via transfer gates, and a plurality of memory cells are connected to each divided bit line. A divided bit line sensor amplifier is provided for each divided bit line, and a main bit line sense amplifier is provided for the main bit line. Then, at the time of refresh, all transfer gates are made non-conductive, a pair of divided bit lines is separated from the main bit line, one word line is selected for each divided bit line, and selected by the divided bit line sense amplifier. The memory cell is refreshed for each word line.

In the present invention, it is desirable to simultaneously select a plurality of word lines not only at the time of refreshing but also at the time of active operation including writing or reading. In this case, word lines are selected by turning off all the transfer gates between the pair of divided bit lines and the pair of main bit lines. Then, at the time of a write operation or a read operation, a pair of divided bit lines is connected to the main bit line pair by turning on a set of transfer gates, thereby performing selective write or read.

It is also possible to select one word line during a write or read operation as in the conventional case, and select a plurality of word lines corresponding to the number of pairs of divided bit lines only during refresh.

(Operation) According to the present invention, since a plurality of word lines are selected by one refresh, the refresh cycle is shortened and the time required for all refresh is significantly shortened as compared with the conventional one. Specifically, for example, the number of word lines is 1024
Taking 1Mbit dRAM as an example, the conventional method uses 1
Two word lines are selected for each refresh, and all the word lines are refreshed by 512 refresh operations. At this time, the total refresh time was 200 (n sec) × 512 = 102.4 (μsec) even if the cycle time was set to the shortest 200 n sec.

On the other hand, for example, when one bit line pair is composed of eight divided bit line pairs according to the present invention and the number of word lines selected by one refresh is 16, the refresh operation is performed 64 times. The refresh is completed for all word lines. At this time, the time required for full refresh is 200 (n sec) x 64 = 12.8 (μsec). This is 1/8 of the conventional method.

Further, in the present invention, if a plurality of word lines are selected at the same time during active operation, the number of row decoders can be smaller than in the prior art. For example, when one main bit line pair is composed of eight divided bit line pairs, the number of row decoders is 1/8 of the conventional one. As a result, the pattern area and the power consumption due to the charging and discharging of the row decoder are greatly reduced.

(Example) Hereinafter, the Example of this invention is described.

FIG. 1 shows a configuration of a core circuit section of a dRAM according to one embodiment.
In the figure, BLi, ▲ ▼ (i = 1,2, ..., m) is a main bit line pair, and each main bit line pair BLi, ▲ ▼ is provided with a main bit line sense amplifier BSi. There is. Each main bit line pair BLi, ▲ ▼ also has a plurality of divided bit line pairs DBLij, ▲ ▼ (i = 1,
2, ..., m, j = 1,2, ..., n) are transfer gates Tij1, Tij
Connected via 2. Each divided bit line pair DBLij, ▲
Each ▼ has a plurality of memory cells Mij
1, one divided bit line sense amplifier DBSij is provided. WL11, WL12, ... Are word lines, DSj is a split bit line select signal for controlling transfer gates Tij1, Tij2, ..., Fj is a split bit line sense amplifier activation signal, and AS is a main bit line sense amplifier activation signal. Signal.

FIG. 2 shows the structure of the row decoder RD portion for selecting the word line. For example, in the case where eight divided bit line pairs are provided for one bit line, the number of row decoders RD is 1/8 of the conventional one, and as shown in the figure, one word line driver WD is used for plural words. The lines are selectively driven at the same time.

FIG. 3 is an operation waveform diagram of the main node at the time of refresh operation in this embodiment, and FIG. 4 is an operation waveform diagram of the main node at the time of reading or writing. The operation will be described below with reference to these figures.

When the active operation starts, the divided bit line selection signal DS
j becomes all “L” level and all transfer gates T
Make ij1, Tij2, ... Non-conductive. That is, all the divided bit line pairs DBLij, ▲ ▼ are the main bit line pairs BLi, ▲
Separated from ▼. Next, a row address is input, and n word lines are selected for each divided bit line pair DBLij, ▲ ▼. Now, for example, the word line WL11, W at the first address in each divided bit line pair
L21, WL31, ... WLn1 are simultaneously selected. afterwards,
The divided bit line sense amplifier activation signal Fj is simultaneously input, the divided bit line sense amplifier DBSij is activated, and the divided bit line pairs DBLij and DBLij that have been precharged to (1/2) V _DD are respectively Settled on V _DD or V _SS depending on the information content of. Here, V _DD and V _SS are the drain power source voltage and the source power source voltage, respectively. Thus, m × n memory cells (M111, M211, ..., Mm11) selected by the n word lines WL11, WL21, WL31, ... WLn1 (M121, M221, ..., Mm21),
..., (M1n1, M2n1, ..., Mmn1) is rewritten.

After this, a refresh operation in which no column address is input, that is, ▲ ▼ only refresh or ▲ ▼
▼ Before ▲ ▼ For refresh, auto refresh, etc., select multiple word lines WL11, WL21,
..., WLn1 returns to the original state, and one refresh operation ends.

When writing or reading in which a column address signal is input, when the rewriting of the memory cell is completed and the column address is taken into the chip, the latched row address signal is unlatched. The line selection signal DS ₁ is selected. As a result, the transfer gates T111, T112, T211, T212, ... Tm11, Tm12 are rendered conductive, and the contents of the memory cells M111, M211, ..., Mm11 are transferred to the main bit via the divided bit lines DBL11, DBL21, ..., DBLm1. Line BL
It is transmitted to 1, BL2, ..., BLm. After that, the bit line sense amplifier activation signal AS is input and the bit line sense amplifier BS1,
BS2, ..., BSm are activated, and logical "1" and "0" are judged.
Next, at least one set of main bit line pairs selected by the column address is connected to the input / output line, and the data stored in the memory cell is read or written. That is, in this embodiment, while a plurality of word lines are simultaneously selected, signal charges are actually exchanged between the divided bit lines and the main bit lines only for the memory cells along one word line.

In the precharge cycle after the refresh operation is completed or after the read / write operation is completed, all the transfer gates are turned on by the divided bit line selection signal DSj. Then, when the refresh operation or the read / write operation is started, all the transfer gates are once brought into a non-conducting state, and then the transfer gates are controlled so as to be brought into conduction as necessary.

As described above, according to this embodiment, as a divided bit line system, a plurality of word lines are selected by one active operation to refresh each word line, compared with the conventional system. Therefore, the refresh cycle is significantly shortened. Therefore, even in the case of a dRAM whose memory cell is miniaturized and has a large capacity, highly reliable operation becomes possible. Further, in the conventional method in which the number of row decoders is the same as the number of word lines, the row
Decoders are becoming more difficult to design. In this respect, in this embodiment, since a plurality of word lines are selected at the same time, the number of row decoders is small, integration is facilitated, and power consumption is reduced.

In the above embodiment, the same number of word lines as the number of divided bit lines are selected during the active operation, the write operation and the read operation. However, the plurality of word lines are selected only during the refresh operation. You can also

FIG. 5 and FIG. 6 show operation waveforms for explaining the operation in such an embodiment, corresponding to FIG. 3 and FIG. 4, respectively.

That is, when the refresh operation starts, this is detected and all the divided bit line selection signals DSj are set to the "L" level, and all the divided bit line pairs are separated from the main bit line pairs. Then, the row address counter for refreshing built in the chip operates, and n word lines WL11, WL21, ..., WLn1 are selected for each divided bit line pair, and memory cells along these word lines are selected. Is refreshed.

When the read or write operation is started, one word line is selected by the external input address. For example, assume that the word line WL11 is selected. At this time, the divided bit line sense amplifier activation signal F1 is input, and the divided bit line sense amplifiers DBS11, DBS21, ..., DBSn1 are activated. When the sense operation by these sense amplifiers is completed, the divided bit line selection signal DS1 is input and the memory cells M111, M21
The contents of 1, ..., Mm11 are divided bit lines DBL11, DBL21, ..., DBLm1
, BLm to the main bit lines BL1, BL2, ..., BLm. After that, the bit line sense amplifier activation signal AS is input, the bit line sense amplifiers BS1, BS2, ..., BSm are activated, and the logic "1",
A judgment of "0" is made.

In the next refresh cycle, n word lines WL12, WL22, ..., WLn2 at the next address in each divided bit line are selected. Then, like the previous refresh operation, m × n memory cells along these word lines are simultaneously refreshed.

As described above, also in this embodiment, as a divided bit line system, a plurality of word lines are selected by one refresh operation to refresh each word line, as compared with the conventional one. Therefore, the refresh cycle is significantly shortened.

In the above embodiment, a plurality of word lines are selected at the same time when active, and the divided bit line sense amplifiers are all activated at the same time. However, the divided bit line sense amplifier activation signals F1, F2, ... The input may be controlled to be sequentially input at time intervals of. This is effective in suppressing the peak current and the current change rate during one active time.

Further, in the above embodiment, the precharge value of the bit line pair and the divided bit line pair is set to (1/2) V _DD , but the present invention is also effective when precharging to V _DD . Although the embodiment does not refer to the presence or absence of the dummy cell, the present invention is effective whether the dummy cell is used or not. Further, regarding the specific configurations of the main bit line sense amplifier and the divided bit line sense amplifier, in addition to a normal flip-flop type sense amplifier, a CMOS structure or a transistor is used.
The present invention can be applied to any case such as a so-called BICMOS structure in which CMOS is combined.

Further, in the above embodiment, when the rewriting of the memory cell is completed at the time of reading or writing and the column address is taken into the chip, the latched row address is unlatched and the divided bit line is selected. However, if the column address is taken into the chip, the divided bit line may be selected even if the rewriting of the memory cell is not completed. When the BICMOS structure main bit line sense amplifier in which the input line and the output line are separated is used, the column address may be taken into the chip earlier than the row address. In this case, the row address that selects the divided bit line selection signal is not latched, and when the row address is input, the divided bit line selection signal is selected almost at the same time as the word line.

[Effects of the Invention] As described above, according to the present invention, the time required for refreshing all word lines is significantly reduced, and the duty ratio for refreshing is improved. In other words, it can be said that the dRAM of the present invention is close to the sRAM in terms of ease of use in that the useless time of refreshing is small.

Also, if not only refresh but also multiple word lines are selected at the time of writing or reading,
The number of row decoders is smaller than the number of word lines, and high integration and large capacity of dRAM can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing a core circuit of a dRAM according to an embodiment of the present invention, and FIG. 2 is a diagram showing a configuration of a row decoder portion thereof.
FIG. 3 is an operation waveform diagram showing the refresh operation of the same, FIG. 4 is an operation waveform diagram showing the read / write operation of the same, and FIGS. 5 and 6 are third waveforms of other embodiments.
FIG. 7 is an operation waveform diagram corresponding to FIGS. M111, M112, M121, M122, …… Memory cell, BLi, ▲ ▼
...... Main bit line pair, DBLij, ▲ ▼ …… Divided bit line pair, BSi …… Main bit line sense amplifier, DBSij …… Divided bit line sense amplifier, WL11, WL12, ..., WLn1 …… Word line, Tij1, Tij2 ... Transfer gate, DSj ... divided bit line selection signal, Fj ... divided bit line sense amplifier activation signal, AS ... main bit line sense amplifier activation signal.

Claims (6)

(57) [Claims] 1. A plurality of word lines and a plurality of divided bit lines,
A memory cell arranged at an intersection of the word line and the divided bit line, and a plurality of memory cells arranged in parallel with the divided bit line and selectively connected to the divided bit lines via a switch. In a semiconductor memory device including a plurality of memory cell arrays each including a main bit line, the divided bit line and the main bit line form a pair, and the divided bit line pair includes a divided bit line sense amplifier,
Each main bit line pair is provided with a main bit line sense amplifier, and during the refresh operation, all the divided bit line pairs are separated from the main bit line pair by keeping all the switches in the off state, and The semiconductor memory device is characterized in that a plurality of word lines are selected for each, and the memory cells are refreshed by increasing the number of selected word lines as compared with the read and write operations. 2. The semiconductor device according to claim 1, wherein at the time of the refresh operation, the same number of word lines as or less than the number of divided bit lines connected to one of the main bit lines is selected. Storage device. 3. The semiconductor memory device according to claim 1, wherein a plurality of word lines are selected during one active operation including a write or read operation other than the refresh operation. . 4. The semiconductor memory device according to claim 1, wherein one word line is selected during writing or reading during one active operation. 5. When selecting the word line, all of the switches are kept in an off state so that all of the divided bit line pairs are separated from the main bit line pair, and in this state, the divided bit line sense amplifier. This refreshes one memory cell for each divided bit line pair,
The set of selected switches are turned on during writing or reading, and only one divided bit line pair is connected to one main bit line pair. Semiconductor memory device. 6. The semiconductor memory device according to claim 1, wherein the plurality of word lines are selected in one refresh operation and refreshed at predetermined time intervals.