JP2543589B2 - Data processing device - Google Patents

Description

The present invention relates to a data processing device by a microprogram process, and a control register and an instruction decoding device for reducing the microprogram process to increase the speed. Instruction decoder, microprogram storing means for outputting control information according to the decoding result of the instruction decoder, and control circuit for decoding the control mode of the control register by the control information which is a part of the decoding result of the instruction decoder And a writing / reading circuit for writing / reading a predetermined field to / from the control register according to a control mode as a decoding result of the control circuit and according to a write / read instruction signal from the microprogram storage means to / from the control register. It is configured to include.

[Industrial applications]

The present invention relates to a data processing device by microprogram processing.

Along with the sophistication of data processing devices, the number of instructions for performing complicated processing is increasing. In the data processing device, the number of microprograms has been increased and complicated in order to deal with the instruction, but it is necessary to reduce the load on the microprograms in order to perform data processing at high speed.

[Conventional technology]

As shown in FIG. 8, an example of the conventional data processing device is a control including an instruction decoder 1 for decoding an instruction, a microprogram ROM 2 for generating a microprogram using a decoding result of the instruction decoder 1 as an address, and a status register 3a. The register 3, an arithmetic unit (ALU) 4, a general-purpose register 5 including a plurality of registers R0, R1, ... The instruction register 6
An instruction is read from data from an external storage device (MSU) and stored in the. Note that C _{0 to} C ₄ indicate address signals or control signals.

The field configuration of the status register 3a of the control register 3 is, as shown in FIG. 9A, a control mode area CM for designating a debug mode, a normal mode, an interrupt mask area MK, a status flag for a branch instruction, etc. It is composed of area FG. As an instruction for such a status register 3a, for example, FIG.
There is one as shown in (G). The instruction 1 shown in FIG. 9 (B) is a case where the contents of the status register 3a are pushed up or popped down by a stack memory (not shown). In this case, the entire status register 3a becomes the operation target, and It doesn't matter. Ninth
In the case of the instruction 2 shown in FIG. 7C, only the flag area FG is updated. In the case of the instruction 3 shown in FIG. 9D, only the control mode area CM is updated. In the case of the interrupt processing instruction 4 shown, only the interrupt mask area is updated,
In the case of the instruction 5 shown in FIG. 9 (F), the control mode area CM and the flag area FG are updated. If such an operation target is the part of the status register 3a, which part is the operation target. Instruct by micro program whether to do. Further, the instruction 6 shown in FIG. 9 (G) is a case where one of the plurality of control registers is operated by one kind of instruction, and in this case, the microprogram does not correspond to the instruction type, and the selection of each control register is made. Corresponds to instructions that include bits.

[Problems to be Solved by the Invention]

In the case of updating only a part of the status register 3a as shown in FIGS. 9C to 9F, as described above, it is necessary to instruct which part is to be operated by the microprogram. This, in turn, increases the number of bits and steps the microprogram has to control. For example, as shown in FIG. 9 (F), when the status register part is included in a compressed form in the instruction,
In order to convert into a format suitable for the status register 3a, the microprogram must operate the arithmetic unit 4 over a plurality of cycles. FIG. 10 and FIG. 11 show the operation. That is, step (machine cycle) I
At, the instruction is decoded by the instruction decoder 1. In step II, the microprogram ROM2 outputs the microprogram MI1. During this time, the instruction code is displayed in the instruction register. In step III, the microprogram MI1 is executed (EX1), the instruction decode is transferred to the arithmetic unit 4, transfer processing (move) is performed, and the instruction code is stored in the general-purpose register R0. At the same time, the microprogram ROM2 outputs the microprogram MI2. That is, the contents of the general-purpose register R0 are transferred to the arithmetic unit 4, the shift operation is executed, and the result is stored in the general-purpose register R1.

At the same time, the microprogram ROM2 outputs the microprogram MI3. In step V, micro operation M
I3 is executed (EX3), that is, the OR logic of the contents of the general-purpose register R0 and the contents of the general-purpose register R1 is executed in the arithmetic unit 4, and the result is stored in the general-purpose register R1. At the same time, the microprogram ROM2 outputs the microprogram MI4. In step VI, the microprogram MI4 is executed (EX4), that is, the arithmetic unit 4
In, the AND logic of the contents of the general-purpose register R1 and the contents of the constant register (one of the general-purpose registers) (mask 1) is executed, and the result is stored in the general-purpose register R1. Also,
At the same time, microprogram ROM2 is a microprogram
Output MI5. In step VII, the micro program
MI5 is executed (EX5), that is, in the calculation unit 4,
The AND logic of the contents of the status register 3a and the contents of the constant register (one of general-purpose registers) (mask 2) is executed, and the result is stored in the general-purpose register R0. At the same time, the microprogram ROM2 is the microprogram MI6.
Is output. In step VIII, the micro operation M16 is executed (EX6), that is, the arithmetic unit 4 executes the AND logic of the contents of the general-purpose register R0 and the contents of the general-purpose register R1 and stores the result in the status register 3a.

In this way, the operation of the status register 3a of the instruction shown in FIG. 9 (F) is finished, but the number of steps and the number of execution cycles increase, which in turn causes a problem of a reduction in processing speed. .

For the instruction 6 as shown in FIG. 9 (G), as shown in FIG. 12, a plurality of microprograms corresponding to the control register type are prepared even if the instruction type is one. Therefore, there is a problem that the number of steps of the microprogram is increased, the number of execution cycles is also increased, and the processing speed is decreased.

As described above, conventionally, when the instruction becomes complicated, the function of the microprogram and the number of steps are simply increased. However, the addition of functions leads to an increase in the number of bits to be controlled by the microprogram, which leads to an increase in the number of steps for hardware and microprogram development as well as an increase in the number of steps.The number of steps corresponds to the execution cycle of the microprogram, and therefore corresponds to instructions The number of executed cycles increases, which hinders speeding up of processing.

Therefore, it is an object of the present invention to provide a data processing device that reduces the microprogram processing to increase the speed.

[Means for solving the problem]

Means for solving the above-mentioned problems include a control register, an instruction decoder for decoding an instruction, a microprogram storing means for outputting a microprogram according to the decoding result of the instruction decoder, and a decoding result of the instruction decoder. A control circuit that decodes the control mode of the control register according to a part of the control information, and a control mode that is a decoding result of the control circuit, and a write / read instruction signal from the microprogram storage means to the control register And a writing / reading circuit for writing / reading a predetermined field to / from the control register.

[Work]

According to the above-mentioned means, access to the control registers including the status register is performed by the control circuit and the write / read circuit which are hardware, and the microprogram merely determines the write / read operation of the write / read circuit. . Therefore, the processing load of the microprogram is reduced.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of a data processing device according to the present invention. In FIG. 1, the general-purpose register 5 of FIG. 8 is not provided, and instead, the control circuit 7 and the control register 3 for controlling the control register 3 by the control information which is a part of the decoding result of the instruction decoder 1 are used. Writing /
Write circuit SEL1 and read circuit SEL2 that control reading
Is provided. This control circuit 7 is a micro program RO
Operates in parallel with M2. The general-purpose register 5 is not necessary for the writing / reading operation of the control register 3 including the status register 3a, but of course it is necessary for other operations, and is therefore necessary for the data processing device.

The write circuit SEL1 of FIG. 1 is composed of a decoder and a switching gate, as will be described later. For example, as shown in FIG. 2, the decoder uses the internal write bus of the instruction code based on the control information of the instruction 5. Bits 0-4
The switching gates are operated so as to correspond to the bits 0 to 4 of the status register 3a and the bits 6 and 7 of the internal write bus of the instruction code to the bits 14 and 15 of the status register 3a. Readout circuit SEL2 in FIG.
Has the same configuration.

Processing the instructions of FIG. 9 by the apparatus of FIG. 1 reduces the processing load on the microprogram. For example, in the case of the instructions 1 to 4 shown in FIGS. 9 (B) to 9 (E), the control circuit 7 gives an operation target instruction which is conventionally given by a microprogram. This: The microprogram has a reduced number of control bits and does not need to recognize the operation target, thus simplifying the microprogram itself.

Further, in the instruction 5 shown in FIG. 9 (F), the control circuit 7 recognizes that the data is in a compressed format, and the bit position is determined according to the correspondence between the bit position of the status register 3a and the bit position of the instruction 5 (data). Shift the contents of the status register 3a. That is, as shown in FIG. 3, the operation is performed in step (machine cycle) I,
The instruction 5 is decoded by the instruction decoder 1. Step
In II, microprogram ROM2 is microprogram
MI is output, and at the same time, the control circuit 7 decodes the control information which is a part of the decoding result, and further fetches the code of the instruction 5 to the internal write bus. In Step III,
The microprogram MI is executed (EX), that is, the instruction code 5 is moved to the arithmetic unit 5. At this time,
The control circuit 7 operates the write circuit SEL1 to match the bit position according to the correspondence between the bit position of the status register 3a and the bit position of the instruction code 5, and manipulates the contents of the status register 3a. The read operation is also the same. As a result, it is not necessary to convert the data format using the arithmetic unit 4 in the microprogram, and the processing becomes one step with only reading and writing instructions and one execution cycle, which leads to speedup.

Further, when the instruction 6 shown in FIG. 9 (G) is processed by the apparatus shown in FIG. 1, the control register 3 is activated by activating the microprogram only by the instruction type, which leaves the selected bits of the control register 3 to the control circuit. Even if they are different, it is possible to control with a common microprogram MI.

The present invention can be extended to the operation of an external storage device (MSU). That is, when memory access control, operand fetch OF, and operand write OW are performed only by instructing the microprogram, a plurality of types of accessible program resources (MSU, general-purpose register) can be executed by one type of instruction as shown in FIG. ), As described above, as shown in FIG.
Even with one instruction 6, it is necessary to prepare a plurality of microprograms corresponding to the combination of MSU and general-purpose register access. In addition, when the information on the size of the operand is included, the microprogram corresponding to more combinations is required, and the number of microprogram steps is significantly increased. That is, as shown in FIG.
When processing the data read by the operand OF, the microprogram step that started the operand fetch OF
In III, since no data comes in from the MSU, the data cannot be processed, and a separate step for data processing is required. This increases the number of microprogram steps.

Therefore, according to the present invention, as shown in FIG. 6, the operand fetch OF and the operand write OW can be activated not only from the microprogram but also from the control circuit 7. As a result, the type of program resource to be accessed and the size of the operand are input to the tag, the operand fetch OF and the operand write OW are activated, and the microprogram is activated only by the instruction type. Even if the combination changes, the control can be performed by a common microprogram. Also, as shown in FIG. 6, operand fetch
By allowing OF to be activated by the control circuit 7 and delaying the activation of the microprogram so that the operand fetch OF and the microprogram read cycle MI match, the instruction can be executed only in the data processing step. .

FIG. 7 is a circuit diagram showing another embodiment of the data processing device according to the present invention. In addition to the first embodiment, the MSU control circuit (hardware) further performs fetch control and write control to the MSU. Is also possible. That is, in FIG. 7, the control circuit 7 of FIG.
1, 7-2, 7-3, the control circuit 7-1 activates the operand fetch (OF) or the control circuit 7-2, and the control circuit 7-2 activates the control circuit 7-3. The control circuit 7-3 sets the access size (byte or word unit) instruction, the operand write (OW) activation, the control register 3 access mode (target selection), or the control register 3 access mode (bit shift). To do. The operation of these control circuits 7-1, 7-2, 7-3 is performed by the instruction decoder 1
Depends on the control information that is part of the decoding result of.

The microprogram ROM 2 operates in parallel with the operations of the control circuits 7-1, 7-2, 7-3. Micro program RO
The M2 issues only a write / read instruction to the control register 3, and operates either the write decoder as the write SEL1 or the read decoder as the read circuit SEL2. Each of the write decoder and the read decoder selectively operates a buffer (switching gate) corresponding to the output of the control circuit 7-3 and connects it to the write internal bus or the read internal bus. The control register 3 is a register 3-1 as the status register 3a.
It is composed of 3-2, 3-3 and other registers 3-4.

The control circuit 7-1 starts the operand fetch (OF) for the MSU, and the operand write (O)
W) is activated by the control circuit 7-3, but these activations depend on the type of instruction code.
It has a configuration that can also be performed by the M2 microprogram.

Thus, in FIG. 7, the access mode of the control register 3 is designated only by the control circuit (hardware), and the output of the read / write decoder corresponds to the control register 3 (or the control register 3 corresponding to the above-mentioned instructions 1 to 6 processing). Read / write is possible. In addition, the control mode of the status registers 3-1, 3-2, 3-3 is the selector SE.
L3 and SEL4 are provided to support the bit position shift operation of instruction 5. Further, since the control of the operand fetch OF and the operand write OW can also be activated from the control circuit (hardware), the microprogram is not burdened when processing the data read by the instruction 6 or the operand fetch OF. Of course, a combination of activating the operand fetch OF from the control circuit and activating the operand write OW from the microprogram can be easily realized.

The control circuit 7 (7-1, 7-2, 7-3) described above is composed of a combination of logic gates.

〔The invention's effect〕

As described above, according to the present invention, it is possible to reduce the function and the number of steps of the microprogram, and therefore, there is a great effect on labor saving of microprogram development and speedup of data processing. The hardware of the microprogram is generally a ROM as described above, and the size of the ROM is determined by the number of steps and the number of control bits of the microprogram. Therefore, since the ROM requires a very large area on the LSI, the area of the ROM is reduced by using the present invention, and a large reduction effect can be obtained compared with the amount of hardware dedicated to the operation of the control circuit and the control register. Furthermore, miniaturization of the ROM leads to improvement of the access time of the ROM, and in particular, it leads to improvement of the overall processing speed in the device which controls mainly the microprogram.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a data processing device according to the present invention, FIG. 2 is a diagram showing the relationship between the field structure of the status register and the field of one instruction in FIG. 1, and FIG. 1 is a cycle transition diagram showing the operation of FIG. 1, FIG. 4 is a diagram showing correspondence of access species, sizes, and microprograms, FIG. 5 is a cycle transition diagram showing operation of a conventional MSU, and FIG. 6 is related to the present invention. FIG. 7 is a circuit diagram showing another embodiment of the data processing device according to the present invention, FIG. 8 is a circuit diagram showing a conventional data processing device, and FIG. 9 is a status register. FIG. 10 is a diagram showing the field configuration of various instructions, FIG. 10 is a cycle transition diagram showing an example of the operation of FIG. 8, FIG. 11 is a supplementary explanation of FIG. 10, and FIG. 12 is a control register selection bit. Micro program It is a figure which shows correspondence with. 1 ... Instruction decoder, 2 ... Micro program ROM, 3 ... Control register, 3a (3-1, 3-2, 3-3) ... Status register, 4 ... Arithmetic unit (ALU), 5 ... General-purpose register, 7 (7-1, 7-2, 7-3) ... Control circuit (hardware).

Claims (2)

(57) [Claims] 1. A control register (3), an instruction decoder (1) for decoding an instruction, a microprogram storage means (2) for outputting control information according to a decoding result of the instruction decoder (1), According to a control circuit (7) for decoding the control mode of the control register (3) according to the control information which is a part of the decoding result of the instruction decoder (1), and the control mode which is the decoding result of the control circuit (7), Write / read circuits (SEL1, SEL) for writing / reading to / from a predetermined fail in the control register (3) in accordance with a write / read instruction signal from the microprogram storage means (2) to the control register (3).
2) A data processing device comprising: 2. An instruction type, a program resource type, an access type, as a part of the decoding result of the instruction decoder (1),
Alternatively, the data processing device according to claim 1, wherein the data processing device is configured by an access size, and the control circuit (7) also performs writing / reading to / from an external storage device in addition to the control of the control register (3).