JP2543552B2 - Data transfer system having transfer identification circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a data transfer system having a transfer identification circuit. The system according to the present invention can be applied to a general computer system including a central portion in a central position and an input / output device (I / O device) in a remote position.

BACKGROUND ART Generally, there are two kinds of data transfer for a channel interface of a computer, namely, interlock data transfer, and 5 to 10 m between an input / output channel device and an input / output device (I / O device). A maximum transfer rate of 1.5 MB per second is achieved for distances of, and Data Streaming Feature (DSF) data transfers for distances of approximately 120 m between I / O channel devices and I / O devices. A maximum transfer rate of 3 megabytes per second is achieved. There is no provision by the computer manufacturer on which of these two types of data transfer is used for signals or operations in the operations for signals in the channel interface.

Either interlocked data transfer or DSF data transfer is required to achieve satisfactory data transfer when an arrangement is used to extend the distance between the I / O channel device and the I / O device. It is necessary to identify whether or not data transfer is being performed.

In general, the interface operation of the I / O channel device is the same for any of these data transfers, which can be either an interlock data transfer or a DSF transfer.
It is satisfactorily performed by the I / O channel device regardless of whether the data transfer is being performed by the data transfer.

However, if the channel interface distance is increased by the insertion of transmission lines connected in series, the distance extension device must be provided within the channel interface without disturbing the normal operation of the channel interface. .

Therefore, in order to match the operation of the distance extension device with that of the I / O device, it is necessary to identify whether the data transfer is performed by interlock data transfer or DSF data transfer. To do.

DISCLOSURE OF THE INVENTION One object of the present invention is to provide an improved data transfer system having a transfer format identification circuit, which can identify interlock data transfer or DSF data transfer without adversely affecting the operation of a channel interface. To provide what you can.

In the present invention, as a basic form, when data is transferred using a computer, an input / output channel device, and an input / output device, the connection distance of the channel interface is extended by a serial transmission line, and an input / output channel device for a computer is provided. A data transfer system having a data transfer identification circuit used for data transfer between input / output devices, wherein the data transfer identification circuit is a data streaming feature (DSF) data transfer detection means and is input from the input / output device. Data streaming by sending one output as a result of detecting that the time between the rising edge and the falling edge of the first tag signal transmitted to the output channel device is within a predetermined time length. What detects interfering data transfer, interlock data transfer A detecting means for detecting that the falling edge of the first tag signal transmitted from the input / output device to the input / output channel device is not detected within a predetermined time after the rising edge of the first tag signal. One that detects interlock data transfer by sending one output as a result of detection, and an output of the data streaming feature transfer detection means or an output of the interlock data transfer detection means is stored. Storage means, wherein the transfer identification is edge detection means, and the falling edge of the tag signal after the rising edge of the tag signal has passed in response to the tag signal supplied to the edge detection means. Detecting edges, the edge detecting means having a rising edge detector, a falling edge detector, a storage element, and a logic gate circuit. A timing means for counting a predetermined time in response to the output of the edge detection means, and an identification storage means for responding to the output of the timing means, which represents one form of data transfer. A data transfer system, comprising: an output or one operable to deliver an output that represents another form of data transfer.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, FIG. 1A is a diagram showing a data transfer system for a computer to which the system according to the present invention is applied, and FIG. 1B is a computer side and I / O in the data transfer system of FIG. 1A. FIG. 2 is a diagram showing the exchange of tag signals through signal lines and data through a data bus between the device sides. FIG. 2 shows the I / O device side and the input / output channel device by interlock data transfer. FIG. 3 is a diagram showing a signal exchange process between the I / O device side and the I / O channel device side by DSF data transfer, and FIG. FIG. 5 is a diagram showing a data transfer system for a computer according to an embodiment of the invention to which a transfer identification circuit is applied. FIG. 5 is a data transfer system for a computer according to the embodiment of the present invention shown in FIG. Typical transfer identification times in the system FIG. 6, FIG. 6 and FIG. 7 are diagrams showing signal waveforms in the transfer identification circuit shown in FIG. 5, and FIG. 8 is a block diagram of a data transfer system for a computer according to an embodiment of the present invention. FIG. 9 is a diagram showing the operation of the transfer identification circuit from one viewpoint, and FIG. 9 is a data transfer system for a computer according to another embodiment of the present invention, in which the transfer identification circuit is applied. FIG. 10 is a diagram showing the configuration of the first distance extension device used in the data transfer system of FIG. 9, and FIG. 11 is a diagram of FIG. The figure which shows the structure of the 2nd distance extension apparatus used for a data transfer system, FIG. 12 is the figure which shows the data transfer system by other Example of this invention, FIG. 13 is an example of the structure of the rising edge detection apparatus. Fig. 14 shows the structure of the fall detection device. FIG. 15 and FIG. 16 are diagrams showing an example of the configuration of a tag transmission circuit, and FIG. 17 is a diagram showing an example of the configuration of an information receiving circuit, a combining circuit, and a frame transmitting circuit. FIG. 18 is a diagram showing an example of a pattern of a signal frame for transmission, and FIG. 19 is a diagram showing an example of configurations of a frame receiving circuit and a separation circuit.

BEST MODE FOR CARRYING OUT THE INVENTION Prior to describing the preferred embodiment of the present invention, a conventional data transfer system is described with reference to FIGS. 1A, 1B, 2 and 3. The operation of the system of FIG. 1A is illustrated by the waveform diagram for interlock data of FIG. 2 and the waveform diagram for DSF data transfer of FIG.

In the system shown in FIG. 1A, data transfer is performed by computer 5.
Between the input / output channel device 6 and the input / output terminal device (I / O device) connected to the. As shown in Fig. 1B, the service out signal (SV OUT), data out signal (DT OUT), and bus out signal (BUS OUT) are transferred from the computer side to the input / output terminal device side, and the service in signal (SV IN), data-in signal (DT IN), and bus-in signal (BUS IN) are transferred from the input / output terminal device side to the computer side.

The write operation by interlock data transfer is illustrated in FIG. The tag signal SVi sent from the I / O device and transferred through the transfer line is detected by the input / output channel device. When the I / O channel device receives this SVi, it sends the signal SVo together with 1-byte data through the bus line. When the I / O device detects this SVo from the I / O channel device and receives the data transmitted from the I / O channel device, the I / O device terminates the signal SVi. When the end of the signal SVi is detected by the input / output terminal device, the input / output terminal device ends the signal SVo.
In this way, the transfer of 1-byte data is completed. Then, this 1-byte data transfer is repeated.

The operation of data transfer from the I / O device to the I / O channel device is performed in a similar manner. That is, the signal SVi is I
When transmitted from the / O device to the I / O channel device, 1 byte of data is transmitted.

In FIG. 3, the operation by DSF data transfer is illustrated. The tag signal SVi is sent from the I / O device to request data supply. The I / O device keeps the SVi on for a predetermined time, and terminates the SVi without waiting for the output of the SVo from the input / output channel device. The predetermined time of this SVi on state is longer than about 270 ns. SVi off state for a predetermined time,
For example, after a minimum of 270 ns, the signal SVi is sent again. After the ON state of SVi elapses for the same predetermined time as described above, SVi ends. This operational sequence is then repeated.

The operation of the I / O channel device is similar to that of the interlock data transfer system. When the I / O channel device receives SVi from the I / O device, it sends the signal SVo and data to the I / O device. The end of SVi is detected after about 270 ns. When the end of this SVi is detected, the signal SVo ends. This operational sequence is then repeated.

The input / output device does not terminate the transmission of SVi by detecting SVo, but terminates it regardless of the detection of SVo.
In a data streaming system, the signal
When only SVi is used, no data transfer takes place during the off state of the signal SVi. Therefore, in order to increase the efficiency of data transfer, the data-in signal DTi transferred from the input / output terminal device side to the computer side is used in addition to the signal SVi.

A data transfer system for a computer to which the transfer identification circuit is applied is shown in FIG. The structure of a typical transfer identification circuit in this data transfer system is shown in FIG.

The system shown in FIG. 4 includes a computer 5, an input / output channel device 6, input / output terminal devices (I / O devices) 71, 72, 73 ..., an additional device 81 for distance extension on the input / output channel device side, and an I / O device. It is configured by an additional device 82 for extending the distance on the O device side. The transfer identification circuit 1 is provided in the addition device 82.

The transfer identification circuit 1 shown in FIG. 5 includes an edge detection unit 11 having a rising edge detector 111 and a falling edge detector 1.
12, an OR gate 113, a flip-flop circuit 114, and an AND gate 115, a counter 12, an initial value supply unit 13, a flip-flop circuit 14, and an OR gate 15.

The rising edge detector 111 receives the tag signal such as SVi and sends the output signal to the input terminal of the flip-flop circuit 114. The rising edge detector 112 receives the tag signal such as SVi and sends the output signal to the OR gate 113 and the AND gate 115. The output of the OR gate 113 is supplied to the reset input terminal of the flip-flop circuit 14, and the output of the flip-flop circuit 114 is supplied to the AND gate 115.

The counter 12 receives the output of the flip-flop circuit 114 through the enable input terminal and sends the output signal to the reset input terminal of the flip-flop circuit 14 and the OR gate 15. The output of the AND gate 115 is supplied to the set input terminal of the flip-flop circuit 14 and the AND gate 15. The Q output terminal of flip-flop circuit 14 sends out a signal indicating a DSF data transfer. The (Q-bar) output terminal of the flip-flop circuit 14 sends out a signal indicating the interlock data transfer. The OR gate 15 sends out a signal indicating the end of identification.

The operation of the transfer identification circuit 1 in FIG. 5 in the case of interlock data transfer will be described with reference to FIG. The tag signal SVi is supplied to the rising edge detector 111 and the falling edge detector 112 (FIG. 6 (1)). The output signal of the rising edge detector 111 is supplied to the flip-flop circuit 114 (FIG. 6 (2)). The potential of the output of the falling edge detector 112 is maintained at the low level (Fig. 6 (3)). The enable input signal is still supplied to the counter 12 (Fig. 6 (4)). The potential of the output signal of the AND gate 115 is maintained at the low level (Fig. 6 (5)). After a relatively long time, for example, 2 μS, a carry signal representing overflow of the counter is sent from the counter 12 (FIG. 6 (6)). The flip-flop circuits 114 and 14 initialize the counter 12 which is reset by this carry signal. When the flip-flop circuit 14 is reset, a high level signal is sent from the output terminal of the flip-flop circuit 14 (FIG. 6 (7)). This high level signal from the output terminal represents the interlock data system.

The operation of the transfer identification circuit 1 of FIG. 5 in the case of DSF data transfer will be described with reference to FIG. The tag signal SVi is supplied to the rising edge detector 111 and the falling edge detector 112 ((1) in FIG. 7). The output of the rising edge detector 111 is supplied to the set input terminal of the flip-flop circuit 114 (Fig. 7 (2)). The output of the falling edge detector 112 is supplied to the reset input terminal of the flip-flop circuit 114 and the AND gate 115 (FIG. 7 (3)).
The enable signal is still supplied to the counter 12 from the rising edge detection pulse to the falling edge detection pulse. The counter 12 performs counting from the initial value previously supplied from the initial value supply unit 13. When the falling edge detector 112 sends a falling edge detection pulse (FIG. 7 (3)),
The high-level signal from the AND gate 115 is supplied to the set input terminal of the flip-flop circuit 14 ((5) in FIG. 7) to cause the Q output terminal of the flip-flop circuit 14 to output the high-level signal. A high level signal from the Q output terminal represents DSF data transfer.

The flip-flop circuit 114 is the flip-flop circuit 114.
Falling edge detector 11 supplied to the reset input terminal of
Reset by output signal of 2, thereby counter 1
2 ends counting and returns to the initial value.

The initial value of the counter 12 is selected by the initial value supply unit 13. The initial value of the counter is such that the overflow of the count value occurs when the counting operation is completed during the time corresponding to the predetermined time.

According to one aspect, the data transfer identification circuit used in the present invention can be represented by the diagram shown in FIG. The data transfer identification circuit shown in FIG. 8 is composed of a DSF data transfer detection unit, an interlock data transfer detection unit and a storage unit. The DSF data transfer unit receives the tag signal and the output of the interlock data transfer detection unit.

The interlock data transfer detector receives the output of the DSF data transfer detector. The storage unit receives the outputs of the DSF data transfer detection unit and the interlock data transfer detection unit, and
F Send either output for data transfer or output for interlock data transfer.

According to the viewpoint shown in FIG. 8, the data transfer identification circuit used for data transfer between the I / O channel device for the computer and the I / O device is the DSF data transfer detection unit, and the I / O device inputs and outputs. Detects DSF data transfer by sending one output as a result of detecting that the time length between the rising edge and falling edge of the first tag signal transmitted to the channel device is within a predetermined time The interlock data transfer detection unit does not detect the falling edge of the first tag signal transmitted from the input / output device to the input / output channel device within a predetermined time from the rising edge of the first tag signal. Detecting interlock data transfer by sending one output as a result of detection; and output or in- put of DSF data transfer detector Storage unit for storing the output of the over lock data transfer detection portion, the constructed.

A data transfer system for a computer as another embodiment of the present invention is shown in FIG. The configuration of the first distance extension device used in the system of FIG. 9 is shown in FIG. 10, and the configuration of the second distance extension device used in the system of FIG. 9 is shown in FIG.

The system shown in FIG. 9 includes a computer 5, an input / output channel device 6, a first distance extension device 2, a transmission line 3, a second distance extension device, and input / output devices 71, 72, 73, ... . The parallel signal from the I / O channel device is the first
Of the distance extension device 2 is converted into a serial signal having a predetermined format, and the converted serial signal is transmitted to the second distance extension device 4 through the transmission line 3 and
The signal transmitted in the distance extension device is converted back into the original parallel signal, and the original parallel signal is converted into the input / output device 71, 7
Supplied to 2,73, ... Data transmission from the input / output devices 71, 72, 73, ... To the computer 5 is performed in the same manner.

In the system shown in FIG. 9, the inter-channel distance extension device is used to connect an input / output device at a remote location from the host computer. A first distance extension device and a second distance extension device are arranged to extend the distance between the channels.

As shown in FIG. 10, the first distance extension device 2 is
Channel interface input / output unit 21, transfer reception / switching unit 23, sequence conversion unit 22, and CPU2
Composed of 4. The channel interface input / output unit 21 includes a tag reception circuit 211, a tag transmission circuit 212, and a transfer data input / output control unit 213. The transfer reception / switching unit 23 includes an information reception circuit 232 and a separation circuit. The sequence conversion unit 22 is a frame receiving circuit
221, a frame transmission circuit 222, a data block transfer control circuit 223, and a data buffer 224 are included.

As shown in FIG. 11, the second distance extension device 4 is
The sequence conversion unit 42, the transfer determination unit 43, the channel interface input / output unit 41, and the CPU 44. The sequence conversion unit 42 includes a frame transmission circuit 421, a frame reception circuit 422, a data block transfer control circuit 423, and a data buffer 424. The transfer determining unit 43 includes the transfer identifying unit 1, the combining circuit 431, the information receiving circuit 432, and the tag transmission circuit 433. The channel interface input / output unit 41 includes a tag receiving circuit 411 and a transfer data input / output control circuit 412.

The operation of the apparatus of Figures 10 and 11 is described below. In the second distance extension device 4, data transfer is performed after selecting the input / output device. CPU to tag receiving circuit 411
Although the start of data transfer is notified by 44, the CPU monitors the state of signals during the process. Based on the monitoring of the signal status by the CPU, the transfer identification unit 1 determines the tag transmission circuit 433.
When the output of the tag transmission circuit should be shut off by controlling the switch 433a of the above, the connection between the tag reception circuit 411 and the tag transmission circuit 433 is switched off.

The rising edge of the signal TAGi, which is first supplied from the input / output device to the tag receiving circuit 411 during the data transfer, is detected by the transfer identifying unit 1. But switch
Since 433a is in the off state, signal TA corresponding to signal TAGi
Go is not transmitted from the tag transmission circuit 433.

In this state, when the data transfer of the input / output device is performed in the interlock data transfer, the signal TAGo is not sent, so TAGi remains rising and the falling cannot be detected. This is because the interlock transfer is a transfer in which TAGi is turned off by detecting that TAGO for TGAi is responded. However, in the DSF data transfer, when the predetermined time elapses, the SV from the I / O channel device is
The input / output device independently disconnects without waiting for the o to be sent so that the falling edge of the signal can be detected.

The switch 433a is in the off state while the detection operation is in progress. When the detection operation is completed, the switch 433a enables signal transmission between the turned-on input / output device and the second distance extension device 4.

When the transfer identification unit 1 detects that the current transfer is a DSF data transfer, a signal is generated in a predetermined format in the information reception circuit 432, but the information reception circuit generates information regarding the transfer, and this information and Data buffer 424
Signal synthesis for parallel data from
Done in. The output of the combining circuit 431 is supplied to the frame transmission circuit 421, the signal is converted into a serial signal in the frame transmission circuit, and the serial signal is transmitted to the first distance extension device.

In the first distance extension device 2, the received signal is converted into a parallel signal in the frame reception circuit 221, and the DSF data transfer information is converted into the parallel signal in the separation circuit.
Separated from 21 outputs. The separated DSF data transfer detection information is detected by the information reception circuit 232, and the tag reception circuit 411 and the transmission circuit 433 are switched to the tag transmission / reception circuit for DSF data transfer by a switch (not shown).
It should be noted that this switch does not occur when the information indicates that it is an interlocked data transfer.

A data transfer system for a computer according to still another embodiment of the present invention is shown in FIG. The system of FIG. 12 operates at a timing that is delayed from the normal timing of the first tag response circuit 81 and the normal timing of the tag signal TAGi from the input / output circuit that operates at the normal timing of the tag signal TAGi from the input / output device. Second tag response circuit 82, selection circuit
83, a counter circuit 85 for control, and the data transfer identification unit 1 are included. The data transfer identification unit 1 in the system shown in FIG. 12 is basically the same as the device shown in FIG.

One of the first tag response circuit 81 and the second tag response circuit 82 is selected by the selection circuit 83, and one of the output of the first tag response circuit 81 and the output of the second tag response circuit 82 is selected by the selection circuit 83.
Is supplied as a tag signal TAGo from the input / output device side 7.

The control counter circuit 85 periodically activates the selection circuit 83 and the transfer identification unit 1. The counter circuit 85 is, for example, a counter for measuring time, and counts time of 1 ms, for example. In the counter circuit 85, for example,
One count is performed for every 100 tag signals SV ₁ . After identifying the transfer method at the start of transfer, assuming that there is a change in the transfer method, the TAG signal is counted as a means to measure this interval for the purpose of repeating the identification at appropriate intervals during transfer. ing. That is, for example, it is aimed to perform detection about once every 100 times.

The operation of the system of Figure 12 is described below. It is assumed that the input / output device selection and the data transfer regarding command transmission are completed as a prior process.

First, the selected terminal device sets SVi as a tag signal or the potential of the data-in DTi transferred from the input / output terminal to the computer side to a high level, and according to the tag signal TAGi, the first tag response circuit 81 and the second tag response circuit 81 Only one of the tag response circuits 82 is activated.

That is, when the control counter circuit 85 sends a low-level signal as an off signal, the selection circuit 83 operates the first tag response circuit 81, and the tag signal TAGi is sent to the input / output device as the response tag signal TAGo. Supplied without delay. On the contrary, when the control counter 85 sends out a high level signal as an ON signal, the selection circuit 83 operates the second tag response circuit 82 and the transfer identification unit 1.

In this way, the OFF signal from the control counter circuit 85 is operated as the selection instruction signal from the first tag response circuit 81 to the selection circuit 83, and the ON signal from the control counter circuit 85 is changed to the second signal. The tag response circuit 82 is operated as a selection instruction signal to the selection circuit 83 and an operation instruction signal to the transfer identification circuit 1.

The transfer identifying unit 1 receives the operation instruction signal from the control counter circuit 85 and identifies between the DSF data transfer and the interlock data transfer based on the tag signal TAGi from the input / output device. During this identification operation, the response to the tag signal TAGi in the second tag response circuit is delayed.

When the identification between the DSF data transfer and the interlock data transfer is completed, the transfer identification unit 1 determines the DSF as the identification result.
Either the data transfer display signal or the interlock data transfer display signal is transmitted, and the identification end signal is supplied to the second tag response circuit 82. As a result, the second tag response circuit 82 supplies the response signal TAGo of the tag signal TAGi to the input / output device.
In other words, the tag response is delayed.

When the operation is completed, the transfer identification circuit 1 supplies an identification end signal to the second tag response circuit 82, and as a result, the second tag response circuit 82 responds to the tag signal TAGi from the input / output device, The response signal TAGo is supplied to the input / output device through the selection circuit 83.

In this way, the data transfer from the input / output device side to the second distance extension device is periodically identified.

An example of the configuration of the rising edge detector 111 in the system of FIG. 5 is shown in FIG. 13, an example of the configuration of the falling edge detector 112 in the system of FIG. 5 is shown in FIG. 14, and FIG. FIG. 15 shows an example of the structure of the tag transmission circuit 212 in the system of FIG. 11, and FIG. 16 shows an example of the structure of the tag transmission circuit in the system of FIG. FIG. 17 shows an example of the configuration of the information receiving circuit, the synthesizing circuit, and the frame transmitting circuit in the system of FIG. An example of a signal frame pattern for transmission of the circuit of FIG. 17 is shown in FIG. 18, and an example of the configuration of the frame receiving circuit and the separation circuit is shown in FIG.

The rising edge detector shown in FIG. 13 is composed of first and second flip-flop circuits and an AND gate. The first flip-flop circuit is an input signal,
For example, it receives SVi and clock signals. The second flip-flop circuit receives the Q output of the first flip-flop circuit and the flock signal. The AND gate receives the Q output signal of the first flip-flop circuit and the output signal of the second flip-flop circuit. The AND gate sends a rising edge display signal.

The falling edge detector shown in FIG. 14 is composed of first and second flip-flop circuits and an AND gate. The first flip-flop circuit is an input signal,
For example, SVi and a clock signal are received. The second flip-flop circuit is the Q of the first flip-flop circuit.
Receive output and clock signals. The AND gate receives the output of the first flip-flop circuit and the Q output of the second flip-flop circuit. The AND gate sends a falling edge display signal.

The tag transmission circuit shown in FIG. 15 is composed of first to eighth gates, a flip-flop circuit, a pulse width securing circuit, and a driver. In the operation of the circuit of FIG. 15, first, an interlock data transfer display signal is supplied from the information receiving circuit. The first and second gates check this condition. If the check result is acceptable, the TAGi set circuit composed of the third to fifth gates and the TAGi reset circuit composed of the sixth to eighth gates are enabled. In the case of interlock data transfer, the set condition is established by the third to fifth gates and the reset condition is established by the sixth to sixth gates. In the case of DSF data transfer, the set condition is established by the fourth and fifth gates, and the reset condition is established by the seventh and eighth gates. In the case of DSF data transfer, the pulse width securing circuit secures the on / off time of the pulse, and when the necessity of securing the on / off time ends, the device output is turned on.

The tag transmission circuit shown in FIG. 16 is composed of a flip-flop circuit for requesting TAGO output, a flip-flop circuit for holding TAGO, first to fourth gates, a pulse width securing circuit, and a driver. In the operation of the circuit of FIG. 16, the flip-flop circuit for requesting the TAGo output is set by the received TAGI. When the DSF detection operation is completed, the output request signal is sent out from the first gate.
When the stop condition is absent and the allowed output signal is received for timing establishment, the fourth gate is turned on, which turns on the second gate. Therefore, the flip-flop circuit for holding TAGo is set, and thus the output signal is sent from the device. TAGo
The pulse width of the holding flip-flop circuit is secured by the pulse width securing circuit. When the input TAGi is turned off, the TAGo holding flip-flop circuit is reset by the function of the third gate.

As shown in FIG. 17, the frame transmission circuit includes a frame data request circuit, a parallel-serial conversion circuit, a frame period and frame formation circuit, and a driver, the synthesis circuit includes a register, and the information reception circuit includes a flip-flop. Circuit.

The signal frame for transmission having the pattern shown in FIG. 18 is serially transmitted between the first distance extension device and the second distance extension device. Specific bits in the control section in the frame are defined as DSF transfer information.

In the operation of the circuit shown in FIG. 17, detection of DSF data transfer is transmitted to the flip-flop circuit in the information receiving circuit and stored as information. The frame transmission circuit is then activated by the CPU to start forming the frame structure of the signal and continue the transmission operation until receiving an end instruction from the CPU. The data from the data buffer is registered in the register, and a frame is formed in the synthesis circuit based on the signal from the frame data request circuit, and the DSF
The output of the flip-flop circuit for holding the transfer information is set to the bit position of the DSF transfer information in the frame. In the frame transfer circuit, the frame data formed as described above is applied to the parallel-to-serial circuit, and the output of the parallel-to-serial circuit is sent to the transmission line, while the frame period of the frame data is maintained. ing. The above process is then repeated.

As shown in FIG. 19, the frame receiving circuit includes a receiver, a clock period circuit, a frame period circuit, and a series-parallel circuit, and the separation circuit includes a register.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (31) Priority claim number Japanese Patent Application No. Sho 62-107949 (32) Priority date Sho 62 (1987) May 2 (33) Priority claim country Japan (JP) Judgment No. 15748 (72) Hideo Suzuki Hideo Suzuki, Kanagawa Prefecture Midori-ku, Yokohama-shi, Edaminami 1-2-20 room, Room 402 (56) Reference JP-A-57-197629 (JP, A)

Claims (12)

(57) [Claims] 1. When a computer, an input / output channel device, and a data transfer using the input / output device, the connection distance of the channel interface is extended by a serial transmission line, and the input / output channel device for the computer and the input device are What is claimed is: 1. A data transfer system having a data transfer identification circuit used for data transfer between devices, wherein the data transfer identification circuit is a data streaming feature (DSF) data transfer detection means, and from the input / output device to the input / output channel device. By sending one output as a result of detecting that the time between the rising and falling edges of the transmitted first tag signal is within a predetermined time length,
Detecting data streaming feature data transfer, interlock data transfer detecting means, wherein the falling edge of the first tag signal transmitted from the input / output device to the input / output channel device is the first tag signal Detecting an interlocked data transfer by sending one output as a result of detecting that it is not detected within a predetermined time length after the rising edge of the data streaming feature transfer. Storage means for storing the output of the detection means or the output of the interlock data transfer detection means, wherein the transfer identification is edge detection means and is responsive to a tag signal supplied to the edge detection means. Operative to detect the falling edge of the tag signal after the rising edge of the tag signal has passed, The edge detecting means has a rising edge detector, a falling edge detector, a storage element, and a logic gate circuit, timing means for counting a predetermined time in response to the output of the edge detecting means, and , An identification storage means responsive to the output of the timing means to operate to deliver an output representative of one form of data transfer or an output representative of another form of data transfer, A data transfer system characterized in that 2. The system according to claim 1, wherein the storage element in the edge detecting means is a flip-flop circuit. 3. The set input terminal of the flip-flop circuit receives the output of the rising edge detector, and the reset input terminal of the flip-flop circuit receives the output of the falling edge detector through an OR gate. The system according to item 2. 4. The system according to claim 2, wherein the output of the flip-flop circuit is supplied to the enable input terminal of the timing means. 5. The system of claim 1 wherein said timing means receives an initial value from an initial value supply means. 6. The system according to claim 1, wherein said identification storage means is a flip-flop circuit. 7. A set input terminal of the flip-flop circuit, an AND gate of the edge detecting means receives an output of a storage element and an output of the falling edge detector of the edge detecting means. The system described. 8. The system of claim 6 wherein the reset input terminal of the flip-flop circuit receives the output of the timing means. 9. A computer, an input / output channel device, and a data transfer using the input / output device, the connection distance of a channel interface is extended by a serial transmission line, and the input / output channel device and the input / output device for a computer are provided. What is claimed is: 1. A data transfer system having a data transfer identification circuit used for data transfer between devices, wherein the data transfer identification circuit is a data streaming feature (DSF) data transfer detection means, and from the input / output device to the input / output channel device. By sending one output as a result of detecting that the time between the rising and falling edges of the transmitted first tag signal is within a predetermined time length,
Detecting data streaming feature data transfer, interlock data transfer detecting means, wherein the falling edge of the first tag signal transmitted from the input / output device to the input / output channel device is the first tag signal Detecting an interlocked data transfer by sending one output as a result of detecting that it is not detected within a predetermined time length after the rising edge of the data streaming feature transfer. A data transfer system comprising: storage means for storing the output of the detection means or the output of the interlock data transfer detection means. 10. A first for receiving a tag from the input / output device.
Of the tag response circuit, the tag from the input / output device, the second tag response circuit that receives the identification end signal from the data transfer identification circuit, the counter circuit for controlling the transmission of the control output, and the selection circuit. The outputs of the first and second tag response circuits are received, and as a selection instruction, the first output is input to the input / output device according to the control output of the counter circuit.
For outputting the output of the tag response circuit or the output of the second tag response circuit, for outputting the data of the data streaming feature or for transferring the data of the interlock from the data transfer identification circuit. 10. The system according to claim 9, wherein the output of the output is controlled by the control output of the counter circuit as an operation instruction. 11. A data transfer system using a channel interface distance extension device having a transfer identification circuit for identifying a data transfer between an input / output channel device for a computer and the input / output device. The apparatus further comprises first and second distance extending means arranged between the output channel device and the input / output device, wherein the first and second distance extending means are sequence converting means and are first according to the channel interface sequence. Alternatively, a signal transmitted from the input / output channel device or the input / output device through the second channel interface input / output circuit is converted into a signal having a predetermined format, and the converted signal is serially transmitted, or a predetermined signal is transmitted. The received signal with the format is inverse transformed and the resulting signal is Is transmitted to the input / output channel device or the input / output device according to the interface interface sequence, and the second distance extension means is the transfer decision means, and uses the tag first sent from the input / output device during the data transfer period. Thereby determining whether the I / O device data transfer in question is an interlocked data transfer but a data streaming feature data transfer,
The first distance extension means is transfer reception and switching means, receives the determination result of the transfer determination means, and controls the operation of the first channel input / output circuit by interlock data transfer and data streaming. A data transfer system comprising: a switch for switching between feature data transfers. 12. A first device for receiving a tag from the input / output device.
Of the tag response circuit, the tag from the input / output device, the second tag response circuit that receives the identification end signal from the data transfer identification circuit, the counter circuit for controlling the transmission of the control output, and the selection circuit. The outputs of the first and second tag response circuits are received, and as a selection instruction, the first output is input to the input / output device according to the control output of the counter circuit.
For outputting the output of the tag response circuit or the output of the second tag response circuit, for outputting the data of the data streaming feature or for transferring the data of the interlock from the data transfer identification circuit. 12. The system according to claim 11, wherein the output of the output is controlled by a control output of the counter circuit as an operation instruction.