JP2540936B2 - Call admission control device - Google Patents

Description

The present invention relates to a packet switch that sends a predetermined packet for each outgoing line, and more particularly to a call admission control device for a high-speed packet switch.

[Conventional technology]

Conventionally, this type of packet switch is a device that can send a predetermined packet for each outgoing line, and is mainly 10 [k bits /
Seconds] or less is intended for the transfer of low speed data.
Therefore, in this packet switch, processing by software control is performed for each packet. This is realized by performing routing / congestion control of the line or the network on a packet-by-packet basis by software control.

By the way, recently, an asynchronous transfer system (ATM) that comprehensively handles communication calls of various transmission speeds including circuit switching.
High-speed packet transmission method called Transfer Mode) is CCI
It is proposed by TT (International Telegraph and Telephone Advisory Committee).

In such an ATM system, transmission at a high speed of, for example, 156 [Mbit / sec] is considered, and a fixed packet length of 34 to 128 bytes is planned. This means that one packet must be processed in 2-3 microseconds to be transmitted.
Such high-speed packet exchange makes it very difficult to perform software processing in packet units as in the conventional case. Therefore, in order to realize packet-based switching operation at high speed, processing by hardware is considered.

[Problems to be Solved by the Invention]

By the way, an effective mechanism for determining whether or not one switching node may receive a new call when the packet-based switching is realized by hardware as described above has not been conventionally known.

Therefore, considering what can be a criterion for judging whether or not to accept a new call, there are two, a packet delay time in the node and a packet discard rate in the node.

If the packet delay time is 156 [Mbit / sec], the average latency in the node is 10 times the packet length 2 to 7 [microsec], which is 20 to 70 [microsec]. Even so, it is known that it does not become a communication obstacle. However, the influence of the discard rate of the term becomes a big problem in communication.

Conventionally, in packet switching, normally when all calls are accepted and it is determined that a node or outgoing line is congested when processing data packets in it,
It was possible to limit the acceptance of subsequent data packets. However, in the ATM method, the processing in packet units after a call is once connected is processed by hardware, and congestion is not controlled in principle. Therefore, congestion control must be performed depending on whether or not the call is accepted at the call level. At this time, the above-mentioned packet discard rate can be a criterion for congestion determination.

By the way, it is considered that the target packet discard rate at the node is about 10 ⁻¹⁰ in the above-described packet switch performing high-speed processing. Considering the value of this discard rate at 156 [M bits / sec], it occurs about once every several hours, which causes a problem in observation accuracy. In addition, since this packet discard rate varies greatly depending on the arrival characteristics of packet traffic and fluctuations in traffic volume, there is a problem that 10 ^-10 cannot be realized by observing only the packet discard rate.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a call admission control device capable of keeping a packet discard rate below a certain level.

[Means for solving the problem]

In order to achieve the above-mentioned object, the call admission control device of the present invention has a transmission buffer capable of accumulating a predetermined number of packets to be transmitted to an output line, and a predetermined number or more of packets accumulated in this transmission buffer. At this time, a storage amount detecting means for outputting a predetermined detection signal, a first counter for counting timing pulses of a constant cycle only during a period during which the detection signal is output from the storage amount detecting means, and a timing pulse of a constant cycle are counted. And a second counter that initializes these counters, reads the count value of each counter when an arbitrary time has elapsed after that, and divides the count value of the first counter by the count value of the second counter. A count value acquisition determining means for repeatedly determining whether or not it is equal to or greater than a predetermined reference value, and this count value acquisition determination step determines that the divided value exceeds the reference value. When rejected, the new call connection to the outgoing line that occurs after that is rejected, and when the count value determination means determines that the divided value is below the reference value, a new call connection to the outgoing line is established. It is characterized by comprising a control circuit for restarting.

The call admission control device of the present invention observes the ratio of packets in the packet sending buffer to a certain value or more, and permits or disallows the connection of the outgoing line based on the value to set the packet discard rate as a target. It can be set to:

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 and 2 are provided for explaining the embodiment of the present invention.

FIG. 1 is a block diagram showing an embodiment of the call admission control device of the present invention. FIG. 2 is a timing chart shown for explaining the operation of the embodiment.

The call admission control device 1 shown in FIG. 1 is based on fixed length packets. The call admission control device 1 includes a transmission buffer 2 that stores a packet PKT, a parallel-serial conversion circuit 3 that converts a signal from the transmission buffer 2 into a serial signal, and a notification signal.
A logical product circuit 4 that performs a logical operation to obtain a logical product of Bk and a timing (clock) pulse Cp, a first counter 5 that advances by a signal from the logical product circuit 4, and a clock pulse Cp
The second counter 6 which is stepped by and the control circuit 7 which controls whether the connection of the outgoing line is permitted or not.

The sending buffer 2 can store a predetermined number of packets for each outgoing line. That is, the output buffer 2 is B ₁
It is for accumulating packets of up to B _m , and for accumulating packets from the switch network of the system to the outgoing line i although not shown. Further, the sending buffer 2 has a function of outputting a notification signal bk to the outside when a packet is accumulated at a fixed packet position (Bk) from its head (B ₁ ). Therefore, the notification signal bk is output when “k” or more packets are accumulated in the transmission buffer 2.

The parallel-serial conversion circuit 3 uses the buffer B _{1 of the} sending buffer 2.
It converts the packet data from the to parallel to serial and sends it to the outgoing line.

The AND circuit 4 is for performing a logical operation of the notification signal bk and the clock pulse Cp having a constant cycle. The output signal from the AND circuit 4 is supplied to the first counter 5. The first counter 5 is adapted to step by this output signal.

The second counter 6 is adapted to step by a clock pulse Cp having a constant cycle. The first counter 5
Then, the second counter 6 is simultaneously initialized to 0 by the reset signal R from the control circuit 7.

The control circuit 7 may be composed of a computer or the like. The control circuit 7 controls the count value lk of the counter 5 and the second counter 6
When the calculated value (A = lk / lp) obtained from the count value lp and the count value lp at regular time intervals (1 second) exceeds the preset reference value Aup A new call connection to the outgoing line is rejected and the calculated value (A = lk / lp)
When it falls below the reference value Adw, it is possible to restart a new call connection to the corresponding outgoing line.

 The operation of the embodiment thus configured will be described.

In FIG. 2, Cp is a clock pulse, bk is a notification signal from the sending buffer 2, lp is a count value of the second counter 6,
lk is a count value of the first counter 5, and R is a reset signal.

The control circuit 7 controls the count value lk of the first counter 5 at time t ₀ .
And the count value lp of the second counter 6 are read. At this time, the count value lp of the second counter 6 is x + 8, and the count value lk of the first counter 5 is y + 3. The control circuit 7 sends the reset signal R to the first counter 5 and the second counter 6 at time t ₁ immediately thereafter. Time t ₀ and time
The time t ₁ is not synchronized and is determined by the processing (software processing) of the control circuit 7. That is, the control circuit 7
Repeats resetting the first and second counters 5 and 6 at the same time, reading the count value of each counter when approximately 1 second has elapsed, and immediately thereafter resetting again. One cycle of the clock pulse Cp is set to be equal to the time length of sending one packet to the outgoing line. Here, 36
[Bytes / packets], transmission rate is 156 [Mbits /
Second], one cycle is about 1.85 [microseconds]. Therefore, when the control circuit 7 reads the first counter 5 and the second counter 6 every one second, the count value lp of the second counter 6 becomes a value near 540540. This value corresponds to the length of time that the second counter 6 is counting clock pulses. The count value lp of the second counter 6 may not be exactly 1 second due to the influence of various interrupt processes in software processing in the cycle in which the control circuit 7 reads. This is the reason for providing the second counter 6.

The capacity m of the sending buffer 2 is 10 ^-10, which is the probability that packets added to this line will overflow from the buffers B _{1 to} B _m and be discarded.
It is determined from the following conditions. Assuming that the packet traffic that joins this outgoing line arrives at Poisson, and if the outgoing line is used up to a utilization efficiency of 0.9, m will be calculated by queuing theory.
= 110. If the packet traffic arrives entirely in Poisson, a packet drop rate of 10 ^-10 is achieved, but A
Since the TM method is intended to handle a wide variety of traffic, the packet arrival characteristics are difficult to predict.

Therefore, set K = 40. When a packet arrives at Poisson at a transmission rate of 156 [Mbit / sec], the probability that the number of packets accumulated in the transmission buffer will be K or more is a value that is sufficiently smaller than 10 ^{-10 at} which overflow occurs. It can be set as desired. The probability that the number stored in the sending buffer exceeds K is about 10 ⁻⁴ when the Poisson arrives and the outgoing line usage efficiency is 0.9. Therefore, the expected lk per second is 10 ^{-4 on} average.
× 0.9 × 540540≈49, which is an observable value. That is, this value is a value corresponding to the probability that 40 or more packets will be accumulated in the sending buffer when the packets arrive with traffic that causes overflow with a probability of 10 ^-10 . When the count value of the first counter 5 is 49 10
It is possible to recognize that packets have arrived with traffic that causes overflow with a probability of ^-10 . On average, lk is a value around this, and lk is a value (49).
When it is much larger than, it means that the traffic pattern that the packet discard rate exceeds 10 ^-10 is added as an input.

Therefore, here, the reference value Aup = 10 ^−3, and Adw =
It is set in the control circuit 7 as 10 ^-4 .

Here, the control circuit 7 takes in the count value lk of the counter 5 and the count value lp of the second counter 6 at regular time intervals (1 second), and calculates the calculated value (A = A) from the count values (lk, lp). lk / lp)
Ask for. Then, the control circuit 7 calculates the calculated value (A = lk / l
When p) exceeds a preset reference value Aup (= 10 ^-3 ), new call connection to the corresponding outgoing line is rejected, and the calculated value (A = lk / lp) is changed to the reference value Adw (= When it goes below 10 ^-4 ), a new call connection to the applicable outgoing line is restarted. As described above, the reason why two types of reference values are provided is that if one type of reference is used, rejection of new calls and resumption of reception may be repeated in a short cycle, which is not preferable for control. Hysteresis is provided for switching between rejecting and resuming acceptance of such calls.

As described above, the present embodiment has been described by giving values such as m, k, Aup, Adw, and the target packet discard rate 10 ⁻¹⁰ , but the present invention is not limited to these values.

〔The invention's effect〕

As described above, according to the present invention, the probability of overflow of the sending buffer is equal to or higher than the target discard rate, based on the time ratio in which the number of packets accumulated in the sending buffer is a certain number or more. It is determined whether or not a new call connection is permitted or not permitted. As a result, even if the packet arrival pattern changes, the packet discard rate can be kept below the target value. Also, the probability that the number of packets that remain is a certain number or more is greater than the probability that an overflow actually occurs, so the count value for obtaining the time ratio becomes a large value, and it is possible to make an accurate determination based on the count result. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the embodiment of the present invention. 1 ... Call admission control device, 2 ... sending buffer, 4 ... AND circuit, 5 ... first counter, 6 ... second counter, 7 ... control circuit.

Claims (1)

(57) [Claims] 1. A transmission buffer capable of accumulating a predetermined number of packets to be transmitted to an output line, and an accumulation amount detecting means for outputting a predetermined detection signal when a predetermined number or more of packets are accumulated in the transmission buffer. A first counter that counts timing pulses having a constant cycle only during a period in which the detection signal is output from the storage amount detecting means; a second counter that counts timing pulses having a constant cycle; and these counters. Is initialized and then the count value of each counter is read when an arbitrary time has elapsed, and the value obtained by dividing the count value of the first counter by the count value of the second counter is equal to or greater than a predetermined reference value. And a count value acquisition determining means that repeatedly determines whether the divided value exceeds the reference value when the count value acquisition determining step determines that the divided value exceeds the reference value. Rejecting a new call connection to the outgoing line that occurs thereafter, and restarting the new call connection to the outgoing line when the counted value acquisition determining unit determines that the divided value falls below the reference value. A call admission control device comprising: