JP2540686Y2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a matrix type liquid crystal display device having a scanning line electrode and a signal line electrode, particularly for generating an AC drive signal for an MSI active display panel. The present invention relates to a liquid crystal display device having a circuit for generating a polarity inversion drive signal.

[Outline of the invention]

According to the present invention, a frequency-divided signal obtained by frequency-dividing a shift clock for line-sequentially scanning a scanning line electrode of a dot matrix display device and a signal obtained by performing an exclusive OR operation on a first polarity inversion signal for inverting the polarity for each frame are provided. When used as the second polarity inversion signal for driving the liquid crystal, a normal display is executed because the interface timing of the existing liquid crystal driver is not matched due to a difference in timing of various control circuits for generating an interface signal of the liquid crystal. May not. Therefore, according to the present invention, even when there is a difference in the interface timing of various control circuits, the difference between the control circuits does not occur by providing the synchronization means so as to always match the driver timing. With the goal.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional polarity inversion drive signal generation circuit. In FIG. 3, CL1 is a shift clock signal, and FLM is a frame signal. M is a first polarity inversion signal that inverts the polarity every frame. DFM is a second polarity inversion signal. 4 indicates that the shift clock CL1 is 1
Dividing circuit that divides frequency by / 4. Q ₁ is the divided output signal. 5 is an exclusive OR circuit. FIG. 4 is a diagram showing the timing of the conventional circuit diagram of FIG.

In FIG. 3 and FIG.
The / 4 divider circuit 4 is reset, and the shift clock signal CL1
Is input as a clock signal. Divided signal to Q ₁ 1/4 frequency divider 4 is input to the exclusive OR circuit 5 generates the second polarity inversion signal DFM performs an exclusive OR between said first polarity inversion signal M . As shown in FIG. 4, the second polarity inversion signal DFM has the following problems. First, a timing time difference t between the fall timing of the shift clock signal CL1 and the polarity inversion timing of the second polarity inversion signal DFM.
_DFM occurs. The timing time difference t _DFM is determined depending on the pulse width of the shift clock signal CL1. However, since the timing time difference t _DFM required for the liquid crystal driver is specified to be about max 500 ns,
With a timing difference t _DFM longer than this, a normal display function cannot be executed. Until now, there has been a restriction that only a liquid crystal control circuit that matches the driver timing can be used. Further, since the 1/4 frequency dividing circuit 4 is reset by the FLM signal, the polarity is instantaneously changed as shown in the period A of the DFM waveform in FIG. Since switching occurs, for example, in the case of a display panel of 640 × 400 dots, there has been a problem that the display of the 400th line is not displayed normally.

[Problems to be solved by the invention]

As described above, if the timing of the driver IC and the timing of the control circuit do not match, normal display cannot be performed, and only the specific control circuit can be applied at present, which is inconvenient for the user. There are also many problems on the supply side, such as extremely narrowing the range of use.

[Means for solving the problem]

The present invention has been made in order to solve the above-described problem, and includes a frame signal, a shift clock signal for line-sequential scanning, and a frequency divider circuit for dividing the shift clock signal. Synchronizing means for synchronizing the frequency-divided signal of the frequency dividing circuit and the first polarity-inverted signal for inverting the polarity for each frame with the shift clock, and using exclusive frequency control of the synchronized frequency-divided signal and the first polarity-inverted signal. An exclusive OR circuit for summing, and using a polarity inversion signal generation circuit that outputs a polarity inversion drive signal from the exclusive OR circuit, using an interface signal timing of the control circuit and an interface timing of the liquid crystal driver. It is characterized by matching.

[Action]

According to the present invention, the synchronization means is provided as described above, and the polarity inversion timing of the shift clock signal and the second polarity inversion signal is set to substantially 0. Matches.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of the invention of FIG. In FIG. 1, a synchronization circuit 2 is added as synchronization means. 1/4 frequency dividing circuit 1, exclusive OR circuit 3, and shift clock signal of other circuit units
The interface signals of CL1, the frame signal FLM, and the first polarity inversion signal M have the same functions as those in FIG. Here, the output to Q ₁ 1/4-divider circuit is input to the synchronization circuit. Further, the first polarity inversion signal M is also input in the same manner. The synchronization circuit 2
It is composed of two D-type flip-flop circuits. Then, a Q ₁ which is input to the synchronization circuit 2 as data output Q takes in the data Q ₁ at the fall of CL1
_{Assume 2} . Similarly, the first polarity inversion signal M input into the synchronization circuit 2 as data, and outputs M ₂ takes in the data M at the fall of CL1. Thus, Q ₂ and M ₂ is outputted from the synchronization circuit 2 shift clock CL1
Is synchronized with the falling edge. The timing is shown in FIG. Q ₂ which is the output of the synchronization circuit ₂ and
M ₂ is XORed by the exclusive OR circuit 3 and the second
Generates a polarity inversion signal DFM. As described above, when the shift clock CL1 falls, the output Q ₁ of the 1/4 frequency divider 1 is output.
And the first polarity inversion signal M passes through the synchronization circuit 2 to Q ₂ ,
Since the synchronized output signals of M _2, the time difference t _DFM falling timing of the shift clock CL1 to the polarity inversion of the second polarity inversion signal DFM can be made zero. Therefore, even if the timings of the interface signals of the various control circuits are slightly different, it is possible to always match the interface timing of the liquid crystal driver within the standard.

[Effect of the invention]

As described above, according to the present invention, even if the timings of various control circuits are slightly different, it is possible to always match with the interface timing of the liquid crystal driver, so that the control circuit can be used without restriction to a specific control circuit. The range of application is extremely wide. Further, the timing of the polarity inversion of the second polarity inversion signal DFM and the fall time difference t of the shift clock CL1
_{Since the DFM} becomes 0, the optimum condition for the liquid crystal driver circuit is obtained, and the current flowing through the liquid crystal driver circuit is suppressed to a small value. Therefore, the current consumption of the liquid crystal driver circuit is reduced.

A display panel using a two-terminal nonlinear characteristic such as MSI or MIM as an active element can increase the voltage ratio applied to a selected point and a non-selected point, so that the contrast ratio can be increased. _{Also in the DFM} , there is a problem of display failure such as a stripe-shaped display for each line. However, the present invention can solve these problems. Further, the frequency dividing circuit is 1/4
By dividing the frequency, the frequency of the drive voltage applied to the non-selection and selection points does not change significantly depending on the display pattern (all selections / all non-selections / characters / graphics). In, since it is possible to have a uniform frequency distribution,
The frequency dependence of the threshold voltage of the liquid crystal can be reduced. Therefore, the present invention has a great effect, such as eliminating the crosstalk phenomenon (which varies depending on the display pattern) in the horizontal line and vertical line directions, which has conventionally been a problem.

[Brief description of the drawings]

FIG. 1 shows a circuit diagram of an embodiment of the present invention. FIG. 2 shows the timing diagram of FIG. FIG. 3 shows a conventional circuit diagram. FIG. 4 shows the timing diagram of FIG. 1, 4 1 frequency divider circuit 2 ２ synchronization circuit 3, 5 排 他 exclusive OR circuit CL1 シ フ ト shift clock signal FLM フ レ ー ム frame signal M… first polarity inversion signal DFM… Second polarity inversion signal

Claims (3)

(57) [Scope of request for utility model registration] A shift circuit for inputting a frame signal and a shift clock signal for performing line-sequential scanning; a frequency dividing circuit for dividing the shift clock signal; a first polarity inversion signal for inverting the polarity for each frame; Synchronizing means for synchronizing the frequency-divided signal output from the frequency dividing circuit with the shift clock signal;
An exclusive-OR circuit for performing an exclusive-OR operation on the synchronized frequency-divided signal output from the synchronization means and the synchronized first polarity-inverted signal. A liquid crystal display device using a polarity inversion signal generation circuit for outputting a signal, wherein timing of an interface signal of a control circuit is matched with timing of an interface signal of a liquid crystal driver. 2. A frequency divider circuit for receiving a frame signal and a shift clock signal for performing line-sequential scanning, dividing the shift clock signal, a first polarity inversion signal for inverting the polarity for each frame, and the division circuit. Synchronizing means for synchronizing the frequency-divided signal output from the frequency dividing circuit with the shift clock signal;
An exclusive-OR circuit for performing an exclusive-OR operation on the synchronized frequency-divided signal output from the synchronization means and the synchronized first polarity-inverted signal. A liquid crystal using a display panel having a two-terminal non-linear element, wherein a polarity inversion signal generating circuit for outputting a signal is used, and a timing of an interface signal of a control circuit is matched with a timing of an interface signal of a liquid crystal driver. Display device. 3. The liquid crystal display device according to claim 1, wherein the frequency dividing circuit comprises a frequency dividing circuit for dividing the shift clock signal by / 4.