JP2538762B2 - Clock loss detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock loss detection circuit capable of detecting input loss of a clock signal.

[0002]

2. Description of the Related Art In digital communication devices and the like, there is a demand for a clock break detection circuit suitable for LSI without the need for external capacitors and resistors for the purpose of reducing manufacturing costs. As a clock loss detection circuit for this purpose, for example, the technique disclosed in Japanese Patent Laid-Open No. 3-206512 (Invention title: clock loss detection circuit) is disclosed. The disclosed clock loss detection circuit has one counter as a basic constituent element, the internal clock generated in the device is counted by the counter, and the count is reset every time the external clock is input. That is, this counter resets the count when the external clock is input, prevents counting up to the set count value, and does not output the count-up output indicating the disconnection of the external clock. On the other hand, when this counter counts up the set count value, it outputs the count-up output to indicate disconnection of the external clock. It should be noted that this counter sets the time from receiving the first internal clock to transmitting the count-up output to be larger than the cycle of the external clock.

[0003]

This conventional clock loss detection circuit has the drawbacks that the circuit is complicated because it is necessary to generate the internal clock in the device, and the loss of the internal clock cannot be detected. .

Further, this conventional clock loss detection circuit is
It is necessary to supply an external clock to detect a clock break only to the reset input terminal of the counter, and there is a drawback that the circuit configuration lacks flexibility.

Further, a digital communication device may require two clock signals like a digital signal speed conversion circuit, but these circuits need to detect disconnection of the two clock signals.

[0006]

According to one of the clock loss detection circuits of the present invention, a first counter output is generated every time the first clock signal is counted up in a first predetermined time.
And a second clock signal every time the second clock signal is counted up in a second predetermined time longer than the first predetermined time.
A second counter which generates a counter output and whose already-counted value is cleared by the first counter output, the first counter output and the second counter output, and the first counter after receiving the second counter output A first clock signal disconnection determination circuit that generates a first clock signal disconnection determination signal indicating disconnection of the first clock signal is provided until a counter output is received.

One of the clock loss detection circuits is configured such that the first clock signal loss determination circuit is a first flip-flop which is set by the output of the first counter and reset by the output of the second counter. Can be taken.

In addition, in addition to the clock loss detection circuit, another one of the clock loss detection circuits of the present invention generates a third counter output each time the second clock signal is counted up in a third predetermined time. A third counter and the first
A fourth counter output is generated every time the clock signal is counted up in a fourth predetermined time longer than the third predetermined time, and the already-counted value is cleared by the third counter output; A second clock signal disconnection determination signal indicating disconnection of the second clock signal is received during a period from receiving the counter output and the fourth counter output to receiving the fourth counter output to receiving the third counter output. And a second clock signal disconnection determination circuit that occurs.

[0009]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Further, FIG. 2 is a signal waveform diagram in each part of this embodiment.

This clock break detection circuit detects that one of the two clock signals 101 and 102 is broken. That is, the first clock break detecting circuit including the counters 1 and 2 and the flip-flop 5 receives the clock signals 101 and 102 to detect the break of the clock signal 101, and includes the counters 3 and 4 and the flip-flop 6. The second clock loss detection circuit receives the clock signals 101 and 102 and detects the loss of the clock signal 102.
The clock signals 101 and 102 are a write clock and a read clock of the speed conversion circuit, and are clock signals supplied from the outside of this circuit.

First, in the first clock break detection circuit, the first clock signal 101 is input to the C (clock) terminal of the first counter 1. The counter 1 is set to the time t.
It is assumed that the first count starts at 0. The counter 1 triggers the clock signal 101 at time t0.
The counting end time t2 is reached when the counting is started from (starting from) and the set count value (five in FIG. 2) is counted (counted up).
At "H" for one cycle of the clock signal 101
(Or “L”), the first counter output 103 becomes R
It occurs at the C (ripple carry) terminal. Now, the time for counting the clock signal 101 to the set count value is the first predetermined time TA.

The second clock signal 102 is input to the C terminal of the second counter 2. When the counter output 103 is not input to the R (reset) terminal, the counter 2 starts counting the trigger of the clock signal 102 from the time t0, and when counting to the set count value (10 in FIG. 2), this counting ends. At time t3, the clock signal 10
A second counter output 104, which is "H" (or "L") for one cycle of 2, is generated at the RC terminal. The counter 2 sets the time for counting the clock signal 102 to the set count value to the second predetermined time TB which is longer than the first predetermined time TA.

However, since the counter 2 inputs the counter output 103 to the R (reset) terminal at the time t2, the already counted value is cleared at the time t2. Therefore, the counter 2 cannot count up to the set count value at time t3, and this time t3
Also in, the counter output 104 remains "L" (or "H").

The first flip-flop 5 is a disconnection determination circuit for the clock signal 101, receives the counter output 103 as a set input at the S (set input) terminal, and the counter output 104 as a reset input at the R (reset input) terminal. To receive. This flip-flop 5 has a counter output 1
03, it is judged that the clock signal 101 is normal, and the "H" (or "L") clock loss judgment output 1
Results in 05. On the other hand, when receiving the counter output 104,
The flip-flop 5 determines that the clock signal 101 is disconnected, and produces the clock disconnection determination output 105 having the opposite logic level "L" (or "H"). This “L” (or “H”) clock loss determination output 105
Continues until it receives counter output 104 and then counter output 103.

That is, in the first clock break detection circuit, when the clock signal 101 is normal, the counter 1 continues to supply the counter output 103 to the flip-flop 5 every first predetermined time TA, so that the clock signal 101 is normal. , And keeps the “H” (or “L”) clock loss determination output 105.

On the other hand, when the clock signal 101 becomes out of clock (between the eighth pulse and the ninth pulse in FIG. 2) and this signal 101 is fixed at "L" (or "H"), the counter 1 counts. The counter output 103 remains "L" (or "H"). Then, the counter 2 reaches the set count value (from time t2 to time t4)
Can be counted, and counter output 1 at time t4
04 becomes "H" (or "L") for one cycle of the clock signal 102. The flip-flop 104 is at time t
When the counter output 104 is received at 4, the clock signal 10
The clock signal disconnection determination signal 105 changed to "L" (or "H") indicating disconnection of 1 is generated.

The counter output 1 indicates that the clock signal disconnection determination signal 105 is "L" (or "H").
It is held until 03 becomes "H" (or "L"), and it can be determined that the clock signal 101 is abnormal (clock disconnected).

That is, at the time t4, the clock signal 10
When the clock signal 101 returns to normal after the clock signal disconnection determination signal 105 indicating the disconnection of 1 is generated, the counter 1 counts five clock signals 101 at time t6 and outputs “H” (or “L”). ") Counter output 103
Is generated. As a result, the clock loss determination signal 101 changes to "H" (or "L"), and the clock signal 101
Can be judged to be normal.

The first clock loss detection circuit described above can be implemented as an LSI because it can be constructed entirely of logic elements, and the circuit is simple because it is not necessary to generate an internal clock in the device. There is.

In addition, this clock loss detection circuit, if the relationship of the first predetermined time TA <the second predetermined time TB is maintained, regardless of the clock cycle of the clock signals 101 and 102, the internal clock, There is an advantage that the clock loss detection operation is guaranteed regardless of the external clock, and it can be applied to a system with various clock cycles without changing the circuit constant.

Next, the second clock disconnection detection circuit also has substantially the same configuration as the first clock disconnection detection circuit and performs substantially the same operation. However, the counter 3 outputs “H” (or “L”) counter output 106 each time the clock signal 102 is counted up for the third predetermined time TC.
The counter 4 produces the counter output 107 of "H" (or "L") every time the clock signal 101 counts up for the fourth predetermined time TD longer than the third predetermined time TC. The counter 4 also clears the already counted value by the counter output 106. The flip-flop 6, which is a disconnection determination circuit for the clock signal 102, has a counter output 10
6 and the counter output 107, the counter output 107
During the period from the reception of the counter output 106 to the reception of the counter output 106, the clock signal disconnection determination signal 108 indicating "L" (or "H") indicating the disconnection of the clock signal 102 is generated.

Now, assuming that the clock signal 102 is cut off between the 28th pulse and the 29th pulse, the counter 3 requires from time t5 to time t8 to count the set count value (five), During this time, the counter output 106 is "L"
(Or “H”). Since the counter 4 is not reset by the counter output 106 during this time, the set count value (five) is counted up at the time t7 to generate the counter output 107 of "H" (or "L"). As a result, the clock loss determination signal 108 changes to "L" (or "H"). The detection state of the interruption of the clock signal 102 is the time t8 when the clock signal 102 is normally recovered.
Until the counter 3 counts up the clock signal 102.

The first predetermined time TA and the fourth predetermined time T
If D is the same, the counters 1 and 4 may be counters of the same design, which is advantageous in that they can be designed and manufactured inexpensively and quickly.

As described above, the clock loss detection circuit according to the present embodiment can be formed into an LSI because it can be configured by all logic elements. Further, in the clock loss detection circuit of this embodiment, if the relationship of the first predetermined time TA <the second predetermined time tB and the third predetermined time TC <the fourth predetermined time TD is maintained, the clock signals 101 and 102 are There is an advantage that the clock loss detection operation is guaranteed regardless of the clock period or the input loss of either of the signals 101 and 102, and the present invention can be applied to a system with various clock periods without changing the circuit constant. be able to.

[0026]

As described above, according to one aspect of the present invention, the first counter that produces the first counter output each time the first clock signal is counted up for the first predetermined time TA and the second clock are provided. A second counter that generates a second counter output each time the signal is counted up for a second predetermined time TB that is longer than the first predetermined time TA, and that clears an already-counted value by the first counter output;
A second counter output and a second counter output;
Since the first clock signal disconnection determination circuit that generates the first clock signal disconnection determination signal indicating the disconnection of the first clock signal is included in the period from receiving the counter output to receiving the first counter output, As a result of being able to configure the circuit of (1) with logic elements, not only is it possible to realize an LSI, but there is an advantage that the circuit configuration is simple because it is not necessary to generate an internal clock in the device.

Further, in the clock loss detection circuit, if the relationship of the first predetermined time TA <the second predetermined time TB is maintained, each of the first and second clock signals has any clock cycle. Even if there is, there is an advantage that the clock loss detection operation is guaranteed regardless of the internal clock and the external clock, and it can be applied to the system of various clock cycles without changing the circuit constant.

Another aspect of the present invention is that, in addition to the first and second counters and the first clock signal determination circuit, each time the second clock signal is counted up in a third predetermined time. A third counter that produces a third counter output, and a fourth counter output and the third counter each time the first clock signal is counted up for a fourth predetermined time TD longer than the third predetermined time TC. In the period from receiving the fourth counter output, the third counter output, the fourth counter output, the third counter output, and the third counter output, And a second clock signal disconnection determination circuit that generates a second clock signal disconnection determination signal indicating disconnection of the second clock signal. Both in the case of an external clock, so completely eliminates the need for generating an internal clock in the device for either of the clock signal disconnection detection is particularly useful.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a signal waveform diagram in each part of the present embodiment.

[Explanation of symbols]

 1 to 4 counter 5, 6 flip-flop 101, 102 clock signal 103, 104, 106, 107 counter output 105, 108 clock loss determination output

Claims (5)

(57) [Claims] 1. A first counter output is generated each time the first clock signal is counted up in a first predetermined time.
And a second clock signal every time the second clock signal is counted up in a second predetermined time longer than the first predetermined time.
A second counter which generates a counter output and whose already-counted value is cleared by the first counter output, the first counter output and the second counter output, and the first counter after receiving the second counter output A clock loss detection circuit, comprising: a first clock signal loss determination circuit that generates a first clock signal loss determination signal indicating a loss of the first clock signal during a period until receiving a counter output. 2. The first clock signal disconnection determination circuit is a first flip-flop which is set by the output of the first counter and reset by the output of the second counter. Clock loss detection circuit. 3. A clock loss detection circuit according to claim 1,
A third counter generating a third counter output each time the second clock signal is counted up in a third predetermined time, and the first clock signal is counted up in a fourth predetermined time longer than the third predetermined time. Receiving a fourth counter output and a fourth counter output for which the already-counted value is cleared by the third counter output, and the fourth counter output. And a second clock signal disconnection determination circuit for generating a second clock signal disconnection determination signal indicating disconnection of the second clock signal during a period from the reception of the third counter output. Detection circuit. 4. The second clock signal disconnection judging circuit is a second flip-flop which is set by the output of the third counter and reset by the output of the fourth counter. The clock loss detection circuit described. 5. The clock loss detection circuit according to claim 4, wherein the first predetermined time is equal to the fourth predetermined time.