JP2534780B2 - Transversal equalizer control circuit - Google Patents

Description

The present invention relates to a transversal equalizer control circuit, and more particularly to a transversal equalizer control circuit applied to a demodulated signal in a digital communication system.

[Conventional technology]

2. Description of the Related Art Conventionally, in a digital communication system, a transversal equalizer has been used in order to remove a waveform distortion that a pulse train transmitted at a constant clock cycle undergoes when passing through a transmission line. This type of transversal equalizer weights and combines each tap output of the delay line with taps, and it is a ZF (Zero-Forcin) that repeatedly adjusts the weighting.
The g) method is used to create inverse characteristics of the transmission line to compensate for waveform distortion.

FIG. 2 shows a conventional transversal equalizer control circuit (5
FIG. 3 is a block diagram showing an example of a tap), which is an AD converter.
1, delay circuits 2 to 5, tap weighting circuits 11 to 15, maximum level error determination circuits (MLE) 21 to 25, and integration circuits 31 to 35. The demodulated signal S _P demodulated by the demodulator is A−
It is supplied to the D converter 1 and is multivalued. In this case, assuming that the demodulated signal S _P is, for example, a signal in one axial direction of the 16QAM (DC amplitude modulation) signal, the output of the AD converter 1 is the first pass signal, the second pass signal, and the third pass signal. A 3-bit signal consisting of a pass signal is obtained. First most significant bit
The pass signal is an identification signal D indicating the quadrant in which the signal is located, and the third pass signal is an error signal E indicating the direction of deviation of the signal from the reference position.

The identification signal D from the AD converter 1 is supplied to the cascaded delay circuits 2 to 3, and the error signal E is supplied to the cascaded delay circuits 4 to 5. The identification signal and the error signal are taken out from each tap on the input side and the output side of each delay circuit in correlation with each time slot and applied to the tap weighting circuits 11 to 15. Each of the tap weighting circuits 11 to 15 calculates the tap weighting by taking the product of the applied identification signal and error signal. Each integration circuit 31-35
The output signals from the tap weighting circuits 11 to 15 are averaged, tap weighting signals C1 to C5 are generated and sent to the transversal equalizer, and the weighting of each tap of the transversal equalizer is performed for each time slot. Control in small amounts.

On the other hand, the error signal has a region having accurate error information, and the synchronization pull-in characteristic can be improved by using only the error signal in this region. For this purpose, maximum level error determination circuits 21 to 25 are provided. The maximum level error determination circuits 21 to 25 receive the first pass signal, the second pass signal, and the third pass signal of the output signal of the AD converter 1, respectively, determine the maximum level error region, and show the determination result. The signal is sent to the tap weighting circuits 11 to 15 in synchronization with the error signal. The tap weighting circuits 11 to 15 perform tap weighting calculation by adopting or not adopting the error signal as error information according to the signals from the maximum level error determining circuits 21 to 25.

[Problems to be Solved by the Invention]

In the above-described conventional transversal equalizer control circuit, the output signal of the maximum level error determination circuit must be synchronized with the error signal input to each tap weighting circuit. Each tap must be provided, and therefore the circuit scale becomes large, and it is difficult to reduce the size and power consumption.

An object of the present invention is to provide a transversal equalizer control circuit that solves such a conventional problem by sharing a maximum level error determination circuit.

[Means for solving the problem]

The transversal equalizer control circuit of the present invention applies N taps (N taps) applied to a demodulated signal in a digital communication system.
= 3,5 ... Odd) in the transversal equalizer control circuit, the AD converter for identifying the demodulated signal and the identification signal of the most significant bit of the output signal of the AD converter are clocked. An identification signal delay circuit having N taps for delaying an integral multiple of the cycle, and an error signal for delaying an error signal indicating an internal deviation of the output signal of the AD converter by (N-1) / 2 times the clock cycle. A delay circuit, a maximum level error determination circuit that receives the output signal of the A / D converter, determines a maximum level error region, and outputs a determination result, and one of N taps of the identification signal delay circuit. N tap weighting circuits for calculating the tap weighting by receiving the identification signal, the error signal output from the error signal delay circuit, and the output signal of the maximum level error determination circuit, respectively, and the output from the tap weighting circuit. And a N integrating circuits for averaging the respective receiving signals.

〔Example〕

 The present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a transversal equalizer control circuit (5 taps) according to the present invention.
D converter 1, delay circuits 2 to 7, tap weighting circuits 11 to 15,
A maximum level error determination circuit 20 and integration circuits 31 to 35 are provided.

As in the conventional block diagram shown in FIG. 2, the demodulated signal S _P demodulated by the demodulator is supplied to the AD converter 1 for multi-level discrimination and is output as the output of the AD converter 1. A 3-bit signal composed of the 1-pass signal, the 2-pass signal, and the 3-pass signal is obtained. The first path signal of the most significant bit is an identification signal D indicating the quadrant in which the signal is located, and the third path signal is an error signal E indicating the direction of deviation of the signal from the reference position.
Is. The identification signal D from the AD converter 1 is supplied to the identification signal delay circuits 2 to 5, and the identification signals at the output side taps of the respective delay circuits 2, 3, 4, and 5 are D ₊₁ and D, respectively.
_{It is +2} , D ₊₃ , D ₊₄ . Where D ₊₁ , D ₊₂ , D ₊₃ , D ₊₄ is
This means that the identification signal D is delayed by 1 bit, 2 bits, 3 bits, and 4 bits in the clock cycle.
Further, the error signal E is supplied to the error signal delay circuits 6 to 7 and outputted as the error signal E ₊₂ . The tap weighting circuits 11 to 15 include one of the identification signals from the input side taps and the output side taps of the identification signal delay circuits 2 to 5 and the error signal E from the error signal delay circuits 6 to 7. ₊₂ is applied to each to perform tap weighting calculation.

Here, looking at the correlation between the identification signal and the error signal input to each of the tap weighting circuits 11, 12, ..., 15,
(D, E _{+ 2} ), (D _{+ 1} , E _{+ 2} ), ..., (D _{+ 4} , E _{+ 2} ). Therefore, when this is viewed with the error signal E as a reference, it becomes clear that the correlations are (D ₋₂ , E), (D ₋₁ , E), ..., (D ₊₂ , E).

On the other hand, since the same error signal E ₊₂ is supplied to each of the tap weighting circuits 11 to 15, even if the output signal of one maximum level error determination circuit is shared, it is synchronized with the error signal E ₊₂ . The maximum level error determination circuit 20 receives the first path signal, the second path signal, and the third path signal from the AD converter 1, respectively, determines the maximum level error area, and taps the signal indicating the determination result at each tap. The weighting circuits 11 to 15 are commonly sent to improve the synchronization pull-in characteristic.

The integrating circuits 31 to 35 average the respective outputs of the tap weighting circuits 11 to 15, generate weighting signals C1 to C5 of each tap of the transversal equalizer, and send the weighting signals C1 to C5 to the transversal equalizer. The weighting of each tap of the transversal equalizer is controlled for each slot by a small amount.

When the number of taps is N (N = 3, 5, ... Odd), the delay circuit for the identification signal is composed of N-1 delay circuits having N taps that are delayed by integer multiples of the clock cycle. In addition, the error signal delay circuit can be operated in the same manner as described above by configuring the delay circuit to delay by (N-1) / 2 times the clock cycle.
It is also clear that the present invention can be applied to cross polarization interference compensation.

〔The invention's effect〕

As described above, according to the transversal equalizer control circuit of the present invention, the error signal supplied to each tap weighting circuit can be made common, so that the maximum level error determination circuit is a single circuit regardless of the number of taps. Therefore, there is an effect that the circuit configuration is simplified, the circuit is downsized, and the power consumption is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a transversal equalizer control circuit of the present invention, and FIG. 2 is a block diagram showing an example of a conventional transversal equalizer control circuit. 1 ... AD converter, 2-7 ... delay circuit, 11-15 ...
Tap weighting circuit, 20 to 25 ... maximum level error judgment circuit, 31 to 35 ... integrating circuit, C1 to C5 ... tap weighting signal, D ... identification signal, E ... error signal, _SP ... demodulation signal .

Claims (1)

(57) [Claims] 1. A N-tap (N = 3,5 ... Odd) transversal equalizer control circuit applied to a demodulated signal in a digital communication system, which identifies the demodulated signal by A
N for delaying the identification signal of the most significant bit of the output signals of the -D converter and the AD converter by an integral multiple of the clock cycle
An identification signal delay circuit having a number of taps, an error signal delay circuit for delaying an error signal indicating an internal deviation of the output signal of the AD converter by (N-1) / 2 times the clock period, and the A- A maximum level error determination circuit that receives the output signal of the D converter and determines a maximum level error region and outputs a determination result, an identification signal from one of N taps of the identification signal delay circuit, and the error signal delay N tap weighting circuits that receive an error signal output from a circuit and an output signal of the maximum level error determination circuit and calculate tap weighting, respectively, and receive output signals from the tap weighting circuit and average them. A transversal equalizer control circuit comprising N integrating circuits.