JP2531781C - - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a subtraction circuit, and more particularly to a subtraction circuit having a low-cost circuit configuration that can be easily integrated. INDUSTRIAL APPLICABILITY The present invention is suitably used for a subtraction circuit of a photoelectric conversion device that removes a dark output from an optical signal including a dark output. [Prior Art] One of the characteristics required for a sensor device is a high S / N ratio. That is, it is required to increase the signal component and reduce the noise component. However, the noise component largely depends on the pattern layout and manufacturing process of the sensor unit, and in order to increase the resolution of the sensor unit, the smaller the pixel size and the higher the integration, the greater the difference in device characteristics between pixels. Are noticeable, FPN (Fixed Pattern Noise) is large, and the S / N ratio tends to deteriorate. In the FPN, various characteristics between pixel devices are closely related to each other, and it is difficult to reduce the characteristics. This has been the most important problem in configuring a sensor device. In order to solve such a problem, first, an output (FPN) at the start of accumulation from the sensor unit is set.
), Then read the optical signal (including FPN) at the end of accumulation, and then take the difference to provide a device having a subtraction circuit that can directly output only the optical signal component without FPN. Was figured out. FIG. 8 is a partial circuit configuration diagram showing one configuration example of a subtraction circuit used in a conventional sensor device. In the figure, C211 is a capacitor for accumulating the output from the sensor at the start of accumulation, and C221 is a capacitor for accumulating an accumulation end signal including fixed pattern noise. The capacitors C211 and C221 are connected to the switch means M211 and M221.
And the differential amplifier A5 via switch means M212 and M222. The output at the start of accumulation and the signal at the end of accumulation including the fixed pattern noise are simultaneously output to the differential amplifier A5, and the difference between the signal at the start of accumulation and the signal at the end of accumulation including the fixed pattern noise by the differential amplifier A5. Thus, an optical signal containing no fixed pattern noise is output. [Problems to be Solved by the Invention] However, in the photoelectric conversion device shown in FIG. 8, it was difficult to integrate the entire photoelectric conversion device due to the frequency characteristics and the like of the differential amplifier. [Means for Solving the Problems] A subtraction circuit according to the present invention comprises an optical sensor, a first signal source for outputting a signal at the start of accumulation of the optical sensor, and an optical signal at the end of accumulation in the optical sensor. A second signal source to be output; first switch means connected to the first signal source; second switch means connected to the second signal source; A capacitance means commonly connected to an output side of the second switch means, an input side reset means for selectively connecting an input side of the capacitance means to a predetermined reset potential, and an output side of the capacitance means. Output-side potential setting means for selectively connecting to a predetermined potential, and resetting the input-side potential of the capacitance means by the input-side resetting means;
Thereafter, one of the first signal source and the second signal source is supplied to the input side of the capacitance means while the output side of the capacitance means is set to a predetermined potential by the output side potential setting means. Then, by supplying the other signal to the input side of the capacitance means, the difference between the signal from the first signal source and the signal from the second signal source is obtained from the output side of the capacitance means. And control means for connecting the potential of the input side of the capacitance means to the reset potential again by the input-side reset means, whereby an optical signal free of fixed pattern noise is accurately output from the output side of the capacitance means. It is characterized by obtaining. [Operation] In the subtraction circuit of the present invention, a signal is output from the first signal source to the capacitance means by using the first switch means connected to the first signal source (the potential of the capacitance means at this time is reduced). V1), the output side of the capacitance means is set to a reference potential, for example, GND. Then, when a signal is output from the second signal source to the capacitor means (the potential of the capacitor means at this time is set to V2) using the second switch means connected to the second signal source, The potential fluctuation on the input side is V2-V1. At this time, the potential fluctuation on the output side of the capacitance means becomes V2-V1 from the reference potential. That is, the difference signal between the signal from the first signal source and the signal from the second signal source can be output from the output of the capacitance means. [Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit configuration diagram for explaining a basic configuration of a subtraction circuit according to the present invention. In FIG. 1, S1 is a connection terminal to a first signal source, M1 is a MOS transistor for controlling ON / OFF of a signal from the first signal source by a clock φA, and S2 is a connection to a second signal source. A terminal M2 is a MOS transistor for controlling ON / OFF of a signal from the second signal source in response to a clock φB. The MOS transistor M1 and the MOS transistor M2 are commonly connected at a contact point P1, and are connected to a capacitor C. The capacitor C is connected to an output amplifier A1. The contact P1 side of the capacitor C is connected to a MOS transistor M4 whose ON / OFF is controlled by the clock φC, so that the electric charge accumulated in the wiring and the capacitor can be reset. The output side of the capacitor C connected to the output amplifier A1 is turned on by the clock φA.
The MOS transistor M3, which is N-OFF controlled, is connected at a contact P2 to a reference potential (V
R) can be applied. Hereinafter, the operation of the subtraction circuit will be described. FIG. 2 is a timing chart for explaining the operation of the above circuit. In FIG. 2, first, at time t0, the pulse φA rises, and the MOS transistor M
When M3 is turned on, the signal voltage V1 from the first signal source is read out to the contact point P1, and at the same time the contact point P2 is reset to the reference potential (VR). Next, at time t1, the clock φA falls, and the MOS transistors M1 and M3 are turned off.
In the F state, the contact P2 is in a high impedance state. Next, when the clock φB rises at time t2 and the MOS transistor M2 is turned on, the signal voltage V2 (here, V2> V1) from the first signal source is read out to the contact point P1. At this time, the potential of the contact P1 rises from V1 to V2, and the potential of the contact P2 rises by (V2-V1) from the reference potential VR by the capacitance C provided between the contact P1 and the contact P2. Therefore, a signal corresponding to the difference signal (V2-V1) is output from the amplifier A1. Next, at time t3, the clock φB falls and the MOS transistor M2 is turned off. At time t4, when the clock φC rises and the MOS transistor M4 is turned on, the charge is accumulated in the wiring and capacitor on the contact P1 side. The reset signal is reset to prepare for the next signal reading. Hereinafter, a case where the present invention is applied to a photoelectric conversion device will be described as an embodiment of the subtraction circuit of the present invention. FIG. 3 is a circuit configuration diagram of a photoelectric conversion device showing a first embodiment of the subtraction circuit of the present invention. As shown in the figure, MOS transistors M11 to M1n are connected to the bases of the sensor transistors Q1 to Qn, and a voltage VBB is applied by ON-OFF control of the pulse φBR. The respective emitters of the sensor transistors Q1 to Qn
Connected to the MOS transistors M21 to M2n and further to the MOS transistors M31 to M3n, M
OS Capacitors CP1 to CPn and capacitor CD1 via transistors M41 to M4n.
~ CD n. MOS transistors M21 to M2n are ON / OFF controlled by pulse φVRS,
The voltage VVR can be applied to the emitters of the sensor transistors Q1 to Qn, respectively. The MOS transistors M31 to M3n are ON / OFF controlled by a pulse φTP, and the MOS transistors M41 to M4n are ON / OFF controlled by a pulse φTD. Capacitors CP1 to CPn and capacitors CD1 to CDn are connected to buffers B11 to B11, respectively.
B1n, are connected to MOS transistors M51 to M5n and MOS transistors M61 to M6n via buffers B21 to B2n. MOS transistor M51 and MOS transistor M61,
MOS transistor M52 and MOS transistor M62,..., MOS transistor M5n
And the gate of the MOS transistor M6n are commonly connected, and are sequentially scanned by the shift register. By sequentially controlling the shift register, the capacitor CP 1
, The capacitor CD1, the capacitor CP2, the capacitor CD2,..., The signals accumulated in the capacitor CPn and the capacitor CDn are transferred to the horizontal transfer lines l1, l2. The horizontal transfer lines l1 and l2 are connected to the subtraction circuit component X. The subtraction circuit configuration unit X is the same as the above-described subtraction circuit except that the reference potential VR is GND, and the description of the configuration is omitted by attaching the same reference numerals. FIG. 4 is a timing chart for explaining the operation of the above circuit. First, at time t1, the clock φTP rises and the MOS transistor M31
M3n are turned on, and the accumulation end signal (including fixed pattern noise) is transferred to the temporary accumulation capacitors CP1 to CPn in a lump for all pixels. Next, at time t2, the clock φTP falls and the MOS transistors M31 to M3 fall.
n is turned off, the clock φBR falls at time t3, and when the transistors M11 to M1n are turned on, the base potentials of the sensor transistors Q1 to Qn are reset to VBB for all pixels (this is a complete reset operation). ). Next, at time t4, the clock φBR rises and the transistors M11 to M1n
Is turned off, the clock φVRS rises at time t5, and when the transistors M21 to M2n are turned on, the emitter potentials of the sensor transistors Q1 to Qn are reset to VVR (this is called a transient reset operation). During the transient reset operation, from time t6 to time t7, the clock φTD rises, the transistors M41 to M4n are turned on, and the potential at the end of the transient reset operation, that is, the potential at the start of the accumulation operation is changed to the capacitors CD1 to CDD. Transferred to n. Next, from time t7, accumulation of new signals in the sensor transistors Q1 to Qn starts, and during that time, the capacitors CP1 to CPn and the capacitors CD1 to CDn already described.
The signals at the end of accumulation (including fixed pattern noise) and the outputs at the start of accumulation are transferred to the buffers B11 to B1n, the MOS transistors M51 to M5n, and the horizontal transfer line l.
2 and buffers B21 to B2n, MOS transistors M61 to M6n, horizontal transfer line l1
Are sequentially output through. In the output operation of the accumulation end signal (including fixed pattern noise) and the accumulation start output, first, the clock φ1 is applied to the MOS transistors M51 and M61 from the shift register, and the carriers of the capacitors CP1 and CD1 are stored in the buffer B11. , Buffer B21 and read out to horizontal transfer lines l2 and l1. Next, the difference signal obtained by subtracting the dark output from the optical signal is extracted by using the above-described subtraction circuit of the present invention. During the first half of the read operation, that is, from time t8 to t9, the clock φA is at the high level, and the MOS transistors M1 and M3 are in the ON state. Therefore, the potentials of the nodes P1 and P2 become the output level at the start of accumulation and GND, respectively. Next, in the latter half of the read operation, that is, during the time t9 to t10, the clock φB is at the high level, so that the MOS transistor M2 is turned on, and the potential of the contact P1 becomes VN.
To VS + N (signal level at the end of accumulation). At this time, since the node P2 is in a floating state, the potential of the node P2 rises from the GND level by the potential rise (Vs) of the node P1, and the level is finally output. Thereafter, at time t10, the clock φ1 from the shift register goes low, the clock φC rises, and in the first half (time t10 to t11), the clock φA goes high, and the transistors M1 and M3 are turned on. , The contacts P1, P2 and the horizontal transfer line 11 are reset. Next, in the latter half (time t11 to t12), the clock φB goes high, the transistor M2 is turned on, and the horizontal transfer line l2 is reset. Such a series of read operations are sequentially performed for each pixel, and an optical signal is output.
At this time, even if the output level at the start of accumulation varies from pixel to pixel, only the signal level at the end of accumulation without fixed pattern noise is output to the output terminal.
Optical information with a high N ratio can be obtained. FIG. 5 is a circuit configuration diagram of a photoelectric conversion device showing a second embodiment of the subtraction circuit of the present invention. FIG. 6 is a timing chart for explaining the basic configuration of the circuit. As shown in FIG. 5, the present embodiment is a four-wire readout type photoelectric conversion device in which the output from the pixel is divided into upper and lower stages, and further into upper and lower stages. Note that the sensor configuration unit and the subtraction circuit configuration unit for each of the four divided horizontal transfer lines are the same as those in the first embodiment, and a detailed description of the configuration and operation will be omitted. As shown in FIGS. 5 and 6, clocks φC1, φC2, φC3, and φC4 are sequentially scanned to output an output at the start of accumulation and a signal after the end of accumulation, respectively, on horizontal transfer lines l1a and l2a.
, Horizontal transfer lines 11b and 12b, horizontal transfer lines 11c and 12c, and horizontal transfer lines 11d
, L2d. The subtraction circuit components Xa to Xd correspond to the subtraction circuit component X in the first embodiment, but no amplifier is provided here. MOS transistors M1a-M
4a, M1b to M4b, M1c to M4c, and M1d to M4d correspond to the MOS transistors M1 to M4, and the capacitors C1 to C4 correspond to the capacitor C. Outputs from the contacts Q1 to Q4 of the subtraction circuit components Xa to Xd are connected to MOS transistors M5a to M5d which are ON-OFF controlled by clocks φC3, φC4, φC2, φC1, respectively. The MOS transistors M5a and M5b are commonly connected, and are turned on by the clock φA0 via the amplifier A2.
The N-OFF controlled MOS transistor M6 is connected, and the MOS transistors M5c and M5d are connected in common and turned on and off by the clock φB0 via the amplifier A3.
It is connected to the F-controlled MOS transistor M7. The MOS transistors M6 and M7 are connected in common, and the capacitor Cs and the amplifier A
Connected to 4. In FIG. 6, Q1, Q2, Q3, Q4 are the contacts Q1, Q2, Q3, Q3,
The potential of Q4, Vout, indicates the output from the amplifier A4. In the first embodiment, the optical signal is output during a period of 1/4 period of the φ1 clock, but in the present embodiment, the horizontal signal line is divided into four and each phase is shifted by 90 °.
By shifting, the optical signal appears continuously at the output end. A sample hold function is provided by the capacitance Cs. Next, an example of an image reading apparatus to which the photoelectric conversion device is applied will be described. FIG. 7 is a schematic configuration diagram of an example of the image reading device. In the figure, a document 501 is mechanically moved in a direction indicated by an arrow Y relative to a reading unit 505. Further, reading of an image is performed by scanning in the direction of the arrow X by the image sensor 504 as the photoelectric conversion device of the present invention. First, the light from the light source 502 is reflected by the original 501, and the reflected light is reflected by the imaging optical system 5.
03, an image is formed on the image sensor 504. As a result, carriers corresponding to the intensity of incident light are accumulated in the image sensor 504, photoelectrically converted, and output as image signals. This image signal is converted into a digital signal by the AD converter 506, and is taken into a memory in the image processing unit 507 as image data. And shading correction,
Processing such as color correction is performed and transmitted to the personal computer 508 or a printer. When the transfer of the image signal for the scanning in the X direction is completed in this manner, the original 501 relatively moves in the Y direction, and the same operation is repeated thereafter to convert the previous image of the original 501 into an electric signal and extract it as image information. Can be. [Effects of the Invention] As described above in detail, according to the subtraction circuit of the present invention, it is not necessary to use circuit components which are difficult to integrate such as a differential amplifier, and the circuit can be easily integrated. It is possible to configure a small device at a low cost.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit configuration diagram for explaining a basic configuration of a subtraction circuit according to the present invention. FIG. 2 is a timing chart for explaining the operation of the above circuit. FIG. 3 is a circuit configuration diagram of a photoelectric conversion device showing a first embodiment of the subtraction circuit of the present invention. FIG. 4 is a timing chart for explaining a first embodiment of the subtraction circuit of the present invention. FIG. 5 is a circuit configuration diagram of a photoelectric conversion device showing a second embodiment of the subtraction circuit of the present invention. FIG. 6 is a timing chart for explaining a second embodiment of the subtraction circuit of the present invention. FIG. 7 is a schematic configuration diagram of an example of the image reading device. FIG. 8 is a partial circuit configuration diagram showing one configuration example of a subtraction circuit used in a conventional sensor device. S1: connection terminal to the first signal source, S2: connection terminal to the second signal source, M1, M2
, M3, M4: MOS transistors, P1, P1: contact, C: capacitor, A1: amplifier, φA, φB, φC: clock.

Claims (1)

Claims: (1) An optical sensor, a first signal source for outputting a signal at the start of accumulation of the optical sensor, and a second signal source for outputting an optical signal at the end of accumulation in the optical sensor First switch means connected to the first signal source; second switch means connected to the second signal source; and the first switch means and the second switch means. Capacitance means commonly connected to the output side; input-side reset means for selectively connecting the input side of the capacitance means to a predetermined reset potential; and selectively setting the output side of the capacitance means to a predetermined potential. Output-side potential setting means for connecting, and resetting the input-side potential of the capacitance means by the input-side reset means,
Thereafter, one of the first signal source and the second signal source is supplied to the input side of the capacitance means while the output side of the capacitance means is set to a predetermined potential by the output side potential setting means. Then, by supplying the other signal to the input side of the capacitance means, the difference between the signal from the first signal source and the signal from the second signal source is obtained from the output side of the capacitance means. And control means for connecting the potential of the input side of the capacitance means to the reset potential again by the input-side reset means, whereby an optical signal free of fixed pattern noise is accurately output from the output side of the capacitance means. A subtraction circuit characterized in that: (2) The subtraction circuit according to claim 1, wherein the first signal source and the second signal source have buffer means.