JP2531151B2 - Driving method of active matrix liquid crystal display panel - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a driving method of an active matrix liquid crystal display panel.

[Prior Art and Problems Thereof] In recent years, some liquid crystal television receivers use an active matrix liquid crystal display panel (hereinafter abbreviated as a TFT panel) as a display unit. Conventionally, this TFT panel is driven as follows. Figure 6 shows
1 shows a general pixel array state of the TFT panel 1. A plurality of pixels 2, 2, ... Are arranged in a matrix on the TFT panel 1, and a TFT (thin film transistor) is formed in each of the pixels 2, 2 ,.
Then, the TFT provided in each of the pixels 2, 2, ...
, Each gate electrode is connected to the gate lines 3, 3, ... In each row, and each drain electrode is connected to the drain line 4 in each column.
4, ... Then, the gate lines 3, 3, ...
Has an odd line connected to the left terminal 5a and an even line connected to the right terminal 5b. In addition, the drain wire 4,
4, the odd dots are connected to the upper terminal 6a, and the even dots are connected to the lower terminal 6b.

The equivalent circuit of each pixel portion in the TFT panel 1 is generally shown in FIG. That is,
The gate line 3 is connected to the gate electrode of the TFT 7, and the drain line 4 is connected to the drain electrode of the TFT 7. Then, the source electrode of the TFT 7 is connected to one end of a parallel circuit composed of a capacitor C _LC and a resistor R equivalently indicating the liquid crystal portion, and the other end of the parallel circuit is connected to a common drive power source.

In the above structure, the drain line 4 receives data of a certain voltage level sampled by a display drive circuit (not shown). In this case, the TFT7 is off during the period when the gate pulse is not input to the gate line 3,
Data input to the liquid crystal part is prohibited. However, when the gate pulse shown in FIG. 8 (a) is input to the gate line 3, the TFT7 is turned on only during the period when the pulse is at high level, and the liquid crystal portion, that is, the one end A of the capacitor C _LC. Data is input to. This allows the capacitor C
_LC is charged rapidly. After that, when the gate pulse becomes low level, the TFT7 is turned off again and “C _LC × R”
A discharge circuit having a time constant of is formed. As a result, the electric charge charged in the capacitor C _LC is discharged through the resistor R until the next gate pulse is given, and the voltage level gradually decreases as shown in FIG. 8 (b). The time t _A that this capacitor C _LC is discharging is the time when the shutter of a pixel is open, and if there is a red filter on this pixel, that pixel is red during the time t _A. Looks as.

The above is the basic operation principle of the TFT panel, and FIG. 9 shows the discharge and lighting states of the pixel in which the TFT image may be displayed. First, the normal interlaced scanning in FIG. 9 will be described. First, the drain wire 3
The polarity of the video signal input as data is inverted every frame. Secondly, a signal called CLR is input to the gate side display drive circuit, and the gate pulse is input to the gate line 3 only during the period when this signal is low level. However, in this case, the level of the common voltage V _COM is assumed to be the value of the substantially central voltage of the inverted polarity.
That is, in the video signal input as data, an AC waveform is given to the liquid crystal divided into the positive side and the negative side with respect to the level of the common voltage V _COM . Fig. 9 (5)
(6) shows the state of discharge in this case.
This series of operations is shown as "charging to capacitor C _LC = writing data (W)" and "discharging from capacitor C _LC = holding data (H)" for each field.
It is a figure (7) (8). In this case, "W / H" means that the data write W and the data hold H coexist. That is, as shown in FIG. 10, for example, in an odd field, the n-th data writing time is only the time when the n-th line is selected, and the n + 1-th data writing time is n. The second one is already holding H of data. Therefore, during this period, both data writing W and data holding H are performed.

Then, FIG. 9 (9) shows the selection of the odd and even lines as a certain four dot block. In this case, a white circle indicates data writing W, and a shaded circle indicates data holding H.

FIG. 9 (10) shows the dot block shown in FIG. 9 (9) as brightness. This Fig. 9 (10)
As is clear from this, the interlaced scanning method has the brightest brightness at the beginning of each field, and then
The brightness gradually decreases and becomes darkest immediately before moving to the next field. Therefore, in each field, bright and dark luminances are alternately repeated to cause luminance unevenness, which is perceived as flicker.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an active matrix liquid crystal display panel capable of uniforming the intensity of luminance between pixels on a TFT panel and reducing screen flicker on a television image. It is an object of the present invention to provide a driving method of the.

SUMMARY OF THE INVENTION The present invention provides a method for driving an active matrix liquid crystal display panel in which a plurality of pixels are arranged in a matrix and each pixel is selectively driven through a drain line and a gate line, and video data is field-by-field. The gate drive circuits of the odd line and the even line are alternately operated every two fields while being inverted. For example, in the first one field, positive side data is selected and held for the gate line, and in the next one field, negative data is selected and held. Side data is selected and stored,
This data retention is continued for the next two fields, and dot blocks of intermediate luminance level are set every other field.

Further, according to the present invention, a dot block having an intermediate luminance level is set every other field, the connection on the drain side is divided into an odd line and an even line, and the connection is performed for every two fields. The lighting order of is changed.

First Embodiment of the Invention Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a simplified illustration of the connection state between the pixels of the TFT panel 10 used in this embodiment. Each of the pixels 11, 11, ...
TFT is provided. The gate line 12 for supplying the gate pulse to each of these TFTs is an odd line G1, G3, G5.
Is connected to the first gate drive circuit 13a, and the even line G
2, G4 are connected to the second gate drive circuit 13b. Then, the drive timing CLR′1 is input to the first gate drive circuit 13a, and the drive timing CLR′2 is input to the second gate drive circuit 13b. In the drain line 14 that supplies data to the drain electrode of the TFT, odd dots D1 and D3 are connected to the first drive circuit 15a, and even dots D
2, D4 are connected to the second drive circuit 15b. Drive circuit 15
Video data and inverted signals are input to a and 15b. The inversion signal is a signal that inverts the level of the video data input to the drive circuits 15a and 15b for each field.
The TFT panel 10 connected as described above is shown by the same equivalent circuit as in FIG.

Next, a scanning method of the TFT panel 10 connected as described above will be described with reference to the timing chart of FIG. When the display video data is input to the drive circuits 15a and 15b, the drive circuits 15a and 15b output the video data by an inversion signal or in each field as shown in FIGS. , Every time the vertical synchronizing signal φv is given. The drive timing signals CLR'1 and CLR'2 input to the gate drive circuits 13a and 13b are shown in FIGS.
Invert every frame as shown in.

Then, in the equivalent circuit shown in FIG. 7 for these signals, the potential at point A changes as follows. First, consider the drive timing signal CLR'2, that is, the time t0 of an even field as a reference. The drive timing signal CLR'2 is at the low level for two fields from the time t0, and the input data is sampled. Data on the positive side is selected in the first field, and data on the negative side is selected in the second field. Further, data holding starts in the next field, but this holding operation is performed for two fields. In this case, in the data holding state, as shown in (5) and (6) of FIG. 2, the voltage value in the latter half field is lower than that in the first field, and therefore the brightness of the pixel is also reduced. It is falling. When this is quantitatively calculated, the voltage change in the case of discharge can be generally expressed by the following equation.

V (t) = V ₀ exp (−t / RC) (1) where V ₀ : initial value RC: time constant, for example, 70 msec.

Next, when "1 field = 16.7 msec" is set, it is calculated by what percentage the voltage V2 after the lapse of 2 fields is lower than the voltage V1 after the passage of 1 field. Than - ((16.7 × 2) / RC) ... (4) (3) (4) V 1 = V 0 e × p (-16.7 / RC) ... (3) V 2 = V 0 e × p Therefore, from the above formula (2), (1- (V2 / V1)) 100 ≈ 20%, and the voltage value is reduced by about 20%.

2 (7) and (8) show the data holding time H in the odd line and the even line in consideration of the above calculation results.
The holding time H1 in one field in the first half and one in the second half
It is shown separately for the holding time H2 in the field.

FIGS. 2 (9) and (10) show the ON / OFF state of each pixel and the change in luminance with the change in time, with four blocks including the selection of odd lines and even lines.
In the dot blocks, white circles indicate data writing W, and shaded circles indicate data holding H. In this case, in the data holding H, three diagonal lines and one diagonal line are shown, but the three diagonal lines indicate that the liquid crystal shutter opens more than one and the image is bright.

In this embodiment, as can be seen from FIG. 2 (10), dot blocks having an intermediate luminance level are set every other field, whereby the overall luminance level is made uniform and flicker is eliminated. It can be significantly reduced.

Second Embodiment of the Invention Next, a second embodiment of the present invention will be described. In this embodiment, the connection on the gate side is the same as that of the embodiment shown in FIG. 1, but the connection on the drain side is arranged every other pixel and the number of drain lines is doubled. That is, as shown in FIG. 3, in the drain line 14, the odd dots D1 _A and D3 _A of the odd lines and the even dots D2 _A and D4 _A of the even lines are provided to the first driving circuit 15a for the pixels 11, 11 ,. Connect and connect even dots of odd lines D1 _B and D3 _B and odd dots of even lines D2 _B and D
4 _B is connected to the second drive circuit 15b. Then, a drive timing signal CLRA that is inverted every frame is given to the first drive circuit 15a, and a drive timing signal CLR whose phase is 180 ° different from the timing signal CLRA is given to the second drive circuit 15b.
Giving B. Further, the video data and the inverted signal are input to the drive circuits 15a and 15b. Drive circuit 15
The a and 15b output data only when the drive timing signals CLRA and CLRB are low level, respectively. Further, the gate drive circuits 13a and 13b are arranged such that G1 → G2 → G3 during one frame.
→ It is set to output the gate pulse in the order of G4 → G5.

FIG. 4 shows the operation timing in the embodiment of FIG. As can be seen from the timing chart of FIG. 4, this embodiment has an intermediate luminance level every other field as in the first embodiment, and has odd and even dots on the gate line 12 for each frame. The lighting order of is changed.

Now, referring to FIG. 3, for example, the drive timing signal CLRA
Is low level, the pixel A is selected by the first drive circuit 15a on the drain side, and the second drive circuit 15b selects pixel B when the drive timing signal CLRB becomes low level next. On the other hand, the gate drive circuits 13a and 13b are
The gate line 12 is selected in the order of G1 → G2 → G3 → G4 → G5. Therefore, in each field, the pixel on the gate line 12 is
There is no state in which all the pixels on one horizontal line are in the data writing W or the data holding H, and the states of the data writing W and the data holding H coexist. This makes it the fourth
It is possible to turn on / off the dot block as shown in FIG. 13 and the luminance level time change becomes uniform as shown in FIG. 4 (14).

In the embodiment shown in FIG. 3, the TFT panel 10 in which the pixels 11, 11, ... Are arranged in a matrix is used, but in addition, for example, as shown in FIG. The positions may be shifted by 1/2 dot and arranged in a delta shape. The other structure in FIG. 5 is the same as that of the embodiment in FIG. By shifting the pixel position in this way, the drain line 14 can be easily connected. In each of the above embodiments, the video data and the inversion signal are input to the drive circuits 15a and 15b to invert the video data in the drive circuits 15a and 15b. It is also possible to create inverted video data and input this video data to the drive circuits 15a and 15b.

As described in detail above, according to the present invention, the video data is inverted for each field, and the gate drive circuits for the odd lines and the even lines are alternately operated for every two fields.
For the gate line, for example, in the first one field, positive side data is selected and held, in the next one field, negative side data is selected and held, and this data holding is continued for the next two fields. Then, since the dot block of the intermediate brightness level is set every other field,
The overall brightness level can be made uniform to reliably reduce flicker.

Further, according to the present invention, a dot block having an intermediate luminance level is set every other field, the connection on the drain side is divided into an odd line and an even line, and the connection is performed for every two fields. Since the lighting order of is changed, the overall brightness level can be made more uniform, and a good screen without flicker can be obtained.

[Brief description of drawings]

1 to 5 show an embodiment of the present invention. FIG. 1 is a view showing a pixel array and a connection state of a TFT panel in the first embodiment of the present invention, and FIG. 2 is a view showing the same embodiment. FIG. 3 is a timing chart for explaining the driving method, FIG. 3 is a diagram showing a pixel array and a connection state of the TFT panel in the second embodiment of the present invention, and FIG. 4 is a timing for explaining the driving method in the same embodiment. Chart, Figure 5 shows the TFT shown in Figure 3.
FIG. 6 is a diagram showing a pixel array and a wiring state when the panel wiring is simplified, FIG. 6 is a diagram showing a general pixel array and a wiring state of a TFT panel, and FIG. 7 is an equivalent of each pixel portion in FIG. FIG. 8 is a diagram showing a circuit, FIG. 8 is a signal waveform diagram for explaining the basic operation of the TFT panel, and FIGS.
7 is a timing chart for explaining an operation when a television image is displayed on the TFT panel shown in the figure. 10 …… TFT panel, 11 …… Pixel, 12 …… Gate line, 13a,
13b …… Gate drive circuit, 14 …… Drain wire, 15a, 15b
...... Drain side drive circuit.

Claims (2)

(57) [Claims] 1. A method of driving an active matrix liquid crystal display panel, wherein a plurality of pixels are arranged in a matrix form, and each pixel is selectively driven through a drain line and a gate line. Is inverted for each field, and the gate drive circuit for the odd lines and the gate drive circuit for the even lines of the gate lines are alternately operated for every two fields forming each frame. One data on the negative side is selected and held, and in the next one field, the other data on the negative side or the positive side is selected and held, and this data holding is continued for the next two fields. The active-matrix is characterized in that a dot block with an intermediate brightness level is set in the latter half of the field. Trix LCD display panel driving method. 2. A method of driving an active matrix liquid crystal display panel, wherein a plurality of pixels are arranged in a matrix form, and each pixel is selectively driven through a drain line and a gate line, and display video data for driving the drain line. The level of is reversed for each field, and the connection on the drain side of each pixel is divided into an odd line and an even line for each column and connected.
Pixels of odd line odd dots and even line even dots are driven as a pair by the first drive circuit, and pixels of odd line even dots and even line odd dot are driven as a pair by the second drive circuit, and 1
The drive circuit and the second drive circuit are alternately operated for every two fields forming each frame, and in the first one field, either the positive side data or the negative side data is selected and held, and the next one
In the field, the other data on the negative side or the positive side is selected and held, and this data holding is continued for the next two fields, and a dot block with an intermediate luminance level is set in the latter half field of each frame, A method for driving an active matrix liquid crystal display panel, wherein the lighting order of odd dots and even dots on a gate line is changed for each frame.