JP2526633B2 - Phase synchronization circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a phase synchronization circuit, and particularly to a phase synchronization control technique in the case where there is a change in the average frequency of an input signal to be phase synchronized, but there is a change in the phase. And a configuration technology of a phase locked loop circuit not including a loop filter.

(Prior Art) Phase Locked Loop (Phase Locked Loop)
The symbol "L" is generally configured as shown in FIG. 14 (when the input signal is a pulse train signal) and FIG. 16 (when the input signal is a sine wave signal). In Figure 14, this
The PLL is a phase comparator (PC) 102, a low pass filter (LPF) 103, and a voltage controlled oscillator (VCO) 104.
And an input pulse 601 to be phase-synchronized to the input terminal 101, which is composed of a frequency divider (FD) 105.
Is applied. Further, the PLL in the case where the input signal is a sine wave signal has a configuration in which the FD 105 in FIG. 14 is omitted as shown in FIG. Since both circuits operate in substantially the same manner, the operation of the PLL shown in FIG. 14 will be described below with reference to FIG.

The input pulse 601 is, for example, as shown in FIG.
It consists of a pulse train with a constant average frequency and no change in its pulse phase, which is applied to one input of the PC 102.
Also, the output pulse 602 applied to the other input of PC102
Is generated by the FD105 as described below,
It is assumed that the phase relationship with the input pulse 601 is as shown in FIG.

The PC 102 compares the phase between the input pulse 601 and the output pulse 602 and, for example, as shown in FIG.
When the phase of the output pulse 602 is delayed with respect to 1, it has a positive polarity and has a negative polarity when the phase is advanced and has a pulse width of the phase difference.
Form a PC output pulse 603 and send it to LPF 103.

The LPF103 has a PC output pulse 60
VCO control voltage according to the pulse width and polarity of each pulse of 3
Form 604 and send it to VCO 104.

As shown in FIG. 15 (e), the VCO 104 has a VCO control voltage 604
Generates a pulse train with a frequency according to the VCO output 605
To FD105.

The FD 105 counts the number of pulses of the VCO output 605 one by one, generates one pulse when the count value reaches the value N, and supplies it as the output pulse 602 to the other input of the PC 102, and at the same time, newly generates it. The counting operation of the number of pulses of the VCO output 605 is started. The output pulse 602 is the VCO output 605 as shown in FIG.
It is generated every time the number of pulses of N becomes the value N.

In summary, in this PLL, the PC output pulse 603 corresponding to the phase difference between the output pulse 602 obtained by dividing the VCO output 605 and the input pulse 601 is smoothed by the LPF 103, and the VCO control voltage 60
By applying 4 to the VCO 104, the oscillation frequency of the VCO 104 is controlled.

As a result, the oscillation frequency of the VCO 104 matches N times the average frequency of the input pulse 601, and the phase of the output pulse 602 matches the phase of the input pulse 601.

Similarly, in the PLL shown in FIG. 16, the phase of the VCO output 605 is matched with the phase of the input sine wave signal 801.

(Problems to be Solved by the Invention) As described above, in the conventional PLL, the oscillation frequency of the VCO, that is, the phase of the output signal is controlled so that the phases of the input signal and the output signal match. Therefore, when the average frequency of the input signal is not changed but the phase is changed, the phase synchronization control operation is performed again, and the state can be shifted to the phase synchronization state with the same contents as before the change.

However, in the transition process, there is a problem that the oscillation frequency of the VCO fluctuates and the phase information that the phase of the output signal has is lost.

This is clear when considering the following control mode. That is, for example, using the PLL shown in FIG. 14 to generate an output pulse at a fixed point on the rotating shaft that rotates at a substantially constant cycle,
When the output of the VCO is used as a pulse train for dividing one rotation of the rotating shaft into N, when the phase synchronization control is performed again as described above, the fixed point position of the rotating shaft and the fixed point position of the rotating shaft are set until the new phase synchronized state is settled. The rotation angle position becomes unknown. This problem may occur when two rotation detectors having different pulse phases are used as the input pulse generation source and both are switched and used.

Furthermore, it is desirable to digitize the PLL in order to improve its reliability and stability. However, conventional PLL
It is indispensable to include a loop filter (LPF) in order to obtain a predetermined response / synchronization performance, but this LPF function cannot be realized by a simple circuit configuration as in the case of an analog circuit. Therefore, the previously proposed digital
In some PLLs, the function of LPF is realized by a probability control filter, but this tends to complicate the circuit configuration, such as requiring a memory that accumulates a large number of observation quantities, and the probability conversion characteristics. There is a problem that it is very difficult to design.

The present invention has been made in view of such problems,
The purpose is to synchronize the phase of the output signal with the input signal where the average frequency does not change but the phase may change. It is an object of the present invention to provide a phase locked loop circuit having a phase correction means for holding the phase in a phase locked state before the change, and to provide a phase locked loop circuit having a new structure not including a loop filter.

(Means for Solving the Problem) In order to achieve the above object, the phase locked loop circuit of the present invention has the following configuration.

That is, the phase locked loop circuit of the present invention (first invention) includes a phase comparator for comparing the phases of an input signal and a feedback signal, and a low pass filter for receiving the output of the phase comparator to form a predetermined control voltage. And a voltage controlled oscillator which receives the predetermined control voltage and generates an output signal which is a basis of the feedback signal, and which operates in order to synchronize the phase of the output signal with the phase of the input signal. The input signal consists of a sinusoidal analog signal or a pulse train signal whose average frequency does not change but whose phase may change, and when the phase of the input signal changes, a predetermined phase correction amount It is characterized in that phase correction means for operating the feedback signal is provided.

The phase synchronization circuit of the present invention (the second invention) includes a phase difference detection means for detecting a phase difference between the input signal and the feedback signal;
Adder means for adding a period comparison signal to the phase difference signal and outputting a control signal consisting of a predetermined control amount; and an oscillating operation at a period according to the control amount upon receipt of the control signal and a basis of the feedback signal. Oscillator means for generating an output signal; cycle difference detection means for detecting a cycle difference between the differentiated input signal and the cycle comparison signal; and integration of the cycle difference signal to form the cycle comparison signal And a period comparison signal generating means.

(Operation) Next, the operation of the phase locked loop circuit of the present invention configured as described above will be described.

First, the operation of the phase locked loop circuit according to the first aspect of the invention will be described. That is, the input signal consists of a sinusoidal analog signal or a pulse train signal in which the average frequency does not change but the phase may change, but when there is a change in the phase of the input signal, the phase correction means changes the phase. The feedback signal is operated with a predetermined phase correction amount corresponding to the change.

As a result, the output signal of the voltage controlled oscillator can hold the phase in the phase locked state before the change. In addition,
The configuration method of the phase correction means differs depending on whether the input signal is an analog signal or a pulse train signal.

As described above, according to the phase locked loop circuit of the first aspect of the present invention, the phase comparison is performed between the input signal and the signal in which the output signal is phase-corrected according to the phase of the input signal. Even if a change occurs, there is an effect that the phase-locked state before the change can be held without re-performing the phase-locked control.

Next, the operation of the phase locked loop circuit according to the second aspect of the invention will be described with reference to FIG. 1 (linear model diagram).

The phase locked loop circuit of the second invention is, as shown in FIG. 1, arranged in a main closed loop of →→→→→.
The → → sub closed loops are installed in parallel, and the loop filter (LPF), which was conventionally required, is not included as a substance. Where is the input signal (consecutive value)
The phase comparison characteristic of the comparator that performs the phase comparison between the phase θ _i (t) of the output signal and the phase θ _o (t) of the output signal constitutes the phase difference detection means as a whole. Is a loop gain (K _β ) included in the main closed loop, is a cycle (cycle comparison signal) ω _o (t) generated in the sub closed loop based on the detected phase difference
The adding means for outputting a control signal for controlling the oscillation cycle in addition to is the oscillating means for oscillating in a cycle proportional to the input control amount.

Further, is a differentiator that differentiates the phase θ _i (t) of the input signal to detect the cycle ω _i (t) of the input signal, and is the cycle ω _i (t) of the input signal and the cycle comparison signal ω _o (t). The comparator that performs a period comparison with the period comparison characteristic has a period comparison characteristic, and constitutes a period difference detection means as a whole.

Is a loop gain (K _α ) included in the sub closed loop,
Is a period comparison signal generating means for integrating the inputted period difference to form a period comparison signal of period ω _o (t).

In the above configuration, in the sub-closed loop, if the output ω _i (t) of the differentiator is ω _i (t) = θ _i (t), then ω _i (s) = sθ _i (s) (1) Therefore, the output ω of the period comparison signal generating means
_o (t) is Can be expressed as Then, the phase θ _o (t) of the output signal generated in the main closed loop is Can be expressed as Therefore, by rearranging the equations (1), (2), and (3), (K _α s + K _β s + K _α K _β ) θ _i (s) = (s ² + K _α s + K _β s + K _α K _β ) θ _o (S) ……
(4) and the transfer function H (s) is Becomes

That is, this phase locked loop circuit is a free-running oscillation cycle of the oscillating means that oscillates a cycle synchronized with the cycle of the input signal generated by the sub closed loop at a phase synchronized with the phase of the input signal generated by the main closed loop. It was done like this.

By the way, as is well known, the transfer function H (s) of a phase locked loop including a conventional loop filter (LPF) is The loop filter is a perfect integral active filter and its transfer function F (s) is In the case of, the formula (6) has the same form as the formula (5).
This indicates that the phase locked loop circuit according to the second aspect of the present invention functions similarly to the conventional secondary loop phase locked loop circuit including the loop filter.

Thus, according to the phase locked loop circuit of the second invention, the conventional secondary loop phase locked loop circuit including the loop filter is
Since it can be realized with a configuration that does not include a loop filter as an entity, it is possible to realize a digitized phase locked loop circuit with a simple circuit configuration and easy design without using a stochastic control filter that has a complicated circuit configuration and is difficult to design. effective.

(Examples) Examples of the present invention will be described below with reference to the drawings. The same names as those in the conventional circuit shown in FIGS. 14 and 16 are designated by the same reference numerals and the description thereof is omitted.

FIG. 2 shows a phase locked loop circuit according to the first embodiment of the present invention. The circuit of the first embodiment is the PLL shown in FIG. 16 provided with a phase correction signal generator 1 and an adder 2 as phase correction means.

The phase correction signal generator 1 receives the input sine wave signal 801 applied to the input terminal 101, monitors the phase relationship between the reference phase internally set and the input signal, and responds to the phase change of the input signal. Generate a predetermined phase correction signal according to the phase difference, and apply it to one input of the adder 2.

The adder 2 adds or subtracts the phase correction signal given to one input and the VCO output 605 given to the other input, and gives it to the PC 102 as a feedback signal.

As a result, the phase offset of the input sine wave signal 801 before and after the phase change is canceled, and the VCO output 605 maintains the phase locked state before the phase change.

Next, FIG. 3 shows a phase lock circuit according to a second embodiment of the present invention. The circuit of the second embodiment corresponds to the circuit of the first embodiment, and the phase correction signal generating circuit is used as the phase correction means.
21 and a delay circuit 22 are provided.

The phase correction signal generation circuit 21 is for the case where the input sine wave signal 801 applied to the input terminal 101 has two kinds of phase states, and the first correction element 21a and the second correction element 21b.
And a switch 21c for receiving the switching signal applied to the input terminal 23 to select one of the first correction element 21a and the second correction element 21b, extracting a predetermined phase correction signal from the selected correction element 21a, and giving it to the delay circuit 22. Equipped with.

The delay circuit 22 appropriately advances or retards the phase of the VCO output 605 according to the input phase correction signal, and uses it as a feedback signal in the PC.
Give to 102. The switching signal applied to the input terminal 23 is a signal indicating the time point when the phase of the input signal is changed.

As a result, the VCO output 605 can be held in the phase locked state before the phase change, as in the first embodiment.

Next, an application example of the circuit of the second embodiment will be described with reference to FIGS. 4 and 5. This makes the operation of the circuit of the second embodiment more apparent. It should be noted that this application example can be similarly applied to the circuit of the first embodiment.

FIG. 4 shows a configuration example of a despin controller used in a spin-stabilized artificial satellite.

This despin control device includes a phase synchronization circuit 31, an angle control unit 32, and a despin control unit 33. This basic configuration is similar to that of the conventional despin control device, except that there are two sets of the sun sensors 34, that is, the sun sensors 34a and 34b, and that the phase synchronization circuit 31 relates to the present invention. Regarding the conventional despin control device, for example, the documents "Sakigake (1985-001-A)" and "Suisei (1985-073-
A) "Despan antenna control system" (ISS Science Report No. 34 ISSN 0285-2853), reference "PLANET-A despan antenna control device" {NEC Technical Report Vol.37 No.2 (Showa 59) (February year)}.

This despin control device obtains a signal that follows the spin motion of the satellite by a sun sensor 34 fixed to the side wall of the satellite body, and based on this, the rotation speed of a despin unit 35 including a directional antenna, an observation sensor, an optical sensor, and the like. By controlling the rotation of the spin unit 35 to rotate the spin motion of the satellite body in the opposite direction at the same speed, and by constantly detecting and correcting the phase in the pointing direction, the despin unit 35 is moved in a fixed direction in the inertial space (for example, It is a device that keeps pointing in the direction of the earth. The phase synchronization circuit in the conventional despin device is designed to be phase-synchronized with the output signal of one sun sensor.

The sun sensors 34a and 34b are, for example, illuminance meters and generate a sunlight detection signal proportional to the incident angle. Now, consider a reference signal (FIG. 5 (a)) whose time origin is 0 phase, and represent this as v = sinωt (8), and input signal # 1 which is the output signal of the sun sensor 34a.
The FIG. 5 (b) phi ₁ from the reference signal as shown in - [theta] ₁ [ra
If it has a delay phase of d], it can be expressed as v ₁ = asin (ω ₁ t + θ ₁ −φ ₁ ) ... (9). Further, the input signal # 2, which is the output signal of the sun sensor 34b, is changed from the reference signal to φ ₂ − as shown in FIG. 4 (c).
If it has a delay phase of θ ₂ [rad], it can be expressed as v ₂ = asin (ω ₂ t + θ ₂ −φ ₂ ) ... (10). Note that θ ₁ and θ ₂ are slight deviations (errors). Here, regarding the input signals # 1 and # 2, it is assumed that the input signal # 2 has a delay phase of q [rad] with respect to the input signal # 1. These input signals # 1 and # 2 are input to the switch 38.

A switching signal d as shown in FIG. 5 (d) is applied to the input terminal 39. This controls the switching of the switch 38 and the switch 21c of the phase correction signal generating circuit 21, and both switches are switched at the time point P. Regarding the switch 38, the input signal # 1 is selected before the time point P, and the input signal # 2 is selected after the time point P. As a result, as shown in FIG. 5 (e), the input signal having the phase change at the time point P is selected. e
Is applied to the input terminal 101.

On the other hand, regarding the switch 21c, before the time point P, the first
The correction element (phase amount φ ₁ [rad]) is selected and the second correction element (phase amount φ ₂ [rad]) is selected after the time point P (FIG. 5 (g)). These are the phase correction amounts for the VCO output signal f (Fig. 5 (f)),
Previously, a phase delay of only the phase amount φ ₁ [rad], and after the time point P, a phase delay of the phase amount φ ₂ [rad] is given to the delay circuit 22 to bring to the VCO output signal f.

Now, assuming that the VCO output signal f before time P is v ₁ ′ = bcos (ω ₁ ′ t + θ ₁ ′) (11), this signal causes a phase delay of φ ₁ [rad] in the delay circuit 22. Then, v ₁ ″ = bcos (ω ₁ ′ t + θ ₁ ′ −φ ₁ ) ... (12) This becomes the phase comparison signal (Fig. 5 (h)) which is the feedback signal of PC102, so In PC102 before P, the same equation (12) as equation (9) is added, The signal indicated by is obtained. Then, since the harmonic component of the first term of the equation (13) is removed by the LPF 103, the VCO output voltage v is the gain of the PC 102 is K, and the transfer function of the LPF 103 is F (s).
Then, = K · F (s) sin {(ω ₁ −ω ₁ ′) t + θ ₁ −θ
_It is expressed as ₁ ′} (14). Here, in Expression (14), ω ₁ = ω ₁ ′
Then, if θ ₁ −θ ₁ ′ is sufficiently small, then = K · F (s) (θ ₁ −θ ₁ ′) (15) That is, the VCO output 605, that is, the VCO output signal f is synchronized with the reference signal (Fig. 5 (a)).

The VCO output signal f and the phase comparison signal after the time point P are as shown in FIGS. 5 (f) and 5 (h), and the equation (15) is obtained by the same procedure.

Next, the angle control unit 32 delays the VCO output signal f with the delay phase of α [rad] set at the angle signal input terminal 40, and then the direction control signal represented by the following equation (16) is obtained. i is formed and sent to the despin controller 33 (FIG. 5 (i)).

v ₁ = bcos (ω ₁ ′ t + θ ₁ ′ −α) (16) The despin control unit 33 outputs the feedback signal represented by the following equation (17) generated by the drive mechanism of the despin unit 35 to the direction control signal i. The drive signal k is sent to the despin unit 35 so as to synchronize j (FIG. 5 (j)).

v = csin (Ωt + Θ−α) (17) Here, the angular frequencies ω, ω ₁ ′, and Ω are the same, and θ ₁ , θ ₁ ′, and Θ are sufficiently small. Can be seen to rotate so as to follow the signal in which the reference signal (FIG. 5 (a)) is delayed by α [rad].

Thus, the sun sensors 34a and 34b are switched and used, and even if the input signals having different phase offsets with respect to the reference signal are alternately input, the directing direction of the despin unit 35 is always directed in a constant direction. I can continue.

Next, FIG. 6 shows a phase locked loop circuit according to a third embodiment of the present invention. This third embodiment circuit is for a case where the input signal is a pulse train signal, and is for the conventional circuit shown in FIG.

That is, in this phase synchronization circuit, an analog switch (SW) 106 is provided between the phase comparator (PC) 102 and the low-pass filter (LPF) 103 as a phase correction means, and a frequency divider A register 107 and a comparator 108, which are holding circuits, are provided in the feedback path between the FD) 105 'and the PC 102.

The average frequency of the input pulse 202 applied to the input terminal 101 is substantially constant, but the pulse phase may change. For example, as shown in FIG. 7 (b), when the phase is changed at the point P, the average frequency of the input pulses # 1, # 2 and # 3 before the change and the input pulse # 4, after the change. The average frequencies of # 5 and # 6 are substantially constant. This input pulse 202 is input to PC 102 and AND gate 113.
It is one of the inputs.

The hold signal 201 applied to the input terminal 109 is normally at a low level as shown in FIG. 7 (a), but is at a high level for a predetermined period near the time P when the phase of the input pulse 202 changes. Is a signal. That is, a low level period is a non-hold period, and a high level period is a hold period. In the illustrated example, the hold period starts after an appropriate time t has elapsed after the falling edge of the input pulse # 3, and the hold period ends in response to the falling edge of the input pulse # 4. It is the input pulse that exists inside. The hold signal 201 is given to the SW 106 as a control signal and is also the other input of the AND gate 113.

As a result, the AND gate 113 generates a timing signal 203 (FIG. 7C) at the timing of occurrence of the input pulse # 4 existing within the hold period of the hold signal 201, and sends it to the register 107.

Unlike the case where the other input is shown in FIG. 14, the PC 102 is the phase comparison pulse 206 formed by the comparator 108 according to the present invention.

The SW 106 receives the hold signal 201 and becomes conductive only during the period when the signal level is low, that is, during the non-hold period, and outputs the output of the PC 102 (comparison result pulse 207) to LPF1.
Report to 03. Also, during the period when the signal level is high, that is, the hold period, it becomes non-conducting state, and PC102 and L
Open between PF103.

As a result, in the hold period, the discharge path of the capacitor in the LPF 103 is cut off, so that the charge stored in the capacitor is at the start of the hold period, and it is held at a substantially constant amount during the hold period. .
That is, the LPF 103 performs a smoothing process on the comparison result pulse 207 every time the comparison result pulse 207 is input to form the predetermined VCO control voltage 208 in the non-hold period, as described in FIG.
During the hold period, VC at the start of the hold period
The O control voltage 208 is held and output.

As a result, the pulse train, which is the VCO output 209 sent from the VCO 104 to the output terminal 112 and the FD 105 ', is held at a frequency substantially the same as the frequency at the start of the hold period during the hold period.

The FD105 'has the same VCO output as the FD105 shown in FIG.
One pulse is generated every time the number of pulses of N reaches the value N, and it is sent to the output terminal 110 as the output pulse 205. However, in the present invention, from the value “0” in the process of repeatedly counting the value N. Each count value up to the value "N-1" (this is called count data) is sent to the register 107 and the comparator 108, respectively. As is clear from the above description, since the VCO output 209 in the hold period does not change and the state before the phase change is held,
The generation timing of the output pulse 205 is the same as that before the phase change even after the phase change.

The register 107 latches the count data in response to the timing signal 203, and holds and outputs it as the latch data 204 to the comparator 108. The FD 105 'outputs count data "0" at the time of output pulse generation. On the other hand, the timing signal 203 is generated in response to the input pulse existing within the hold period. Therefore, the latch data 204 is count data within the period from immediately after the output pulse 205 is generated to the first input pulse after the output pulse is generated and within the hold period. This indicates a time position corresponding to the phase difference between the output pulse 205 generated before the phase change and the input pulse 202 immediately after the phase change when the input pulse has a phase change without correction.

In FIG. 7, as shown in FIG.
Among them, the input pulses # 1, # 2 and # 3 represent those in the non-hold period after the phase change not shown. The input pulse # 4 is immediately after the new phase change, and the input pulses # 5 and # 6 are those during the non-hold period after the new phase change.

Therefore, as shown in FIG. 7D, the latch data 204 is changed from the data A based on the phase change performed outside the figure to the data B based on the new phase change, but the data B
Indicates the phase difference B between the output pulse 205 immediately before the start of the hold period and the input pulse # 4 existing within the hold period. The same applies to the data A.

The comparator 108 compares the count data output from the FD 105 'and the latch data 204 held and output by the register 107 for coincidence or non-coincidence, and at the time when they coincide, that is, the output pulse 205 is delayed by the time indicated by the latch data 204. The phase comparison pulse 206 is generated at different time positions and sent to the other input of the PC 102 and the output terminal 111. In the example of FIG. 7, the latched data 20 before the time P when there is a phase change.
Since the content of 4 is the data A, the phase comparison pulse 206 is generated at the time position delayed by the time A from the output pulse 205. Further, after the time P when there is a phase change, the input pulse # 4 immediately after the change is delayed by the time B from the output pulse 205 immediately before the change, and this is the content of the latch data 204 (data B). The comparison pulse 206 is time P
For each of the subsequent output pulses 205, time B
It occurs at a time position delayed by only. Note that the phase comparison pulse
As shown in FIG. 7 (f), the 206 occurs even within the hold period, but this occurs in the circuit of the embodiment and can be easily removed.

The PC 102 forms a comparison result pulse 207 (FIG. 7 (g)) based on the phase difference between the input pulse 202 and the phase comparison pulse 206, and sends it to the SW 106.

By repeating the above operation, the phase of the phase comparison pulse 206 is controlled so as to match the phase of the input pulse 202. Here, even if there is a change in the phase of the input pulse 202, the phase relationship between the input pulse 202 and the phase comparison pulse 206 does not change significantly, so that it is possible to quickly shift to a new phase locked state.

Next, an application example of the phase locked loop circuit according to the third embodiment of the present invention will be described with reference to FIGS. 8 and 9. FIG. 8 is an example of a circuit for acquiring a pulse (spin synchronization pulse) synchronized with the spin motion of the satellite in a spin-stabilized artificial satellite. That is, this is a circuit example for acquiring the input signal of the angle control section 32 in the application circuit shown in FIG.

In FIG. 8, two star sensors (stellar detection devices) 301a and 301b are attached to the satellite body (not shown), and both are switched and used. The star sensors 301a and 301b rotate together with the satellite body to scan the sky of the sensor field of view and generate a pulse when a star is present in the sensor field of view.

Since the satellite body is in a spin motion, a pulse train corresponding to the spin motion is generated, and the stars in the sensor field of view are changed with the change of the direction of the spin axis, and the phase of the pulse train is changed. When this pulse train is referred to as a star pulse 401, this star pulse 401 has a phase changed within a period of one spin as shown in FIG. The star pulse 401 is sent to the pulse detector 302 and one input of the AND gate 307, respectively. In FIG. 9A, the left side of the time point P shows the star pulse based on the star sensor 301a, and the right side shows the star pulse based on the star sensor 301b.

That is, at the time point P, the star sensor 301a was switched to the star sensor 301b.

The phase locked loop (PLL) 304 according to the present invention shown in FIG. 6 has an input pulse 407 applied to the input terminal 101 and a hold signal 406 applied to the input terminal 109.
Further, the phase comparison pulse 408 sent to the output terminal 111 is given to the time gate generator 305, and the VCO output 410 sent to the output terminal 112 and the output pulse 409 sent to the output terminal 110 are shown as spin synchronization pulses. Taken out.

As described above, since the VCO output 410 is a pulse train that divides each pulse interval of the output pulse 409 into N, the output pulse 40
9 is used as a pulse generated when a fixed point on the satellite body coincides with a certain direction of inertial space.
Output 410 is used to identify each position within the interval. Therefore, when switching between the star sensors 301a and 301b for use, the content of the spin synchronization pulse should not be changed in the process of switching.

In view of the fact that the star pulse 401 has a phase change, the time gate generator 305 sets the time gate 403 in FIG. 9 in order to extract one star pulse 401 at a predetermined timing position synchronized with the average spin period. As shown in (c), it is generated at fixed time intervals and is applied to one input of the pulse detector 302 and one of the OR gates 308, respectively. As shown in FIG. 9C, the time gate 403 has a pulse width of 2ΔT and 2π−T from the leading edge of the phase comparison pulse 408.
₀ (a fixed time shorter than the average spin period) -A pulse that rises after ΔT.

The pulse detector 302 generates a reset pulse 404 if the star pulse 401 exists on the time gate 403, and a set pulse 405 if it does not exist. The reset pulse 404 becomes the reset signal of the flip-flop 309. Further, the set pulse 405 is applied to the flip-flops 309 and 31.
It becomes a set signal of 0.

In the example shown in FIG. 9, as shown in FIG.
There is a pulse on the time gate 403 during the use period of the star sensor 301a, and there is no pulse on the time gate 403 immediately after the point P when the star sensor 301a is switched to the same 301b. A pulse exists on the time gate 403 after one spin cycle. Therefore, the reset pulse 404 is generated during the use period of the star sensors 301a and 301b (Fig. 9 (d)), and the set pulse 405 is generated in the transient state near the time point P when both are switched (the ninth pulse). Figure (e)).

The output terminal of the flip-flop 309 is connected to the other input of the OR gate 308, the input terminal 109 of the PLL 304 and one input (control terminal) of the AND gate 311 respectively. The flip-flop 309 receives the reset pulse 404 and holds the output at “0”, while receiving the set pulse 405 and holds the output at “1”. That is, the set pulse 405 is input to the output of the flip-flop 309, and then the reset pulse 4 is input.
The period until 04 is input is "1", which is the hold period for the PLL 304 (Fig. 9 (f)), and the AND gate 311 is set in the prohibited state within this hold period.
Further, the OR gate 308 outputs the time gate 403 as it is during the non-hold period when the output of the flip-flop 309 is “0”, but during the hold period, the output is set to “1” during that period. The output of this OR gate 308 is AND gate 3
The other input of 07.

The AND gate 307 extracts one pulse on the time gate 403 from the star pulse 401 during the non-hold period and sends it to the transmission circuit 303. On the other hand, in the hold period, the start time of the hold period is at the time position before the switched star sensor 301b generates the first star pulse 401, as shown in FIG.
The star pulse 401 generated by the star sensor 301b is sequentially input to the delay circuit 303 from the first pulse to the third pulse.

The delay circuit 303 delays the input pulse by a certain time T ₀ and sends it to the other input (signal terminal) of the AND gate 311 and the clear terminal CL of the flip-flop 310.

The AND gate 311 outputs the output of the delay circuit 303 to the OR gate 312 only while the output of the flip-flop 309 is “0”.
To one of the inputs. During the hold period in which the output of the flip-flop 309 is "1", the AND gate 311 is set to the prohibition state as described above, so that the star pulse 401 does not pass through the AND gate 311 within this hold period.

On the other hand, in the flip-flop 310, since the set pulse 405 is input to the set terminal SET, the output changes from “1” to “0” in response to the set pulse 405, and then the output of the delay circuit 303 is input to the clear terminal CL. In response, it goes from "0" to "1". Here, among the outputs of the delay circuit 303, what is effective in the flip-flop 310 is the changed star pulse 401.
It is the first of these to occur.

In the pulse generation circuit 313, in response to the output of the flip-flop 310 changing from “0” to “1”, the star pulse is generated.
Generates a pulse of approximately the same width as the pulse width of each 401 pulse,
It is applied to the other input of OR gate 312. That is,
The pulse generated by the pulse generation circuit 313 is the star pulse 401 generated first after the change is delayed by a certain time T ₀ . The OR gate 312 uses the outputs of the AND gate 311 and the pulse generation circuit 313 as input pulses 407 for the PLL3.
It is sent to the input terminal 101 of 04. Therefore, the pulse generation circuit 3
The pulse generated by 13 is the input pulse existing within the hold period.

In PLL304, output pulse 409 immediately after the start of the hold period
To the input pulse 407 within the hold period becomes the changed phase difference, and the phase comparison pulse 408 is generated according to the phase difference. The phase comparison pulse 408 is generated at the same time position as the input pulse in the hold period, but this occurs in the circuit of the embodiment as described above and does not affect the circuit operation. As described above, even if the phase of the input pulse 407 changes, the output pulse 409 and the VCO output 410 are not affected by it.

As described above, according to the phase locked loop circuit of the third embodiment of the present invention, a phase comparison pulse based on the phase difference between the input pulse and the output pulse of the FD 105 'is formed, and this phase comparison pulse is phased to the input pulse. Since they are synchronized, it is possible to reliably shift to a new phase-locked state even if the phase of the input pulse is changed. Also, when there is a change in the phase of the input pulse, the control voltage of the VCO 104 is held at the value at the time of the change for a predetermined period, so during the transition process to transition to a new phase-locked state. Also, the oscillation frequency of the VCO 104 can be maintained at the same frequency as before the change without changing, and the output pulse of the FD 105 'can be generated at the same timing as before the change without losing the phase information held up to that time.

Next, FIG. 10 shows a phase locked loop circuit according to a fourth embodiment of the present invention. The circuit of the fourth embodiment comprises the phase locked loop circuit shown in FIG. 1 formed of a digital logic circuit. First
In FIG. 10, is a period comparator, is an α multiplier, is an up / down counter, is a set value converter, is a frequency divider,
Is a phase comparator, is a β multiplier, is an up / down counter, is a digitally controlled oscillator, is a frequency divider, and is a fixed clock generator.

The input signal consists of a pulse train of pulses that occur at time X _i (i = 0,1,2, ...), and its period x _i is x _i = X _i −X _i-1 (18). This input pulse train is applied to one input of the period comparator and one input of the phase comparator, respectively.
The output of the set value converter is supplied to the other input of the period comparator via the frequency divider, and the output of the digitally controlled oscillator is supplied to the other input of the phase comparator via the frequency divider. To be done.

In the present embodiment, the set value converter and the digital control oscillator are composed of a rate multiplier, and a clock of a constant frequency f (Hz) generated by a fixed clock generator is supplied to this rate multiplier as an operation clock. As is well known, in the rate multiplier, the frequency of the input clock is f (Hz) and the frequency of the output clock is f '.
(Hz), the number of bits for rate input is n, and the setting value is A (decimal), Therefore, the frequency f'of the output clock changes according to the set value A. At this time, since the pulse intervals of the output clock are not equal, a frequency divider and the same are provided so that comparison pulses are supplied to the period comparator and the phase comparator at equal intervals. Here, the set value A
Is the output (A _i ) of the up / down counter in the set value converter and the output (B _i ) of the up / down counter in the digitally controlled oscillator.

First, the following operation is performed in a loop that goes around the period comparator from the latter stage. The period comparator is composed of a counter (a), a register (b) and a parallel-serial converter (c) as shown in FIG. 11, for example. Assuming that the input pulse train is of positive polarity, for example, the counter (a) is set to "0" at the trailing edge of each pulse (that is, the period is detected by differentiating operation), and then the period until the next pulse is input. During the period (that is, the period of the period x _i ), the output pulse train of the frequency divider is used as a clock to perform a stepwise operation, and the count value is output in parallel to the register (b). Here, the period y _i of the output pulse train of the frequency divider
Is y _i = A _i · N · τ (20), where N is the division ratio and τ (τ = 1 / f) is the period of the input clock of the set value converter. The register (b) is the parallel output value of the counter (a) at the leading edge of each pulse of the input pulse train.
It latches (that is, detects a period difference) the digital quantity indicating x _i −y _i , and outputs it to the parallel-serial converter (c). As a result, a serial digital signal indicating the period difference x _i −y _i is output from the parallel-serial converter (c) to the α multiplier.

The α multiplier forms a signal α (x _i −y _i ) consisting of a predetermined number of pulses by multiplying the input serial digital signal indicating the period difference x _i −y _i by α (0 <α ≦ 1), and outputs it. Output to up / down counter.

In the up / down counter, the input signal α (x _i −
When the content of y _i ) is y _i −x _i , up count operation is performed,
When y _i <x _i , down count operation is performed, and the count value A _i (0 <A _i ≦ 1), which is the integral value, is output to the rate input of the set value converter and the set input of the up / down counter Output to SET. Here, the rate input A _i is a digital amount that controls the cycle of the output clock of the set value converter, but in the set value converter, the information does not change between the input and the output, but the up / down counter Since the output "signal for comparing periods (period comparison signal)" is a parallel signal, it is converted into a serial signal which is convenient for period comparison by the period comparator.

That is, the up / down counter constitutes the period comparison signal generating means. The rate input A _i is A _i = A _i-1 + α (x _i −y _i ) ... (21).

In this way, the setting value converter outputs a clock with the frequency of the input clock reduced for the convenience of the value of the rate input A _i , and divides this output clock by N to obtain a pulse train of period y _i and a period x _{i. The} period y _i is converged to the period x _i by comparing the period with the input pulse train of _i and controlling the rate input A _i of the set value converter by following the period difference x _i −y _i .

Next, the following operation is performed in a loop that goes around the phase comparator after the phase comparator. The phase comparator comprises, for example, as shown in FIG. 12, a counter (d), a register (e) and a parallel-serial converter (g). The counter (d) is a cyclic counter that performs a stepping operation using the output pulse train of the frequency divider as a clock and repeatedly counts from the value “0” to a predetermined value, and the count value is output in parallel to the register (e). .. Here, the output pulse train of the frequency divider has a frequency division ratio of N,
Set the period of the input clock of the digitally controlled oscillator to τ (τ
= 1 / f), the period z _i is z _i = B _i · N · τ (22) and the phase Z _i is Is. Therefore, the period z _i is z _i = Z _i −Z _i-1 (24). The register (e) latches the count value output in parallel by the counter (d) in response to the input of each pulse of the input pulse train, and outputs it to the parallel-serial converter (g). For example, it is assumed that the counter (d) repeatedly counts from the value “0” to the value “M”, and when the counter (d) counts and outputs the value “M”, the time of the corresponding pulse in the output pulse train of the frequency divider ( That is, the phase) is set to Z _i , Z _{i + 1} , Z _{i + 2} , ..., and these correspond to the occurrence times (ie, phases) X _i , X _{i + 1} , X _{i + 2} , ... Of the input pulse train. If the contents of the latch output of the register (e) have the value “M”, it means that the phase difference is “0”, and the contents of the latch output have a predetermined value before and after the value “M”. When it is, it means that it is a digital quantity showing a predetermined phase difference X _i −Z _i . The parallel digital signal indicating the phase difference X _i −Z _i is converted into a serial digital signal by the parallel-serial converter (g) and further multiplied by β (0 <β ≦ 1) by the β multiplier, and the signal has a predetermined number of pulses. It becomes β (X _i −Z _i ) and is input to the up / down counter.

The up / down counter sets the set value A _i applied to the set input SET and inputs the input signal β
When the content of (X _i −Z _i ) indicates a phase delay of phase Z _i with respect to phase X _{i, the} up count operation is started from the set value A _i (A _i = A _i-1 + α (x _i −y _i )). On the contrary, when the phase is advanced, a down-count operation is performed and the count value B _i (B _i = A _i-1 + β (X _i −
Z _i )) to the rate input of the digitally controlled oscillator. That is, the up / down counter constitutes an adding means. Here, the rate input B _i is a digital quantity that controls the period and phase of the output pulse train of the digitally controlled oscillator.

In this way, the digitally controlled oscillator generates the output pulse train of the cycle and phase set by the rate input B _i , and divides the output pulse train by N to obtain the pulse phase of the cycle z _i .
Z _i is compared with the pulse phase X _i of the input pulse train, and the phase difference X _i
A value B _{i + 1} (B _{i + 1} = A _{j obtained} by correcting the synchronization cycle A _j by following −Z _i
By setting + β (X _i −Z _i )) as the rate input, the phase Z _i
To converge to the phase X _i .

Note that the synchronization cycle A _j is at the time when the phase difference correction is executed, and is i when the digital PLL is in the synchronization state.
= J, and i ≠ j in the asynchronous state.

FIG. 13 shows an example of operation characteristics of the embodiment circuit (digital PLL) described above. Fig. 13 shows the results of computer simulation, where α = 0.05, β = 1, and the frequency of 1/2 Hz when the frequency of the output pulse train of the frequency divider is 1/3 Hz as the initial free-running oscillation frequency of the digitally controlled oscillator. The response process to an input pulse train is shown. As shown in FIG. 13, after the phase difference X _i −Z _i continues to cycle slip,
That is, it can be understood that after the flicker process, when the period difference (steady period deviation) x _i −y _i becomes a certain value or less, the lock-in range is entered, and thereafter the synchronization state is maintained.

The measurement conditions of the operating characteristics shown in FIG. 13 are, for example, when a signal synchronized with the spin motion of this artificial satellite is generated from a sun sensor attached to the side wall of the rotating artificial satellite,
An artificial satellite that was initially rotating at 20 rpm changed its rotation speed to 30r.
This is equivalent to increasing to pm.

Next, since it can be easily inferred from each of the first to third embodiments, it is omitted in the drawing. However, also in the circuit of the fourth embodiment, the phase correction means for operating the feedback signal in the feedback path from the digitally controlled oscillator to the phase comparator. By providing the above, it is possible to obtain a phase-locked loop circuit having the same functions as those shown in the first to third embodiments.

(Effect of the Invention) As described in detail above, according to the phase locked loop circuit of the present invention, the phase comparison is performed between the input signal and the signal obtained by phase-correcting the output signal according to the phase of the input signal. Therefore, even if a phase change occurs in the input signal, there is an effect that the phase-locked state before the change can be held without redoing the phase-locking control.

Further, according to the phase locked loop circuit of the present invention, a conventional secondary loop phase locked loop circuit including a loop filter can be realized with a structure that does not actually include a loop filter, so that the circuit structure is complicated and difficult to design. There is an effect that it is possible to realize a digitized phase locked loop with a simple circuit configuration and easy design without using a control filter.

[Brief description of drawings]

FIG. 1 is a linear model diagram of a phase locked loop circuit according to claim 5, FIG. 2 is a block diagram of a phase locked loop circuit according to a first embodiment of the present invention, and FIG. 3 is a second block diagram of the present invention. FIG. 4 is a block diagram showing the configuration of a phase locked loop circuit according to the embodiment, FIG. 4 is a block diagram showing the configuration of an artificial satellite despin control device to which the circuit according to the second embodiment is applied, FIG. 5 is a timing chart of the application example circuit, and FIG. FIG. 7 is a configuration block diagram of a phase locked loop circuit according to a third embodiment of the invention, FIG. 7 is a timing chart of the third embodiment circuit,
FIG. 8 is a configuration block diagram of an application example circuit of the third embodiment circuit, FIG. 9 is a timing chart of the application example circuit, and FIG. 10 is a configuration block diagram of a phase synchronization circuit according to the fourth embodiment of the present invention. 11 is a block diagram showing an example of the period comparator in FIG. 10, FIG. 12 is a block diagram showing an example of the phase comparator in FIG. 10, and FIG. 13 is a circuit diagram of the fourth embodiment. Operating characteristic diagram, FIG. 14 is a block diagram of the configuration of a conventional phase locked loop circuit when the input signal is a pulse train signal, FIG. 15 is a timing chart of the conventional example circuit, and FIG. 16 is a sine wave signal as the input signal. It is a block diagram of a conventional phase locked loop circuit. 1,21 …… Phase correction signal generator, 2 …… Adder, 22,303…
… Delay circuit, 31,304 …… Phase locked loop (PLL), 32 ……
Angle control unit, 33 …… despin control unit, 34,34a, 34b …… sun sensor, 35 …… despin unit, 102 …… phase comparator (P
C), 103 ... Low-pass filter (LPF), 104 ... Voltage controlled oscillator (VCO), 105,105 '... Frequency divider (FD),
106 …… Analog switch (SW), 107 …… Register, 10
8 …… Comparator, 110,111,112 …… Output terminals, 301a, 3
01b …… Star sensor, 302 …… Pulse detector, 305 ……
Time gate generator, 307,311 …… And gate, 308,3
12 …… OR gate, 309,310 …… Flip-flop, 313
...... Pulse generation circuit ...... Period comparator ...... α multiplier ...... Up-down counter ...... Set value converter ...... Divider ...... Phase comparator ...... β multiplier
...... Up-down counter, ...... Digitally controlled oscillator, ...... divider, ...... fixed clock generator.

Claims (5)

(57) [Claims] 1. A phase comparator for comparing the phases of an input signal and a feedback signal, a low pass filter for receiving an output of the phase comparator to form a predetermined control voltage, and a circuit for receiving the predetermined control voltage. A phase-locked circuit having at least a voltage-controlled oscillator for generating an output signal which is a basis of the feedback signal, the phase-locked circuit operating to synchronize the phase of the output signal with the phase of the input signal; Is composed of a sinusoidal analog signal or a pulse train signal whose phase may change, and a phase correction means for continuously operating the feedback signal with a predetermined phase correction amount when the phase of the input signal changes. A phase synchronization circuit characterized by being provided. 2. The phase locked loop circuit according to claim 1, wherein the input signal comprises the analog signal, and the phase correction means outputs a predetermined phase correction signal in response to a phase change of the input signal. A phase correction signal generator to generate;
A phase-locked circuit provided in a feedback path between the phase comparator and the voltage-controlled oscillator, and an adder that adds a phase correction signal to an output signal of the voltage-controlled oscillator and uses it as the feedback signal. . 3. The phase locked loop circuit according to claim 1, wherein the input signal is the analog signal, and the phase correction means receives a switching command indicating that the input signal has a phase change. A phase correction signal generator which selects one of various preset phase correction amounts and outputs it as a phase correction signal; a phase provided in a feedback path between the phase comparator and the voltage controlled oscillator A phase-locked loop circuit comprising: a delay circuit, which performs advance / delay of a phase angle on an output signal of a voltage-controlled oscillator based on a correction signal and uses the delay process as the feedback signal. 4. The phase locked loop circuit according to claim 1, wherein the input signal is a pulse train signal, and the phase correction means is provided between the phase comparator and the low pass filter. A hold period showing a time region near the time when a phase change occurs in an input pulse which is a signal, and a non-hold period showing a remaining time region including at least a region where the input pulse having the phase change exists Hold signal consisting of and is transmitted from the outside, the output of the phase comparator is transmitted to the low pass filter only in the non-hold period, and in the hold period, the control voltage at the start of the hold period is held and output to the low pass filter. A switch for controlling the output of the voltage-controlled oscillator that outputs a pulse train having a frequency corresponding to the control voltage A frequency divider that counts the number of pulses in the pulse train and generates an output pulse each time the count value reaches a predetermined value; the first input pulse immediately after the output pulse is generated and after the output pulse is generated. A holding circuit for storing and holding a count value of the frequency divider within a period up to that within the hold period in response to the input pulse within the hold period; a count value for storing and holding by the hold circuit And a comparator for generating a phase comparison pulse as the feedback signal when the frequency divider and the count value counted by the frequency divider are compared with each other, and the count value is counted. 5. A phase difference detecting means for detecting a phase difference between an input signal and a feedback signal; an adding means for adding a period comparison signal to the phase difference signal and outputting a control signal having a predetermined control amount; Oscillating means for receiving a control signal and oscillating in a cycle according to the control amount to generate an output signal which is a basis of the feedback signal; and a cycle difference between the differentiated input signal and the cycle comparison signal. A phase synchronization circuit comprising: a cycle difference detecting means for detecting; and a cycle comparison signal generating means for integrating the cycle difference signal to form the cycle comparison signal.