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JP2526007B2 - 半導体チップへの電気的相互接続を形成するための構造および方法 - Google Patents

半導体チップへの電気的相互接続を形成するための構造および方法

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Publication number
JP2526007B2
JP2526007B2 JP5058439A JP5843993A JP2526007B2 JP 2526007 B2 JP2526007 B2 JP 2526007B2 JP 5058439 A JP5058439 A JP 5058439A JP 5843993 A JP5843993 A JP 5843993A JP 2526007 B2 JP2526007 B2 JP 2526007B2
Authority
JP
Japan
Prior art keywords
layer
substrate
copper
germanium
electrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5058439A
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English (en)
Other versions
JPH0621140A (ja
Inventor
マイケル・ジョン・ブラディー
カーチス・エドワード・ファレル
スン・クオン・カン
ジェフリー・ロバート・マリノ
ドナルド・ジョーゼフ・ミカルセン
ポール・アンドリュー・モスコウィッツ
ユージン・ジョン・オサリバン
テレンス・ロバート・オトゥール
サンパス・プルショタマン
シェルドン・コール・リーレイ
ジョージ・フレデリック・ウォーカー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
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Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH0621140A publication Critical patent/JPH0621140A/ja
Application granted granted Critical
Publication of JP2526007B2 publication Critical patent/JP2526007B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
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    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

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Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、電気導体がシリコン及
びゲルマニウムを含有する材料を含む表面を有する、電
子デバイスに関する。さらに詳しくは、ワイヤが前記の
表面にワイヤ・ボンディングされ、はんだが前記表面に
フラックスなしで接着されている。さらに詳しくは、シ
リコン及びゲルマニウムを含有する材料表面は、金属層
のスタック中で中間層として、また金属層と誘電層の間
で中間層として使用される。さらに詳しくは、本発明の
材料は電気的に付着され、転写される。最も詳しくは、
本発明の材料はシリコンとゲルマニウムの共有化合物で
ある。
【０００２】
【従来の技術】金属銅は非常に良好な導電性を有する。
その結果、将来の電子デバイス用パッケージにおける相
互接続用金属被覆としての銅の開発に対する努力に現在
広い関心が寄せられている。ＶＬＳＩ（超大規模集積回
路）の回路密度の上昇は、チップ上、及びチップが電気
的に相互接続されるパッケージ基板上の電気導体に対し
て、ますます厳しい要求を課してきている。回路密度の
上昇は電気導体寸法の減少に対応するが、この寸法の減
少は抵抗と電流密度の増加につながり、それによって、
信号損失が増大し、電子デバイス及び電子パッケージ上
の電気導体への電気移動による損傷が助長される。これ
らの問題は、銅または金をベースとする高導電性金属被
覆の開発を促している。回路密度が増大すると、多数の
相互接続段が必要となり、したがって複雑な工程によっ
て達成される完全に平面状の構造が必要となる。
【０００３】低誘電率による容量性寄生電流を減らし、
また平面化が可能なままで残留応力を減らすには、新素
材が必要になる。こうした新しい素材及び工程は、特に
導体として銅を使用する場合、電気導体上の腐食を促進
する可能性のある既存の導電性材料と化学的融和性がな
いことがある。腐食防止のために保護層を加える場合に
は、寸法が減るので、銅線の高い導電性を維持すること
がますます困難になる。保護層はスペースをとるので、
高導電性の銅に与えられるスペースが減る。
【０００４】
【発明が解決しようとする課題】金は一般に使用される
耐食性材料である。半導体チップ上やパッケージ基板上
の電気導体は、腐食防止のために通常は金で被覆する。
しかし、金は高価な材料であり、電子デバイスや基板の
製造コストを抑えなければならない場合は、抵抗率が低
くて耐食性の良い他の材料に代えなければならない。例
えば、半導体チップのパッドをパッケージ基板のパッド
に電気的に相互接続するための、複数の導電性リードを
有するリード・フレームは、一般に金の被覆を有する銅
で形成されている。さらに、最新のテスト・プローブを
記載している、参照により本明細書にその教示を組み込
んだ同時係属の米国特許出願第０７／５８３６２１号に
は、半導体デバイスのテストのために金で被覆した銅Ｔ
ＡＢリード・フレームを使用することが記載されてい
る。
【０００５】
【課題を解決するための手段】本発明者等は、本発明の
Ｓｉ及びＧｅ材料が金に代わるはるかに安価な代替品を
提供することを発見した。金は耐食性であり、大気中の
酸素にさらしても酸化物を形成せず、はんだが良く付
く。本発明のＳｉ及びＧｅ材料は、金と同様に実質上耐
食性であり、表面に酸化物を形成せず、はんだが良く付
く。
【０００６】さらに金は、ワイヤ・ボンディングまたは
超音波ボンディングによってワイヤが電気的に接続され
る、半導体チップまたはパッケージ基板接点のパッド上
で一般に使用される表面金属被覆である。意外なこと
に、本発明のＳｉ及びＧｅ材料は金と同様にワイヤ・ボ
ンディングに適した表面をもたらすことがわかった。
【０００７】さらに金は、はんだ、特に鉛亜鉛はんだを
接着できる表面を提供するために、半導体チップまたは
パッケージ基板接点のパッド上を金属被覆するために一
般に使用される表面である。金ははんだが良く付く表面
である。意外なことに、本発明のＳｉ及びＧｅ材料はは
んだが良く付くことがわかった。
【０００８】本発明のＳｉ及びＧｅを含む材料の諸特性
は、金の特性に匹敵する。この材料は半導体チップや半
導体チップ・パッケージ基板中の導電性パッドや導線な
ど、多層金属構造中の中間層として有用である。
【０００９】本発明の素材は耐酸化性であり、酸素に対
する拡散隔膜として働くので、酸化物の形成を防止する
ための中間障壁層として有用である。
【００１０】本発明の上記その他の目的、特徴、及び利
点は、下記の詳細な説明と添付の図面及び特許請求の範
囲から明らかになろう。
【００１１】本発明の広い態様は、シリコン及びゲルマ
ニウムを含有する材料を含むメタラジ構造を有する、半
導体チップ・パッケージ構造である。
【００１２】本発明のパッケージ構造の特定の態様で
は、含シリコン材料及び含ゲルマニウム材料がケイ化物
及びゲルマニウム化物である。
【００１３】本発明のパッケージ構造の他の特定の態様
では、ワイヤが、本発明のＳｉ及びＧｅを含む材料の表
面にワイヤ・ボンディングされる。
【００１４】本発明のパッケージ構造の他の特定の態様
では、はんだマウンドが、本発明のＳｉ及びＧｅを含む
材料の表面にはんだ付けされる。
【００１５】本発明のパッケージ構造の他の特定の態様
では、選択的に被覆されたリード・フレームが、本発明
のＳｉ及びＧｅを含む材料の表面を有する。このリード
・フレームは半導体チップへの電気的相互接続をもたら
す。
【００１６】本発明の他の広い態様は、ゲルマニウムを
含む材料の無電解めっきである。
【００１７】本発明の他の広い態様は、本発明のＳｉ及
びＧｅを含む材料の転写である。シリコンまたはゲルマ
ニウムの層は、柔軟な支持基板によって支持される。
【００１８】
【実施例】Ｃ４などのはんだマウンドの付いたチップを
パッケージ基板上のパッドなどの基板に接合するために
は、パッドがボンディングのためにはんだで濡れる表面
メタラジを有することが望ましい。アルミニウム／銅
（Ａｌ／４％Ｃｕ）は、シリコン・チップまたはパッケ
ージ基板の代表的な最新の配線層である。Ｃ４はＡｌ／
Ｃｕ表面層に直接はんだ接合できない。後述のように、
はんだ付け可能なパッドは、中間の接着層及び障壁層を
覆う上部Ａｕ層を有する。例えばＣｒ／Ｃｕ／Ａｕは典
型的なはんだ付け可能な表面メタラジ構造であり、その
うちＣｒ層は接着層であり、ＣｕはＡｕとＣｒ層の下の
金属層の間の相互拡散を防止する障壁層である。しか
し、Ｃｕを使用する場合には２つの問題がある。Ｃｕは
再加工サイクルを支持できるのに十分な厚さがなければ
ならず、ＣｕはＡｕと相互拡散することができ、はんだ
中に溶解する。はんだ付けされた構造を再加工するに
は、構造全体をはんだの融解温度に加熱するが、こうし
た温度では強い相互拡散が発生する可能性がある。
【００１９】Ａｕは、Ｃｕを酸化から保護し、テスト・
プローブとボンディングのための良好な表面を提供する
という意味がある。しかし、長い間貯蔵したり温度変化
にさらされたりすると、ＣｕとＡｕが相互拡散を起こ
し、表面に達したＣｕが酸化する可能性がある。この酸
化した表面が、チップＣ４の基板接点パッドへの適切な
リフロー接合を妨げる。酸化物はまた、プローブ・テス
トに高い接触抵抗をもたらす。表面酸化物の問題を解消
するための接合の１つの解決策は、チップ接合作業また
はテストの前に追加のフラックス・ステップによってウ
ェハまたは基板を処理して、表面酸化物を除去すること
である。これには費用と時間がかかる。
【００２０】この問題の１つの解決策は、本発明のシリ
コンまたはゲルマニウムを含む材料を使用することであ
る。こうした材料の例としては、Ｃｕ3Ｇｅ、Ｎｉ3Ｇ
ｅ、Ｃｕ3Ｓｉ、Ｎｉ3Ｓｉなどの共有化合物がある。本
明細書では、パッケージング応用例、例えばチップの接
合のための、本発明のシリコン及びゲルマニウムを含む
材料の使用について記載する。また、図１に示すような
接点パッド用の上表面（ＴＳＭ）メタラジのための、シ
リコン及びゲルマニウムを含む材料の簡略化された製造
工程も記載する。
【００２１】図１は、電子デバイス、例えば基板２の表
面６上に配置された電気導体４を有する半導体チップま
たはパッケージ基板などの半導体を示す。電気導体４
は、接点パッドでも導線でもよく、どちらも一般にＡｌ
／Ｃｕ材料で作ることができる。電気導体４の周囲に、
電気導体４の露出領域１０を残して不動態化層８があ
る。不動態化層８は、有機材料または無機材料、例えば
ポリイミド、ＳｉＯ2またはＳｉ3Ｎ4とすることができ
る。シリコンまたはゲルマニウムを含む材料１２の層
が、領域１０に接触して配置される。層１２の厚さは約
１０００〜１００００Åとすることができる。
【００２２】低い抵抗率を有する本発明のシリコンまた
はゲルマニウムを含む材料のパターンの選択された付着
は、下記の工程を利用することによって実施できる。例
えば、基板上での標準の半導体処理を使用してフォトレ
ジストまたはリフトオフ・ステンシルを生成することが
でき、あるいはモリブデン・マスクを基板の上に置くこ
とができる。高周波スパッタリングまたはイオン・ビー
ム・クリーニングを使用して、接触パッドの表面からア
ルミニウム酸化物や銅酸化物などの酸化物を除去するこ
とができる。例えば、８００Å程度のゲルマニウム膜を
室温で真空蒸着し、続いて厚さ１２００Å程度の銅の薄
膜を付着する。次いでホスト基板を１００℃で１時間加
熱し、これによって固相反応で合金Ｃｕ3Ｇｅを形成す
ることができる。次いで基板を室温に冷却し、真空を切
り、アセトン中でフォトレジスト・ステンシルを剥が
し、あるいはモリブデン・マスク技法を採用した場合
は、モリブデン・マスクを除去する。この結果得られる
オーム性接触は、５〜１２マイクロオーム−ｃｍの範囲
の公称値の抵抗率で酸化されない。この材料の抵抗率は
純銅のそれよりもいくらか高いが（２マイクロオーム−
ｃｍ超）、銅はＣｕ3Ｇｅの形で安定しており、シリコ
ン基板中に拡散することはない。より厚い、またはより
薄い薄膜では、上記の値を調節して所要の厚さを得るこ
とができる。厚さ約１０００〜１００００Åのゲルマニ
ウム化銅薄膜が最も好ましい。ひどく酸化されたパッド
を持つ基板の場合には、基板に厚さ１０００ÅのＣｒま
たはＴｉの薄い層を加えることが望ましい。Ｃｒまたは
Ｔｉは、高周波スパッタリングまたはイオン・ビーム・
クリーニングの後、Ｇｅ付着の前に、パッドの表面に付
着する。ＣｕとＧｅの付着の順序を逆にすることもでき
る。
【００２３】Ｃｕ3Ｇｅ合金の形成後、薄いＡｕ層を合
金の上面に付着してテスト・プローブ用のより軟らかい
接触域を準備することも望ましい。
【００２４】図２は、図１の構造の代替実施例を示す。
図１と図２で共通の参照番号は、すべて同じものを表
す。パッド４の領域１０上に、任意選択の厚さ約２００
〜２０００ÅのＣｒまたはＴｉの層１４を付着する。層
１４は接着のためのものである。層１４上に、厚さ約１
０００〜１００００Åの本発明によるゲルマニウムまた
はシリコンの層１６を付着する。層１６上に、厚さ約２
００〜２０００ÅのＡｕ、Ａｇ、Ｉｎ、Ｓｎ、またはＰ
ｂなどの軟らかい材料の任意選択層１８を付着する。
【００２５】図３は、ＣｕまたはＣｒ／Ｃｕ／Ｃｒ配線
を持つ基板の上部表面メタラジ（ＴＳＭ）のための、本
発明のゲルマニウム及びシリコンを含む材料を使用し
た、本発明の他の１実施例を示す。図１、図２、及び図
３で共通の参照番号は、すべて同じものを表す。パッド
４は、Ｃｒの下層２０、Ｃｕの中間層２２、及びＣｒの
上層２４から成る。このケースで、Ｃｕ3Ｇｅを使用す
る場合、これは、最上段の金属２４の表面２３から上述
のように銅の酸化物を取り去ることによって、あるいは
一般に使用されているフォトリソグラフィ技法を用いて
Ｃｒ／Ｃｕ／Ｃｒ構造４のＣｒの上層２４を開いて、開
口部２６からＣｕ層２２を露出させることによって、そ
れが製造できる。例えばゲルマニウムの層２８を約１６
００Åの厚さに付着し、それに続いて厚さ約１２００Å
の銅の層３０を付着する。その後、この工程は上述のよ
うに進行して、図４に示すように、層２８と３０からゲ
ルマニウム化銅層３２を形成することができる。図４は
さらに、ゲルマニウム化銅層３２にボンディングされた
はんだマウンド３４を示す。Ｃｕ3ＧｅからなるＴＳＭ
層は、従来のＣｒ／Ｃｕ／Ａｕ構造を上回る利点がいく
つかある。これはＣｒ／Ｃｕ／Ａｕと同様にはんだで濡
らすことができる。しかし、室温またはそれ以上の温度
で大気に長時間さらしても、Ｃｕ3Ｇｅ上層の濡れ性は
低下しない。したがって、本発明のゲルマニウムまたは
シリコンを含む材料で被覆したパッドは、基板をチップ
接合工程にかけるとき酸化されない。ゲルマニウムまた
はシリコンを含む層にフラックスを塗布したり、炉加熱
工程にかけて、チップ接合の前に酸化物を除去する必要
はない。この材料はまた、Ｃｕ3Ｇｅのはんだへの溶解
の少ないチップ接合及び再加工工程に役立ち、したがっ
て厚い銅を蒸着させる必要性がなくなる。
【００２６】一般に、Ｃ４はんだマウンドは、（通常は
モリブデン・マスクを介する蒸着によって）チップ・パ
ッド・アレイ上に配置される。はんだマウンドの付いた
チップは、対応するパッド・アレイを有する基板の上に
配置される。基板パッドにゲルマニウムまたはシリコン
を含むＴＳＭ層を設けて、基板パッドの表面の酸化を避
け、またフラックスを使ってＣ４をゲルマニウムまたは
シリコンを含むＴＳＭ層にはんだ付けするのを避けるこ
とができる。Ｃ４はんだ付けは、米国特許第３４２９０
４０号及び米国特許第３４０１１２６号に詳しく記載さ
れており、この両特許の教示を参照によって本明細書に
組み込む。
【００２７】シリコン上に付着したアルミニウムのブラ
ンケット被膜上に、Ｃｕ3Ｇｅブランケット被膜を付着
することによってＣｕ3Ｇｅの抵抗率を測定した。アル
ミニウム被膜を貫通する５ｍｍのストリップをエッチン
グすることによってアルミニウム被膜を絶縁した。次に
アルミニウムの上にＣｕ3Ｇｅを付着し、１００℃でア
ニールした。Ａｌ被膜は厚さ３００Åであり、Ｃｕ3Ｇ
ｅは１８７０Åであった。Ｃｕ3Ｇｅの抵抗率測定値は
１３マイクロオーム−ｃｍであった。
【００２８】先に指摘したように、Ｓｉ半導体デバイス
用にＡｌ／Ｃｕ（通常はＡｌ−４％Ｃｕ）接点メタラジ
を使用する際に遭遇する１つの問題は、付着後の熱処理
中に接点領域から隣接するＡｌ相互接続メタラジへのＳ
ｉの拡散が発生する可能性があることである。高い漏洩
電流または短絡を引き起こす可能性のあるこの問題を是
正するために、Ａｌメタラジに、Ａｌ中のＳｉの溶解度
を満足するのに必要な量（シリコン０．５重量％）より
過剰な、ある量（１．０〜１．５重量％）のＳｉを加え
る。
【００２９】問題は、アルミニウム接点メタラジの上面
に蒸着されたシリコン層がしばしば、アルミニウム中に
完全には拡散しないことである。Ａｌ表面上にシリコン
または酸化シリコンが残留する結果、アルミニウム・メ
タラジへのワイヤ・ボンディングを行うとき、「非粘
着」接続が生じる可能性がある。
【００３０】残留するシリコンまたは酸化シリコンを除
去するための技法は、Ｓｉ拡散ステップの後に接点パッ
ド表面にＲＩＥを施すことである。しかし、そうする
と、ＲＩＥ工程の後もなおシリコン及び酸化シリコンが
しばしば残存し、さらに、Ｓｉ、Ｃｕ、Ｏ、Ｃ及びＦか
ら構成される中間層が表面に形成される可能性が生じる
結果となる。
【００３１】本発明は、望ましくない表面残留物の問題
を解決するため、Ａｌメタラジの上表面にゲルマニウム
またはシリコンを含む材料を置く、接点メタラジのため
の新しい構造を提供する。本発明のＳｉを内部に拡散さ
せたＡｌ／Ｃｕ導体に、ワイヤを直接ボンディングし、
ゲルマニウム及びシリコンを含む材料の層でキャップす
ることができることがわかった。図５、６、７に、本発
明のゲルマニウム及びシリコンを含む化合物の上表面を
有する構造を製造する際の諸ステップを示す。図５、
６、７で共通の参照番号はすべて同じものを示す。
【００３２】図７の構造では、標準のＡｌ／Ｃｕ接点メ
タラジ、ならびにＣｕ単独など他のメタラジが使用でき
る。図５では、厚さ１ミクロンのＡｌ／Ｃｕ層４２が基
板４０上に付着されている。層４２上にシリコン層４４
は、通常は蒸着によって付着する。層４４の上表面にＣ
ｕの薄層４６を蒸着する。十分なＳｉを蒸着させて、本
発明による銅／シリコン材料の層を形成し、溶解度要件
を満たすためＡｌ／Ｃｕ層４２の中に拡散させるのに十
分なＳｉ（厚さ約２００Å）を残さなければならない。
Ｓｉに１５０ÅのＣｕを加えて合計約３００Åとなる。
Ｃｕ層の付着後、図５の構造を約１００〜３００℃、好
ましくは２００℃で、約１０〜６０分間、好ましくは３
０分間熱処理すると、図６の構造が形成される。これ
は、メタラジ構造５０の上表面５２上に厚さ約２５０Å
のＣｕ／Ｓｉ材料の層４８が形成されている。層４８の
下にＳｉ層５４がある。図６の構造を、３５０℃〜４５
０℃で３０分〜６０分間熱処理して、層５４中のＳｉを
Ａｌ／Ｃｕ層４２中に拡散させ、溶解度要件が満たされ
るようにする。好ましい実施例では、処理済みの構造
は、Ｓｉが０．５％拡散した厚さ約１．０ミクロンのＡ
ｌ（４％）／Ｃｕから成り、本発明に従って厚さ数１０
０ÅのＣｕ／Ｓｉ材料でキャップされている。Ｃｕ／Ｓ
ｉ材料は約６０マイクロオーム−ｃｍという低い抵抗率
を示し、ワイヤ・ボンディングのための良好な表面を形
成する。
【００３３】図７の構造で、Ｓｉは通常Ｓｉデバイスと
ともに使用され、ＧｅはＧｅデバイスとともに使用され
る。
【００３４】図８は、ワイヤ５６が表面層１８にボンデ
ィングされた、図７の構造を示す。Ａｌ、Ｃｕ、または
Ａｕのワイヤなど、通常用いられているどんなワイヤを
使用してもよい。また、熱圧着ボンディング、超音波ボ
ンディング、サーモソニック・ボンディング、レーザ・
ボンディングなど、通常用いられているどんなワイヤ・
ボンディング技術を使用してもよい。
【００３５】図９は、リード・フレーム１３０、アルフ
ァ粒子バリヤとしても働く誘電体被膜１３２、及び半導
体チップ１３４の概略分解図であり、本発明の１実施例
でのこれらの要素の空間的関係を示すものである。リー
ド・フレーム１３０は金属シート・ストック、ＴＡＢ
（テープ自動ボンディング）テープ、フレックス・テー
プなどから作成され、位置合せ孔１３６を備えている。
リード・フレームは、Ｃｕ、Ｃｕ合金、合金４２（Ｎｉ
４２％、Ｆｅ５８％）、インバール（Ｎｉ３６％、Ｆｅ
６４％）、Ａｌ、または他の何らかの適当な電気導体で
作ることができる。リード・フレーム１３０は複数のリ
ード１３８を有する。各リード１３８は１つの内端１３
９を有する。導体１３８の半導体チップ１３４の上を延
びる部分は、誘電体被膜１３２によって半導体チップ１
３４から分離されている。少なくとも、内側部分１３８
は本発明のゲルマニウム及びシリコンを含む材料で被覆
され、後述のように内側部分へのワイヤ・ボンディング
ができるようになっている。
【００３６】誘電体被膜１３２は、１７５℃を超える融
点の高分子被膜であり、ハロゲン化物やＮａ、Ｋ、Ｐを
含めた活性金属などのイオン化可能な化学種を含まな
い。米国特許第４４２６６５７号で提唱されているよう
に、誘電体被膜としてポリイミド被膜を使用することが
できる。このようなポリイミド被膜の１つにデュポン社
のＫａｐｔｏｎ（登録商標）がある。
【００３７】半導体チップ１３４は、接着層（図示せ
ず）によってリード・フレーム導体１３８に取り付けら
れる。薄い接着剤の層が、リード・フレーム導体または
チップ１３４の上部活性表面１５４に塗布される。この
上部活性表面１５４は、チップ１３４の主表面の１つで
ある。チップは通常不動態化／絶縁材料で被覆されてい
るにもかかわらず、チップへの短絡の可能性を回避する
ために、誘電性インターポーザを使用することが好まし
い。この誘電性インターポーザは、導体とチップの間に
位置するアルファ粒子バリヤ１３２とすることが好まし
い。次いで、各表面に異なる接着材を使用して接着層を
アルファ粒子バリヤ１３２の両面に貼りつけることがで
きる。
【００３８】アルファ粒子バリヤとして有効に役立ち、
同時に有効な熱伝達ができるように、誘電体被膜１３２
は約１．５〜２．０ミル（約３８〜５０ミクロン）とす
べきである。
【００３９】半導体チップ１３４を、第１接着層で誘電
体被膜１３２に取り付ける。この第１接着層は、エポキ
シ、アクリル、シリコーン、及びポリイミドの群から選
択され、シリコーンが、腐食を最小限に抑えるので好ま
しい。
【００４０】誘電体被膜１３２を、第２接着層で導体１
３８に取り付ける。この第２接着層は、エポキシ、アク
リル、シリコーン、及びポリイミドの群から選択され、
エポキシとアクリルの群から選択することが好ましい。
というのは、これらの材料を用いると、導体１３８が誘
電体被膜１３２に完全に接着され、したがって半導体チ
ップ１３４と導体１３８との間の熱伝導が強化され、リ
ード・フレーム導体１３８が半導体チップ１３４に機械
的にロックされるからである。
【００４１】十字形部材１４０がリード・フレーム１３
０の導体１３８間に設けられ、リード・フレーム１３０
に剛性を与え、半導体チップ１３４、誘電体被膜１３
２、及び導体１３８をカプセル封じしたとき、カプセル
封じ材料の流動を制限する。
【００４２】図１０は、カプセル封じ材料１４６の一部
を取り除いた、半導体チップ１３４を含むパッケージ１
４２を示す。カプセル封じの後に、図３のリード・フレ
ーム・サルベージ１４８と十字形部材１４０を取り除
く。必要に応じて、パッケージ１４２を越えて延びる導
体１３８を形成してもよい。取り除かれた十字形部材
は、図１０では１４０^に破線で部分的に示してある。
【００４３】導体１３８の厚さを最小にして、上から下
までのカプセル封じのシーリングを最大にしなければな
らない。部分線１５６でのカプセル封じの編みを最大に
すると、耐亀裂性が向上する。カプセル封じ材料内の導
体を確実にシールするには、約０．５〜１ｍｍの最小経
路長が必要だからである。
【００４４】リード・フレーム導体１３８のカプセル封
じのロッキングは、図１０に示すように、導体１３８に
鋭い角またはよじれ１５０を設けることによって達成さ
れる。リード・フレーム導体によじれを設けることによ
って、本発明のパッケージは、優れた機械的特性を維持
しながら、半導体モジュールの幅を減少させることがで
きる。というのは、パッケージ材料内のリードの長さ
が、もはやパッケージのチップとエッジの間隔によって
制限されなくなるからである。
【００４５】導体１３８は、半導体チップ１３４の表面
積の３０％〜８０％、好ましくはその最大パーセントを
覆うべきである。導体１３８は、半導体チップ１３４上
の端子パッド１５２との接触を避けるような位置にすべ
きである。この面積を最大にすると、半導体チップ１３
４の効果的な冷却強化と、導体１３８の半導体チップ１
３４表面への適切なボンディングが保証される。導体１
３８をもっと長くしてチップ１３４に達し、それに接着
するようにすると、パッケージ外部からワイヤ・ボンド
までの経路（Ｄ）が長くなり、したがって、腐食や早期
の障害を引き起こす可能性のある環境汚染物の侵入に対
する抵抗力が増す。
【００４６】端子パッド１５２を含む半導体チップ１３
４の活性層１５４から熱を除去するのは、従来技術の実
装された半導体チップで行われているように半導体チッ
プの背面から熱を除去するのよりも効果的である。
【００４７】端子パッド１５２は、ワイヤ１５８で導体
１３８に接続される。導体１３８の構成は、ワイヤ１５
８の長さが約３０ミル（約０．７６ｍｍ）未満になるよ
うにすることが好ましい。ワイヤ１５８の長さを最小限
に抑えると、実装された半導体チップの電気的性能が改
善される。
【００４８】図１０の構造を、基板（図示せず）上に取
り付け、リード１３８の外端１６２を、上記のように基
板上のパッドにはんだ付けする。図１０は、パッケージ
１４２から外側に曲がったリード１３８の外端１６２を
示す。この外端は、パッケージ１４２の下へ内側に曲が
ってもよく、このような外端は通常Ｊリードと呼ばれ
る。図１１は、図１０に示すものに類似した構造の概略
断面を示す。図１１は、チップ１８０のパッド１７８と
リード１７０の内端１７２、１７４との間にワイヤ１７
６がワイヤ・ボンディングされた、リード・フレーム１
７０を示す。チップと内端１７２、１７４は成型コンパ
ウンド１８２中にカプセル封じされ、パッケージ・チッ
プ構造１８６を形成する。リード１７０の外端１８４は
パッケージ１８６に向かって内側に曲がっている。この
曲がった外端１８４を、上述のようにはんだ１９２で基
板パッドまたは基板１９０上の接点位置１８８にボンデ
ィングすることができる。基板１９０は、印刷回路板、
金属被覆パッケージ・セラミック基板、フレックス・テ
ープなどにすることができる。
【００４９】要約すると、図９、１０、１１の発明は、
Ｃｕ3Ｇｅ、Ｎｉ3Ｇｅ、Ｎｉ3Ｓｉ、Ｃｕ3Ｓｉ、または
これらの二元化合物の他の相など適当なゲルマニウムま
たはシリコンを含む材料で被覆された、銅または他の材
料のリード・フレームから成る。Ｓｉ及びＧｅを含む材
料を形成するための工程は、適当などんなリード・フレ
ーム材料の被覆にも使用できる。リード・フレームは銅
であってはならない。被覆はボンディング・パッドの位
置に行ってもよく（スポットめっきまたはスポット被
覆）、リード・フレーム全体を覆ってもよい。Ｇｅ及び
Ｓｉを含む材料の付着は、蒸着、または電気めっきとそ
れに続く熱処理を行って、材料を形成することによって
実施できる。例えば、Ｃｕ3Ｇｅ及びＮｉ3Ｇｅは蒸着す
ることもできる。Ｃｕ3Ｇｅは電解法でめっきすること
ができる。Ｃｕ3Ｓｉは２５０℃より高い温度で表面酸
化物を形成することに留意されたい。Ｎｉ3Ｇｅは無電
解法でめっきすることができる。
【００５０】本発明のゲルマニウム及びシリコンを含む
材料は、独特の性質により、はんだ付けに代わるボンデ
ィング技法をもたらす。コンピュータ・パッケージ・コ
ンポーネントは一般に、電気的または機械的接合工程中
にさらされる可能性のある温度に関する材料上の問題に
よって制限される。しかし、高強度、高伝導性（電気的
及び熱的）接続がコンピュータ・パッケージ技術に必要
である。導体を接合するには一般にはんだ接点が使用さ
れている。しかし、はんだの使用には一般にフラックス
の塗布とそれに続く清浄化が必要である。良好な熱伝導
性や電気伝導性が必要でない場合には、２つのコンポー
ネントを接合するのに有機エポキシが使用できる。しか
しエポキシはその温度範囲が制限されている。例えば電
源など熱をもつコンポーネントには、高温に耐えうる接
合媒体が必要である。
【００５１】本発明の構造は、２つ以上のコンポーネン
トからなり、これらは、例えばＣｕ3Ｇｅなど本発明の
ゲルマニウム及びシリコンを含む材料からなる媒体によ
って、機械的、熱的に、また必要なら電気的に接合され
た、印刷回路板、フレキシブル・ケーブル、または機械
エレメントでよい。Ｃｕ3Ｇｅは、接着性及び導電性媒
体として働く。各機械エレメントは銅の表面を有し、そ
れにＣｕ3Ｇｅが接合された構造中で密着している。こ
の構造を製造するには、接合すべきエレメントの各表面
を、銅表面をもつように製造する。印刷回路板及びフレ
キシブル・ケーブルは通常そのような形で製造される。
表面が銅でない場合には、例えばめっきや蒸着など適当
な手段で銅を付着する。続いて、ゲルマニウム層を、例
えばめっきや蒸着など適当な手段で少なくとも表面の１
つに付着する。銅の表面を清浄化し、一般には１００〜
２００℃の中温で、一般に１０kpsi台の圧力でゲルマニ
ウム表面と密着させる。この結果、図１２の構造が形成
される。
【００５２】図１２では、基板２００上にメタラジ構造
２０２があり、その表面２０４にＣｕまたはＮｉがあ
る。図９のリード１３８の内端１３９など、他のＣｕま
たはＮｉオブジェクト２０６が表面２０４に接し、その
間にＧｅまたはＳｉの層２０８がある。圧力と熱を加え
た後、図１３の構造が形成される。図１２と図１３で共
通の参照番号は同じものを表す。図１２の層２０８は、
本発明のゲルマニウムまたはシリコンを含む化合物でで
きた層２１０となる。
【００５３】この新しいボンディング技法の他の使用例
は次の通りである。第１の例では、銅／ポリイミド・フ
レキシブル・ケーブルの接点上にゲルマニウムをめっき
した。合わせた銅印刷回路板をまず清浄化し、次いで１
６０℃で６０分間、２０kpsiの圧力でケーブルに圧着し
た。その結果、メタラジ構造Ｃｕ／Ｃｕ3Ｇｅ／Ｃｕ／
ポリイミドを有する印刷回路板が得られた。
【００５４】電源用にポリイミド・エレメントとモリブ
デン・エレメントを接合することの実現可能性をテスト
するために、構造を次のようにした。（１）２００Åの
クロムとそれに続いて１．０μｍの銅を蒸着したＭｏ基
板、（２）２００Åのクロム、１．０μｍの銅、２００
０Åのゲルマニウムから成る蒸着層をもつ厚さ２５μｍ
のUpilex（他のポリイミドも適当）である。銅表面を清
浄化して、上記のゲルマニウム表面に圧着した。この結
果得られる積層構造は、Ｍｏ／Ｃｒ／Ｃｕ／Ｃｕ3Ｇｅ
／Ｃｕ／Ｃｒ／Upilexであった。この構造のサンプルで
引張り試験を行った所、最大３０ｇ／ｍｍの強度であっ
た。
【００５５】図１２のＧｅまたはＳｉの層２０８を部材
２０６または表面２０４上に配設するための方法は、銅
やニッケルなどの導体にゲルマニウムまたはシリコンを
移転させるための乾式法である、デカル法である。この
デカル法を使って、銅層上に不動態化層を形成すること
ができる。
【００５６】図１４では、デカル２１３は、薄い柔軟な
共形基板２１２、例えばUpilexまたはポリイミドなどの
高分子材料から成る。基板２１２上に元素ゲルマニウム
またはシリコンの薄い層２１４がある。層２１４の厚さ
は約５００〜５０００Åの範囲にあり、約１０００Åが
最も好ましい。層２１４は、蒸着、スパッタリング、シ
ーディング後のめっき、または他の適当な手段で作成で
きる。
【００５７】この工程では、まず導体２１８の表面２１
６を清浄化する。２１８がＣｕの場合は、例えば硫酸な
どの銅清浄化浴を使用する。次に、表面２１６をデカル
２１３のゲルマニウムまたはシリコン２１４と接触させ
る。次に２つの表面をプレスにより矢印２２０で示すよ
うに、適当な力をかけて密着させる。適当なプレスは油
圧プレスである。銅・ゲルマニウムなどのＧｅまたはＳ
ｉを含む材料、好ましくはＣｕ3Ｇｅの層が銅線２１８
の表面２１６上に形成されるまで、２つの部片を、プレ
ス中で約１００〜３００℃、好ましくは約２３０℃の高
温に保持する。これには数分で十分である。次に２つの
部片をプレスから取り出して、図１５に示すように、銅
表面２１６から矢印２１５の方向に、銅表面２１６上の
ＧｅまたはＳｉコーティング２１４からデカルを剥が
す。図１６は、その結果得られる、Ｃｕ表面２１６の上
にＧｅ層２１４が配設された構造を示す。上述のよう
に、熱を加えて、本発明によるＳｉまたはＧｅを含む材
料を形成することができる。この新しい構造は、本発明
のゲルマニウムまたはシリコンを含む材料の層でキャッ
プした、Ｃｕなどの導体から成る。
【００５８】付着は、セラミック、シリコンまたは他の
基板の薄膜再分配パターンなど、どんな平面化されたま
たは柔軟な銅基板に行うこともできる。銅表面を有する
印刷回路板または印刷回路板の一部分をこのようにして
被覆することができ、導体として銅を使用する柔軟な回
路（フレクスまたはＴＡＢ）（テープ自動ボンディン
グ）も同様に被覆することができる。付着の前にデカル
薄膜をパターン付けして、連続する銅表面上にパターン
付き被覆を生成することもできる。被覆は、動くローラ
の間でシートをプレスすることによって、連続的に付着
することもできる。
【００５９】誘電材料としてポリイミドを使用する構造
中で銅の導体を使用するときは、銅線の上面を不動態化
して、次のポリイミド絶縁層を製造するために使用され
るポリアミド酸の作用から保護することができる。この
不動態化は、上記のようにして行われる。図の構造は、
ポリイミド絶縁層を備えた銅の導体から成る。銅線の上
面が、本発明によるシリコンまたはゲルマニウムを含む
材料によって不動態化される。
【００６０】図１７は、誘電体２１６中に埋め込んだ導
体２１２、２１４を有する構造２１０を示す。導体２１
２、２１４は、それぞれ本発明のシリコンまたはゲルマ
ニウムを含む材料からなる上部層２１８、２２０を有す
る。ポリアミド酸（ＰＡＡ）層２１７が、誘電体２１６
の表面２２２上に配設されている。層２１７には、開口
２２４、２２６が設けられ、それぞれ層２１８、２２０
を露出させている。層２１７は、層２１８と２２０がそ
れぞれ間にあるので、導体２１２、２１４とは接触して
いない。
【００６１】層２１８、２２６は、Ｃｕ原子がＰＡＡ層
２１７と接触しないようにする障壁層として働く。Ｃｕ
原子がＰＡＡと接触すると、ＰＡＡを加熱してポリイミ
ドに硬化するとき、錯体を形成してＣｕ酸化物を放出す
る。Ｃｕ酸化物の粒子はポリイミドの誘電率を増加させ
るので、望ましくない。ＰＡＡ中でのＣｕ酸化物粒子の
形成は、米国特許第５０５３２７２号に記載されてお
り、この教示を参照により本明細書に組み込む。
【００６２】図１７の構造２１０は、半導体チップ・パ
ッケージ基板、またはこの基板の上部金属被覆層、また
は半導体チップの上部金属被覆層として有用である。
【００６３】図１７の空間２２４、２２６を、図１８に
２２５、２２７で示す導電性材料で満たすことができ
る。ＰＡＡを焼結した後、ＰＡＡ層２１７はポリイミド
となるが、誘電体２１６がポリイミドであれば、図１７
の表面２２２はもはや識別できなくなる。したがって、
図１８では表面２２２を点線で示してある。２つのポリ
イミド層が積層または互いに接着されている場合には、
これらは別々の層として残る。図１８では、層２１８は
導体２１２と２２５の間の中間層であり、層２２０は導
体２１４と２２７の間の中間層である。
【００６４】本発明のＳｉ及びＧｅの材料は、相互拡散
障壁層及び腐食抑制層として働く中間層として有用であ
る。これは、異種金属間の電食作用の電極として働く可
能性のある残留水を含む、ポリイミドなどのポリマー中
に埋め込まれた導体に特に有用である。電食作用は次の
メタラジ構造、Ｃｒ／Ｃｕ／ＣｒまたはＣｒ／Ｃｕ／Ｔ
ｉ／Ａｕ中で腐食を引き起こす可能性がある。
【００６５】本発明者等は、腐食を防止するために本発
明のＳｉ及びＧｅを含む材料、例えばＣｕ3Ｇｅを、例
えばＣｒとＣｕの間に導入することを開示する。銅また
はニッケルの層を、本発明のＳｉ及びＧｅを含む材料の
保護被覆中で銅またはニッケルのクラッド層で置き換え
た構造を開示する。また、銅の層全体を上記の材料で置
き換えた構造を開示する。例えば、Ｃｒ層の厚さが２０
０Å、Ｃｕ層の厚さが３．５μｍである、Ｃｒ／Ｃｕ／
Ｃｒ構造を有する接触パッドを、両方のＣｒが厚さ２０
０Å、両方のＣｕ3Ｇｅが５０００Å、Ｃｕが２．５μ
ｍである、Ｃｒ／Ｃｕ3Ｇｅ／Ｃｕ／Ｃｕ3Ｇｅ／Ｃｒか
ら成る新しい構造で置き換える。代替実施例では、新し
い構造はＣｒ／Ｃｕ3Ｇｅ／Ｃｒであり、両方のＣｒが
厚さ２００Å、Ｃｕ3Ｇｅが３．５μｍである。
【００６６】Ｃｒ層が厚さ２００Å、Ｃｕ層が６μｍ、
Ｔｉ層が１μｍ、Ａｕ層が１μｍである、Ｃｒ／Ｃｕ／
Ｔｉ／Ａｕの層を有する構造を、Ｃｒが厚さ２００Å、
Ｃｕ3Ｇｅが５０００Å、Ｃｕが５．５μｍ、Ａｕが１
μｍである、Ｃｒ／Ｃｕ3Ｇｅ／Ｃｕ／Ｔｉ／Ａｕから
成る新しい構造で置き換える。代替実施例では、新しい
構造はＣｒ／Ｃｕ3Ｇｅ／Ｔｉ／Ａｕであり、Ｃｒが厚
さ２００Å、Ｃｕ3Ｇｅが６μｍ、Ｔｉが１μｍ、Ａｕ
が１μｍである。
【００６７】本発明のＳｉ及びＧｅを含む材料、例えば
Ｃｕ3Ｇｅの層を中間層として付着させる好ましい方法
は２つある。付着はすべて、一般に知られているモリブ
デン・マスク法を使って実施する。Ｃｕ3Ｇｅ層を作成
する第１の方法は、Ｇｅ層には約２５００Å、銅の層に
は３．０μｍの厚さを用いて、Ｃｒ、Ｇｅ、Ｃｕ、Ｇ
ｅ、Ｃｒを順に蒸着することである。この構造を２００
〜３００℃で１５〜３０分間、その場でアニールする。
別法として、以前に作成した材料源を用いてＣｕ3Ｇｅ
を直接付着することもできる。１つの付着順序はＣｒ、
Ｃｕ3Ｇｅ、Ｃｕ、Ｃｕ3Ｇｅ、Ｃｒである。
【００６８】ＣｕをすべてＣｕ3Ｇｅで置き換えた実施
例は、Ｃｕ3Ｇｅの直接付着によって、またはＧｅとＣ
ｕの層を交互に付着した後アニール・ステップにかける
ことによって行われる。
【００６９】図９のリード・フレームは、Ｃｕ上へのＣ
ｕ3Ｇｅの付着に関して述べた方法の後で無電解めっき
を用いて、Ｓｉ及びＧｅを含む材料の表面層をもつよう
に製作することができる。しかし、この方法は、この材
料の選択に限られたものではない。
【００７０】本発明者等は、銅の上に形成されたＣｕ3
Ｇｅの層から成る表面を有する電気接点を開示する。銅
は、薄い層としてもよく、また電気接点のバルク材料で
もよい。接点のバルク材料は銅でもよく、またＢｅＣｕ
やＣｕＮｉや黄銅など銅めっきができる他の適当な材料
でもよい。接点は、ばねの形でもよく、柔軟な基板に接
着された導体の一部分でもよく、またテスト用に使用さ
れるような独立の電気プローブでもよい。
【００７１】本発明者等は、上述の構造を製作するため
の方法を開示する。接点のバルク材料が銅でない場合
は、まずその表面上に１２００Å程度の銅層をめっきす
る。次に、めっきした銅の厚さの２／３である８００Å
程度のゲルマニウムを、バルク銅、またはバルク材料の
上、薄い銅層の上に電気めっきする。面積が未定の表面
をめっきするには文献に記載されているような定電流源
ではなく、定電圧めっき装置を使用するのが好ましいこ
とがわかった。この構造を、通常は２００℃で３０分間
アニールして、表面にＣｕ3Ｇｅの層を形成する。めっ
きは次の条件を用いて実施した。電気めっき浴は、６５
℃でプロピレン・グリコール中に７％のＧｅＣｌ4とし
た。めっきは定電圧条件下で実施した。固体ゲルマニウ
ムをアノードとして使用した。図１に示すような電気接
点は、３５ボルトで５分未満めっきした。小形テスト・
プローブは３５ボルト（約１アンペアの電流を引き出
す）で４分間めっきした。
【００７２】この構造を上記のようにアニールした。サ
ンプルの試験片についてＸ線回折分析を行って、Ｃｕ3
Ｇｅの形成を確認した。
【００７３】この構造及び工程は、銅でできたまたは銅
めっきができる、すべての電気接点またはプローブ構造
に使用することができる。金めっきに勝る主な利点は、
コストの節減と、金の表面よりはるかに硬い表面ができ
ることである。リード・フレームをテスト・プローブと
して使用することは、同時係属の米国特許出願第０７／
５８３２６１号に詳しく記載されており、その教示を参
照により本明細書に組み込む。
【００７４】この構造が高い費用効果で作成できるよう
に、ゲルマニウム化合物を電子パッケージに使用するに
は、無電解めっきが望ましい。代替の電気めっきには、
共通電極が必要である。これは必ずしも実現可能ではな
い。付着による処理では、高価な加工設備と時間が必要
である。この問題を解決するのは無電解めっきである。
【００７５】例えば発明者等は、適当な基板へのゲルマ
ニウム化合物の無電解めっきに使用できるめっき浴を開
示する。具体的には、銅上にニッケル・ゲルマニウム、
すなわちＮｉ3Ｇｅをめっきすることを開示する。ま
た、ニッケル層とそれに続く無電解ニッケル・ゲルマニ
ウム層から成る、ＧａＡｓデバイスへの接点を開示す
る。
【００７６】めっき浴は下記のものから成る。
【００７７】５００ｍｌの第１の水性浴を準備する。こ
の浴には、硫酸ニッケル７水和物３ｇ／ｌ、３クエン酸
ナトリウム２水和物９ｇ／ｌ、次亜リン酸ナトリウム１
水和物２０ｇ／ｌが含まれる。
【００７８】５０ｍｌの第２の水性浴を準備する。この
浴には四塩化ゲルマニウム５０ｇ／ｌ、クエン酸ナトリ
ウム１３５ｇ／ｌ、クエン酸４８ｇ／ｌが含まれる。
【００７９】第２浴を第１浴に加える。８５℃で５５０
ｍｌの体積が蒸発によって５００ｍｌに減少する。銅基
板をめっき浴に漬けてめっきを行う。上述し図示した構
造は、ニッケル・ゲルマニウム中での無電解めっきによ
って、適切な基板上に作成することもできる。
【００８０】ニッケル・ゲルマニウム表面をボンディン
グ用に使用できるかどうかテストした。ワイヤ・ボンド
及びはんだ接点が、表面上に容易に作成できた。
【００８１】上記の各実施例は本発明の原理を例示した
ものにすぎないことを理解されたい。本発明の原理を実
施する当業者は、本発明の趣旨及び範囲に含まれる、他
の様々な修正や変更を考えつくことができよう。
【図面の簡単な説明】
【図１】Ｓｉ及びＧｅを含む材料の上表面を有する接点
パッドの側面図である。
【図２】複数の表面層を有する、図１に示す構造の他の
実施例の側面図である。
【図３】パッドが電気的に接続された導体が複数の層を
もつ、接点パッドの別の実施例の側面図である。
【図４】はんだマウンドが取り付けられたＳｉ及びＧｅ
を含む表面を有する、接点パッドの側面図である。
【図５】図１の構造を製作する方法の側面図である。
【図６】図１の構造を製作する方法の側面図である。
【図７】図１の構造を製作する方法の側面図である。
【図８】ワイヤがボンディングされたＳｉまたはＧｅの
表面を有する、接点パッドの側面図である。
【図９】本発明のＳｉ及びＧｅ材料を含む選択された領
域を有することのできるリード・フレームの斜視図であ
る。
【図１０】図９のリード・フレームを使用したチップ・
パッケージの斜視図である。
【図１１】図９のリード・フレームを使用したチップ・
パッケージの斜視図である。
【図１２】２つの導体間のボンディング材料として本発
明のＳｉ及びＧｅを含む材料を使用する方法を示す図で
ある。
【図１３】２つの導体間のボンディング材料として本発
明のＳｉ及びＧｅを含む材料を使用する方法を示す図で
ある。
【図１４】本発明のＳｉ及びＧｅを含む材料を製作する
ための転写方法を示す図である。
【図１５】本発明のＳｉ及びＧｅを含む材料を製作する
ための転写方法を示す図である。
【図１６】本発明のＳｉ及びＧｅを含む材料を製作する
ための転写方法を示す図である。
【図１７】本発明のＳｉ及びＧｅを含む材料の、メタラ
ジ構造中の中間層としての使用を示す図である。
【図１８】本発明のＳｉ及びＧｅを含む材料の、メタラ
ジ構造中の中間層としての使用を示す図である。
【符号の説明】
２ 基板 ４ 電気導体 ６ 導体表面 ８ 不動態化層 １０ 露出領域 １２ シリコンまたはゲルマニウムを含む材料 １４ ＣｒまたはＴｒの層 １６ ゲルマニウムまたはシリコンの層 １８ Ａｕ、Ａｇ、Ｉｎ、Ｓｎ、Ｐｂなど軟らかい材料
の層
───────────────────────────────────────────────────── フロントページの続き (72)発明者 カーチス・エドワード・ファレル アメリカ合衆国10509、ニューヨーク州 ブルースター、オーチャド・ヒル・レー ン 301 (72)発明者 スン・クオン・カン アメリカ合衆国10514、ニューヨーク州 チャッパカ、メイベリー・ロード36 (72)発明者 ジェフリー・ロバート・マリノ アメリカ合衆国12065、ニューヨーク州 クリフトン・パーク、サウスバリー・ロ ード 20 (72)発明者 ドナルド・ジョーゼフ・ミカルセン アメリカ合衆国10512、ニューヨーク州 カーメル、ロングフェロー・アンド・ハ ッチンソン・ローズ（番地なし) (72)発明者 ポール・アンドリュー・モスコウィッツ アメリカ合衆国10598、ニューヨーク州 ヨークタウン・ハイツ、ハンターブルッ ク・アベニュー 343 (72)発明者 ユージン・ジョン・オサリバン アメリカ合衆国10960、ニューヨーク州 アッパー・ナイヤック、ノース・ブロー ドウェイ539 ２号 (72)発明者 テレンス・ロバート・オトゥール アメリカ合衆国12533、ニューヨーク州 ホープウェル・ジャンクション、クリー ク・ベンド・ロード 15 (72)発明者 サンパス・プルショタマン アメリカ合衆国10598、ニューヨーク州 ヨークタウン・ハイツ、ラボイ・コート 2075 (72)発明者 シェルドン・コール・リーレイ アメリカ合衆国05401、バーモント州バ ーリントン 、レイクウッド・パークウ ェイ 154 (72)発明者 ジョージ・フレデリック・ウォーカー アメリカ合衆国10028、ニューヨーク州 ニューヨーク ヨーク・アベニュー1540 11号ケイ (56)参考文献 特開 平４−731（ＪＰ，Ａ)

Claims (7)

    (57)【特許請求の範囲】
  1. 【請求項１】基板と、 前記基板上の電気導体と、 前記電気導体の表面の少なくとも一部をなす表面材料と
    を含み、 前記表面材料が、Ｃｕ3Ｇｅ、Ｎｉ3Ｇｅ、及びこれらの
    二元化合物の他の相から成る群から選択される化合物か
    らなる、半導体チップへの電気的相互接続を形成するた
    めの構造。
  2. 【請求項２】さらに前記表面材料と電気的に接触して配
    設された第２の電気導体を含むことを特徴とする、請求
    項１記載の構造。
  3. 【請求項３】前記第２の電気導体が、ＣｒとＣｕから成
    る群から選択された材料を含むことを特徴とする、請求
    項２記載の構造。
  4. 【請求項４】前記表面材料がポリマー層と接触して配設
    されることを特徴とする、請求項１記載の構造。
  5. 【請求項５】複数の電気接点を有する基板と、 複数のリードを有し、各リードが第１端と第２端を有す
    るリード・フレームと、 複数の電気接点を有する電子デバイスと、 前記リードの第１端及び第２端の表面の少なくとも一部
    分をなす表面材料であって、Ｃｕ3Ｇｅ、Ｎｉ3Ｇｅ、お
    よびこれらの二元化合物の他の相から成る群から選択さ
    れた化合物からなる表面材料と、 前記電子デバイスの電気接点と前記リードの第１端との
    間にワイヤ・ボンディングされた複数のワイヤとを含
    み、 前記リードの第２端が前記基板の電気接点にはんだ付け
    されている、半導体チップへの電気的相互接続を形成す
    るための構造。
  6. 【請求項６】半導体チップへの電気的相互接続を形成す
    るための方法であって、 第１及び第２の表面を有する支持基板の前記第１表面上
    に第１の材料を供給するステップと、 第１及び第２の表面を有する第２の基板の前記第１表面
    上に第２の材料を供給するステップと、 前記第１の材料と前記第２の材料が接触するように、前
    記支持基板の第１表面上に前記第２の基板の第１表面を
    配設するステップと、 前記第２の基板を、前記支持基板の第１表面の方向に圧
    着するステップと、 前記第１および第２の材料を加熱して、前記第２の材料
    を前記支持基板の第１表面に接着させると同時に、Ｃｕ
    3Ｇｅ、Ｎｉ3Ｇｅ、およびこれらの二元化合物の他の相
    から成る群から選択された化合物を形成するステップ
    と、 冷却するステップと、 前記第２の基板を前記支持基板の第１表面上から除去
    し、前記第２の材料を前記支持基板の第１表面上に接着
    したまま残すステップと、を含む方法。
  7. 【請求項７】前記加熱が約３００℃未満の温度であるこ
    とを特徴とする、請求項６記載の方法。
JP5058439A 1992-04-24 1993-03-18 半導体チップへの電気的相互接続を形成するための構造および方法 Expired - Fee Related JP2526007B2 (ja)

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DE69324959D1 (de) 1999-06-24
JPH0621140A (ja) 1994-01-28
CA2089791A1 (en) 1993-10-25
DE69324959T2 (de) 1999-12-02
MY134716A (en) 2007-12-31
ATE180357T1 (de) 1999-06-15
BR9301497A (pt) 1993-10-26
CA2089791C (en) 1998-11-24
EP0566901B1 (en) 1999-05-19
CN1112729C (zh) 2003-06-25
US5855993A (en) 1999-01-05
KR930022536A (ko) 1993-11-24
KR0135739B1 (ko) 1998-04-24
CN1082770A (zh) 1994-02-23

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