JP2522398B2 - Phase control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a phase control device for controlling the phase of data which is transmitted by using a bipolar transmission method and whose waveform is equalized by the data received through a transmission line. .

[Conventional technology]

In the conventional phase control method of this type, the waveform after transmission line equalization is sampled and the waveform is balanced (balanced).
Was calculated to detect whether the sampling point was behind or ahead of the original center of the data, and the phase control was performed to make the sampling phase proper. For example, a method of forming a phase locked loop (PLL) by using a wavelength division multiplexing transmission system (WDM) that obtains a difference between waveforms and controls a phase is used.

A conventional example will be described with reference to FIG. FIG. 3 is a waveform diagram showing an example of the sampling waveform. In FIG. 3, the sampling rate T _S is twice the transmission rate T _B. Sampling is performed according to the transmission rate T _B on the time axis. Data points a ₁ , a ₂ , a ₃ , ... And data points a ₁ , a ₂ ,
Data points a ₁ ′, as sampling points in the middle of a ₃ , ...
Set a ₂ ′, a ₃ ′, ... At this time, the phase detector performs the following calculation.

However, N is the number of data to be calculated, <Sign a _n >
= + 1 (a _n > 0), 0 (a _n = 0), -1 (a _n <0).

At this time, if the sampling phase leads the data, the operation result becomes a positive value, and conversely, if the phase is delayed, the operation result becomes a negative value and the phase is correct. If it does, the result of the calculation is zero. Therefore, using this calculation result, the phase control oscillator adjusts the phase so that the calculation result becomes zero.

(<Reference> IEICE National Convention 1984 Paper No.5
59 Takatori, Suzuki et al.) [Problems to be Solved by the Invention] In the conventional phase control method described above, phase control is performed by the balance of the waveforms after equalization, so transmission is performed from the center of the original data. If the sampling process is performed at a location which is 1/2 clock of the rate off, the operation result becomes zero, phase control becomes impossible, and reception data cannot be reproduced.

For example, referring to the conventional example shown in FIG. 3, data points a ₁ ′, a ₂ ′, a ₃ ′, ...
Since the a _n values of _{a n>, <Sign a n} > is always a zero value, Therefore, it becomes impossible to control.

An object of the present invention is to provide a phase control device that solves the above drawbacks.

[Means for solving the problem]

The phase control device according to the present invention, when receiving the input data sequence of code 0/1 that has been converted into the bipolar code and passed through the low-pass filter through the transmission line, separately inputs the data sequence received by the A / D converter. Digital sampling is performed with a sampling clock having a speed twice the transmission rate, the digitally sampled data is input to an equalizer, and the waveform is equalized by a digital filter. When reproducing the input data sequence by determining the code 0/1 based on a predetermined threshold,
In a phase control device in which a phase control oscillator supplies the sampling clock to the A / D converter to control the phase of digital sampling, the waveform equalized data output by the equalizer is input, and the waveform A phase detector that equalizes and calculates the phase difference between the center point of the received data on the time axis and the sampling, and outputs a control voltage corresponding to the calculated value; and a waveform equalized by the equalizer that equalizes the waveform. The received data is input, the waveform is equalized, the data is sampled by the sampling clock, and the difference between the voltage value at each sampling point and the voltage value at the previous sampling point is calculated. A half-clock detector that outputs a control signal only when it is a positive value, and a self-oscillation frequency that controls the oscillation frequency of the sampler corresponding to the control voltage output by the phase detector. When the control signal is generated from the half clock detector, the generated sampling clock is directly output to the A / D converter when there is no control signal from the half clock detector, and when there is the control signal from the half clock detector. And a phase-controlled oscillator that controls the sampling timing of the A / D converter by inverting the polarity of the generated sampling clock and outputting it to the A / D converter.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a waveform diagram showing an example of waveforms for explaining the calculation method of the present invention.

In FIG. 1, the phase control method according to the present invention has a phase detector 11, a half clock detector 12, and a phase control oscillator 13 in the receiving section 2.

 Details will be described with reference to FIG. 1 and FIG.

Input data 3 input to the transmission unit 1 is converted into a bipolar code by a bipolar converter 4, passed through a low pass filter 5 and band-limited, and then output to a transmission line 6. The data that has passed through the transmission line 6 is input to the reception unit 2, digitally encoded by the A / D converter 7, and then the distortion due to the transmission line is corrected by the equalizer 8 using a digital filter. This correction data is discriminated and judged by the judging device 9 based on the preset threshold value, and the code 0/1 indicates the output data 1
Output as 0. Further, at this time, the output of the equalizer 8 is input to the phase detector 11 and the half clock detector 12, where it is operated and input to the phase control oscillator 13 as a control signal. The control signal output from the phase control oscillator 13 controls the sampling timing of the A / D converter 7 as a sampling clock. The phase detector 11 uses the correction data output from the equalizer 8 based on the sampling clock output from the phase control oscillator 13 to obtain the data points shown in FIG.
The voltage values at a ₁ ′, a ₁ , a ₂ ′, a ₂ , a ₃ ′, and a ₃ are sampled and extracted, and the calculated value at each data point is output to the phase control oscillator 13. This calculated value is a data point
Positive values are obtained at a ₁ and a ₂ ′, zero values at data points a ₁ ′ and a ₂ , and negative values at data points a ₃ ′ and a ₃ .

Similarly to the phase detector 11, the half-clock detector 12 uses the correction data output from the equalizer 8 based on the sampling clock output from the phase-controlled oscillator 13 to obtain the data points a ₁ ′, a in FIG. The voltage values at ₁ , a ₂ ′, a ₂ , a ₃ ′, and a ₃ are sampled and extracted, and the difference from the voltage value at the previous sampling point is calculated. When the calculated value is a positive value ( At the data point a ₂ ′), a control signal for inverting the polarity of the sampling clock is output to the phase control oscillator 13.

The phase control oscillator 13 is composed of a digital PLL circuit and a sampling clock polarity switching circuit (neither of which is shown), and the digital PLL circuit receives the average value as the calculation result of the correction data from the phase detector 11. After performing the phase synchronization control by a known method, the sampling clock is output to the sampling clock polarity switching circuit. The sampling clock polarity switching circuit is driven by the control signal output from the half clock detection 12. That is, the half-clock detector 12 detects the half-clock deviation of the correction data and outputs the digital PLL circuit according to the control signal output when the operation result is a positive value (when the data point is a ₂ ′ in FIG. 2). When the sampling clock is inverted to the opposite polarity and the control signal is not output from the half clock detector 12 (when the operation result is a negative value or a zero value: the data points a ₁ ′, a ₁ , a ₂ , in FIG. 2).
a ₃ ′, a ₃ )), use the sampling clock as is.
Supply to the A / D converter 7.

The method of phase control in this system will be described with reference to FIG.

In FIG. 2, the sampling rate T _S is twice the transmission rate T _B. Time data points a ₁ to sample processed according to the transmission rate T _B on the axis, a _2, a _3, ... sampling points a ₁ to midpoint _{', a 2', a 3} ', ... to. The half clock detector 12 performs the following calculation.

<Sign a _n > × (a _n ′ −a _n ), where <Sign a _n > = + 1 (a _n > 0), 0 (a _n =
0) and -1 (a _n <0).

At this time, when the sampling processing is performed on the data points a ₁ , a ₂ , a ₃ , ...
When a ₁ ′, a ₂ ′, a ₃ ′, ... Are sampled, there is a 1/2 clock shift. Now, in this case
Due to the characteristics of the bipolar code, if there is no 1/2 clock deviation, the operation result will be a zero value or a negative value, and vice versa.
In the case of a clock shift, the calculation result is a zero value, a negative value or a positive value. Therefore, the half-clock detector 12 outputs a control signal for switching 1/2 clock only when the value becomes a positive value.

For example, the data points a ₁ in FIG. 2, a _2, a _3, if ... of the operation result in the data points a ₁ is a negative value, the data points a ₂ zero value, and negative in the data points a ₃ value Become. Conversely data points
In the case of a ₁ ′, a ₂ ′, a ₃ ′, ..., the data point a ₁ ′ has a zero value, the data point a ₂ ′ has a positive value, and the data point a ₃ ′ has a negative value. By detecting a positive value with a ₂ ′, 1 /
2 Clock shift control. However, a predetermined threshold value is provided to detect a _n = 0. This is because the data points a _n may not be completely zero, so it is necessary to define the zero level range.

In addition, if there is no 1/2 clock deviation, the operation result will not be a positive value due to the bipolar characteristics.
In case of clock shift and code 1,0 or code -1,0
If there is a pattern, the operation result will be a positive value, so a positive value will always appear except for all the patterns of code "0" and code "1, -1,1, -1, ...".

The phase detector 11 performs sampling processing on the waveform after transmission line equalization as in the conventional example, and performs phase control according to the balanced state of the waveform. As described in the conventional example, the phase detector 11 performs the following calculation.

However, N is the number of data to be calculated, <Sign a _n > = + 1 (a _n > 0), 0 (a _n = 0), −1 (a _n
<0).

At this time, if the sampling phase leads the data, the operation result becomes a positive value, and conversely, if the phase is delayed, the operation result becomes a negative value and the phase is correct. If it does, the calculation result is zero. The digital PLL circuit of the phase control oscillator 13 performs phase synchronization control by a known method based on the calculation result output from the phase detector 11, generates a sampling clock, and outputs it to the sampling clock polarity switching circuit. The sampling clock polarity switching circuit of the phase control oscillator 13 is driven by the control signal output from the half clock detector 12,
Is the polarity of the sampling clock generated by the digital PLL type circuit when it detects the 1/2 clock shift of the received data due to the delay characteristics of the transmission line 6 and outputs the control signal only when the operation result is a positive value. Is inverted, and when there is no control signal from the half clock detector 12, the digital PL
The sampling clock generated by the L circuit is output to the A / D converter 7 as it is without polarity reversal, and the A / D converter 7 receives the bipolar clock based on the received sampling clock via the transmission path 6. By sampling the data, even if the received data has a 1/2 clock shift, phase synchronization is possible and the received data can be reliably reproduced.

In this way, the digital PLL circuit of the phase-controlled oscillator 13 controls the sampling clock frequency based on the control voltage output corresponding to the phase difference detected by the phase detector 11 to perform the phase synchronization control and the half clock. Only when the detector 12 detects the 1/2 clock shift and the operation result is a positive value, the polarity of the sampling clock generated by the digital PLL circuit is inverted to control the sampling timing of the A / D converter 7. It becomes possible to reproduce the received data, which was not possible when the received data was shifted by 1/2 clock.

〔The invention's effect〕

As described above, according to the present invention, the input data sequence of code 0/1 which has been converted into the bipolar code and passed through the low pass filter is received via the transmission line, and digital sampling is performed by the sampling clock having a speed twice the transmission rate. A / D converter for equalization, an equalizer for waveform equalizing the digitally sampled received data with a digital filter, and a code 0/1 for the waveform equalized received data based on a predetermined threshold value.
In a phase control device having a judging device for judging the input data sequence according to the above, and a phase control oscillator for controlling the phase of digital sampling by supplying a sampling clock to the A / D converter, the equalizer outputs Input the waveform equalized received data, calculate the phase difference between the center point of the waveform equalized received data on the time axis and the sampling clock, and output the control voltage corresponding to the calculated value Phase detection And the waveform equalized receive data output from the equalizer are input, and the waveform equalized receive data is sampled by the sampling clock and the voltage value at each sampling point and the voltage at the previous sampling point respectively. The half clock detector that calculates the difference from the value and outputs the control signal only when the calculation result is a positive value, and the self-clock corresponding to the control voltage output by the phase detector And controlling the oscillation frequency to generate a sampling clock outputted as it is to the A / D converter,
When the half-clock detector outputs a control signal, the polarity of the generated sampling clock is inverted and output to the A / D converter, which consists of a phase-controlled oscillator that controls the sampling timing of the A / D converter. As a result, it becomes possible to reproduce the received data, which was impossible when the received data is shifted by 1/2 clock.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a phase control method of the present invention, FIG. 2 is a waveform diagram showing an example of a waveform explaining a calculation method, and FIG. 3 is an example of a waveform explaining a conventional calculation method. It is a waveform diagram showing. 1 ... Sending unit, 2 ... Reception unit, 3 ... Input data, 4 ...
… Bipolar converter, 5 …… Low pass filter, 6 ……
Transmission line, 7 ... Analog-digital converter, 8 ... Equalizer, 9 ... Judgment device, 10 ... Output data, 11 ... Phase detector, 12 ... Half clock detector, 13 ... Phase control Oscillator.

Claims (1)

(57) [Claims] 1. When the input data sequence of code 0/1 converted to a bipolar code and passed through a low-pass filter is received via a transmission line, the data rate received by the A / D converter is input separately. Digital sampling is performed by a sampling clock having a double speed, the digitally sampled data is input to an equalizer and waveform equalization is performed by a digital filter, and then a decision unit determines the waveform equalized data by a predetermined value. When reproducing the input data sequence by determining the code 0/1 based on the threshold value, the phase control oscillator
In the phase control device for controlling the phase of digital sampling by supplying the sampling clock to the A / D converter, input the waveform equalized data output from the equalizer,
This waveform is equalized, the phase difference between the center point of the received data on the time axis and the sampling clock is calculated, and a phase detector that outputs a control voltage corresponding to the calculated value; and a waveform output by the equalizer The equalized received data is input, the waveform is equalized, the data is sampled at the sampling clock, and the difference between the voltage value at each sampling point and the voltage value at the previous sampling point is calculated. A half clock detector that outputs a control signal only when the operation result is a positive value; and a half clock detector that controls the oscillation frequency of itself in response to the control voltage output by the phase detector to generate the sampling clock. When there is no control signal from the detector, the generated sampling clock is used as it is.
Output to the A / D converter, and when there is the control signal from the half clock detector, the polarity of the generated sampling clock is inverted and output to the A / D converter, and the A / D A phase control oscillator for controlling the sampling timing of the converter, and a phase control device.