JP2521906B2 - Recording and playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A. Industrial field of use B. Outline of invention C. Prior art D. Problems to be solved by the invention E. Means for solving the problem F. Action G. Example G-1. Schematic configuration (Fig. 1) G-2. Overall structure of tape recorder (Fig. 2) G-3. Description of main part operation (Fig. 3) G-4. Other structural examples H. Effects of the invention A. Industrial BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing apparatus, and more particularly to a recording / reproducing apparatus for converting an analog signal such as an audio signal into a digital signal and writing / reading it in a storage means such as a memory.

B. Outline of the Invention The present invention is a recording in which an analog signal such as an audio signal is converted into a digital signal and written in a storage means, and the content written in the storage means is read according to an operation input, converted into an audio signal and taken out In the reproducing apparatus, a counter for obtaining an address for accessing the storage means is also used as an interval timer, and the counter output of is latched by the latch means according to the operation input, and the signal written in the storage means is stored in the storage means. When the capacity is less than the capacity, the count value stored in the latch means is used as the end address, the storage means is sequentially read and reproduced according to the count operation from the initial value of the counter, and at the time when the end address is reached. A predetermined silent interval is formed by the interval timer operation of the counter. By repeating the work, even when there is an operation input when the small storage contents status than the total storage capacity of the storage unit, in which a feasible without inconvenience smooth digital repeat playback.

C. Conventional technology Tape recorders and the like have been widely used to record and reproduce analog signals such as audio signals, but they respond by recording and reproducing by mechanically driving magnetic tapes and the like. There is a limit to the speed.

By the way, JP-A-49-83472 and JP-A-52-143007.
In Japanese Patent Laid-Open Publication No. 9-242242, a technique for digitizing an audio signal and storing it in a memory device or the like is disclosed. With such a technique, so-called random access reproduction in which desired recording contents are instantly read can be easily realized, but a recording time (for example, about 1 hour) comparable to that of a normal tape recorder is secured. However, even if the digital signal compression technique is used, a very large storage capacity is required for the memory device, which is not only extremely expensive as compared with the price of the currently popular general analog tape recorder. Especially, it is difficult to apply to a portable tape recorder.

Therefore, the applicant of the present application has proposed a digital circuit for causing a general analog tape recorder, for example, a tape recorder for language learning (so-called LL) to perform digital recording and reproduction only for a short time (for example, about several seconds) required for repeat reproduction. We are proposing a tape recorder with a system added. According to this tape recorder, not only the repeat reproduction can be performed with high response and high accuracy, but also the scale of the digital circuit system, especially the memory capacity, can be small.

D. Problems to be Solved by the Invention By the way, when such repeat reproduction is performed digitally, access or address control to a digital storage means composed of a semiconductor memory such as RAM is troublesome, and especially RAM or the like. If you try to perform repeat playback with a playback time that is shorter than the repeat time that corresponds to the total storage capacity of, the start address (start address) and end address (end address) of repeat playback will be complicated, which is preferable. There are problems that repeat reproduction cannot be performed and the circuit configuration becomes complicated.

The present invention has been made in view of the above-mentioned circumstances, and when the repeat reproduction is performed digitally by sequentially and repeatedly reading the storage means such as the RAM, the stored contents smaller than the capacity of the storage means can be used. An object of the present invention is to provide a recording / reproducing apparatus that enables effective and smooth repeat reproduction, and is particularly suitable for a small-sized language learning (LL) tape recorder.

E. Means for Solving the Problems A recording / reproducing apparatus according to the present invention is an A / D conversion means for converting an input analog signal into a digital signal, and a storage means for storing the digital signal from the A / D conversion means. And convert the digital signal from this storage means into an analog signal
The digital control unit is provided with a D / A conversion unit and a digital control unit for controlling the storage unit. The digital control unit outputs a counter for switching the count of the address and the interval time of the storage unit and an address count output of this counter. The latch means for temporarily storing, the comparing means for comparing the count output of the counter and the address of the output of the latch means, and the counter receiving the operation input, the address count output of the counter and the output of the comparing means And a control means for controlling the latch means, and until the operation input is made, the digital signals from the A / D conversion means are continuously written in the storage means, and the operation input is made. When the address is output, the address count output of the counter is stored in the latch means, and the storage means is switched to the read mode. Further, when an operation input is made and when the reading of the digital signal from the storage means is completed, the counter is switched to one for counting the interval time, and when the address count output of the counter coincides with the interval value, The address stored in the latch means is used as a read end address, and a digital signal up to the read end address is read from the storage means on the basis of the output of the comparison means to set the interval setting means. The above-mentioned problems are solved by the feature that the operation of forming a silent section of time and the reading of the digital signal from the storage means are alternately repeated.

F. Action When there is an operation input with the stored contents smaller than the storage capacity of the storage means, the address at the time of the operation input is used as the end address, and the counter counts from the initial value to the end address and the RAM The storage means is sequentially accessed, and when the end address is reached, the above-mentioned counter is used as an interval timer to sequentially repeat an operation of forming a predetermined silent section, whereby the stored contents are stored through a predetermined time interval. It is possible to smoothly realize so-called repeat reproduction by repeatedly reading.

G. Example G-1. Schematic configuration (FIG. 1) FIG. 1 is a block diagram for explaining a recording / reproducing apparatus according to an example of the present invention. Specifically, a general analog tape is used. An example of a circuit suitable for digitally realizing a repeat reproduction function by being added to a recorder, especially a small portable tape recorder for language learning is shown.

A digital signal obtained by AD conversion (analog-digital conversion) of an analog audio signal from an audio circuit system of an analog tape recorder described later is supplied to the input terminal 1 of FIG. The audio signal is sent to the RAM 2 which is a storage means and sequentially written. The digital signals sequentially read from the RAM 2 are sent to the output terminal 3 via the system controller or the digital mute circuit 11 in the digital controller 10. The digital signal taken out from the output terminal 3 is DA converted (digital-analog converted) into an analog audio signal, which is sent to an audio circuit system described later.

The digital control unit 10 is used as a RAM controller and a system controller, and a counter 12 having at least a function as an address counter of the RAM 2 and a function as an interval timer described later,
A latch circuit 13 for temporarily holding (so-called latching) the count output from the counter 12, and the latch circuit 13
Means for comparing the output from the counter and the output from the counter 12, a so-called comparator 14, and a gate circuit for gate-controlling the output from the latch circuit 13 and sending it to the preset data input terminal (or data load terminal) of the counter 12. 15 and a sequencer 16 that serves as control means for controlling the operation of each part
And at least. Sequencer 16
Is the operation of each of the digital mute circuit 11, the counter 12, the latch circuit 13, and the gate circuit 15 according to the operation input (for example, the pause operation input) from the control input terminal 6 of the digital control unit 10 and the output from the comparator 14. It is for the purpose of sequentially controlling. The digital controller 10 is further provided with a timing controller 17, a multiplexer 18, and an interval time setting circuit 19, and the timing controller 17 has a clock input terminal 7 at which a sampling clock pulse serving as a reference synchronization pulse is provided. Is being supplied through. Various timing pulses from the timing controller 17 are supplied to the sequencer 16, the multiplexer 18, the external RAM 2 and the like. The multiplexer 18 outputs the count output from the counter 12 to RA
The interval time setting circuit 19 sends an interval end signal to the sequencer 16 when the count output from the counter 12 reaches a predetermined value. Also, the counter 12
Sends a carry output to the sequencer 16 when counting the value according to the storage capacity (total address space) of RAM2,
Sequencer 16 sets the overflow flag OVF according to the conditions.
Set.

G-2. Overall structure of tape recorder (Fig. 2) With reference to Fig. 2, a specific example in which the digital recording / reproducing circuit system having the above-mentioned structure as a main part is applied to a general analog tape recorder. explain.

The tape recorder schematically shown in FIG. 2 digitally performs repeat reproduction for a short period of time (for example, about 4 seconds or 8 seconds), and in a normal reproduction mode in a repeat mode ON state described later. , Analog playback signal AD
When it is converted and constantly written in the RAM2 that is the storage means, and the pause button etc. is operated (at the time of pause operation)
Then, the contents stored in RAM2 are read repeatedly in sequence and DA
By converting, repeat playback is realized.

First, the analog audio circuit system in FIG. 2 will be described. To the recording / reproducing amplifier 51, the reproduction signal from the recording / reproducing head 52 is input via the selected terminal P of the mode selection switch 53, and from the microphone 54. Is input, and the recording output (so-called Rec. Out) signal from the amplifier 51 is supplied to the recording / playback head 52 via the selected terminal R of the mode changeover switch 53. ing. The recording / reproducing amplifier 51 is supplied with a circuit power source, so-called Vcc, from a + B power source terminal 55. +
The B power supply voltage is supplied to the common terminal of the mode changeover switch 57 via the resistor 56, and the selected terminal R of this mode changeover switch 57 is connected to the recording / playback switching terminal (PB / REC) of the recording / playback amplifier 51. The selected terminal P is grounded. These mode changeover switches 53 and 57 are interlocked with each other, and the respective switches 53 and 57 are respectively connected to the respective selected terminals R.
The recording mode is selected when the switch connection is made to the switch, and the reproduction mode is selected when the switch connection is made to each selected terminal P.

The reproduction output (Line Out) signal from the recording / reproducing amplifier 51 is supplied to the variable resistor 60 for volume control via the capacitor 58 and the resistor 59, and the output signal from this variable resistor 60 is
It is supplied to the power amplifier 61 via a resistor and a capacitor. The output signal from the power amplifier 61 is taken out from the output terminal 62 as an audio output signal.

The following digital circuit system is added to the above-described schematic configuration of the analog audio circuit system in order to perform the digital repeat reproduction as described above.

That is, the analog audio signal from the output (Line Out) terminal of the recording / playback amplifier 51 is passed through the capacitor 21 and the resistor 22 and through the LPF (low pass filter) 23 to the AD
-AD (analog-digital) converter 24a of DA converter 24
Is supplied to From the AD converter 24a, for example, a delta-modulated (specifically, ADM, adaptive delta-modulated) digital signal is output, and this digital signal is stored in the RAM as a storage means via the terminal 1 in FIG. It is sent to (random access memory) 2 and sequentially written. This RA
The M2 is designed so that writing and reading operations are controlled by the system controller or the digital control unit 10 as described above, and the digital signal read from the RAM 2 is AD / DA converted through the digital control unit 10. Of 24
It is sent to the DA (digital-analog) converter 24b. Regarding the input / output terminals and the like of the digital control unit 10, those corresponding to those in FIG. 1 are designated by the same reference numerals.
The output signal from the DA converter 24b is sent to the muting circuit 30 via the LPF 27, the resistor 28 and the capacitor 29. The muting circuit 30 includes a switching transistor 31 connected between the signal transmission line and the ground,
The output signal from the muting circuit 30 is supplied to the buffer amplifier 32 via the capacitor. The output signal from the buffer amplifier 32 is the capacitor 33 and the resistor 34.
Is supplied to the connection point between the resistor 59 and the variable resistor 10 of the analog audio circuit system via. At this time, the resistance 59,
34 acts as a so-called mixing resistor.

Regarding the circuit power supply of this digital circuit system,
The power from the B power supply terminal 55 is passed through the switching circuit 35, the repeat mode changeover switch 36, etc., and the DC-DC converter 37.
To be obtained from this DC-DC converter 37. The transistor 35a of the switching circuit 35 is turned on when the mode switch 57 is switched and connected to the terminal P on the reproducing side, and supplies the + B power source to the repeat mode switch 36. Repeat mode selector switch 36
Is for switching and selecting a repeat operation in which, for example, when the pause button is operated during the reproducing operation, the recorded content for a predetermined time (for example, 4 seconds, 8 seconds) immediately before the pause is repeatedly reproduced. This repeat mode changeover switch 36 is specifically, for example, three selected terminals a, b,
The selected terminal a corresponds to the repeat mode off (no repeat), the terminal b corresponds to the repeat mode for 4 seconds, and the terminal c corresponds to the repeat mode for 8 seconds. When the repeat mode selector switch 36 is switched and connected to the selected terminal b or c, the + B power source obtained through the transistor 35a is supplied to the DC-DC converter 37, and the power source output from the DC-DC converter 37 is output. Is supplied to the AD / DA converter 24, the RAM 2 and the digital control unit 10 of the digital circuit system. When the repeat mode selector switch 36 is switched and connected to the selected terminal a, the + B power source from the transistor 35a of the switching circuit 35 is applied to the base of the transistor 31 of the muting circuit 30 via the time constant circuit 41. Then, the muting is turned on.

Here, switching of the repeat time when the repeat mode is selected can be realized by switching the sampling lock frequency of the AD / DA converter 24, for example, and specifically, the clock generation unit in the AD / DA converter 24. By switching the time constant, for example, by switching the capacitors 38b and 38c with the changeover switch 39, the sampling lock frequencies are, for example, 64 kHz (64 kbps) and 32 kHz (32 kbp).
s) and. That is, assuming that the digital output signal from the AD / DA converter 24 that has undergone AD conversion and has undergone adaptive delta modulation (ADM modulation) is 1 sample per 1 bit, and the storage capacity of RAM 2 is 256 kb (kilobit), the sampling frequency is 64 kHz. It is possible to record for 4 seconds at, and record for 8 seconds at 32 kHz. The sampling clock in the AD / DA converter 24 is sent to the digital control section 10 through the clock input terminal 7 as the reference synchronizing pulse shown in FIG. Of course, the changeover switches 36 and 39 are interlocked with each other.

Here, when the repeat mode is selected by connecting the repeat mode changeover switches 36 and 39 to either of the terminals b or c and the repeat mode is selected, the reproduction output (Line Out) signal of the recording / reproduction amplifier 1 is selected. Is supplied to the AD conversion unit 24a of the AD / DA converter 24 via the LPF23, etc.
The converted digital signals are sequentially written in RAM2. At this time, when the pause operation signal is input to the terminal 6 of the digital control unit 10 by the operation of the so-called pause button, the control unit 10 switches the RAM 2 to the read mode, and the recorded contents for 4 seconds or 8 seconds immediately before the pause input. Are sequentially and repeatedly read and sent to the DA converter 24b of the AD / DA converter 24 via the digital controller 10. During this repeat reproduction operation, the stored contents of the RAM 2 are repeatedly read and reproduced, for example, with a predetermined interval (silent section) interposed. The analog audio signal extracted from the DA converter 24b via the LPF 27 is sent to the buffer amplifier 32 via the muting circuit 30 and the like. The output signal from the buffer amplifier 32 is sent to the variable resistor 60 of the analog audio circuit system via the capacitor 33 and the resistor 34, amplified by the power amplifier 61, and taken out from the output terminal 62. Therefore, after the pause operation, the playback content (playback output from the recording / playback amplifier 51 of the analog audio circuit system) for 4 seconds or 8 seconds immediately before the pause operation is repeated digitally with the above predetermined time interval interposed. The so-called repeat reproduction is realized digitally. Here, when the time from the pause cancellation to the next pause operation is shorter than the repeat time (for example, 4 seconds or 8 seconds), the audio reproduction content within this short time is repeated with the above interval. Digitally reproduced.

G-3. Description of operation of main part (FIG. 3) With reference to FIG. 3, the control operation for performing the digital repeat reproduction as described above in the digital circuit system of the tape recorder having the above-described schematic configuration is described. While explaining. That is, the example of FIG. 3 shows the operation when the repeat mode changeover switches 36 and 39 are switchably connected to the terminal b or c corresponding to the repeat mode ON and the reproduction mode is selected.

The control operation of FIG. 3 is roughly composed of four basic operations. These basic operations are the initial setting operation (steps S11 to S13) immediately after the power is turned on (power on) and immediately after the repeat reproduction is canceled. Digital recording operation to the RAM2 which is the storage means (steps S14 to S19), a silent section (interval) forming operation between the sound reproduction sections during repeat reproduction (steps S21 to S24), and digital reading by reading the RAM2. This is the reproducing operation (steps S25 to S33).

First, when power is supplied to the digital circuit system in step S10 of FIG. 3, that is, the mode changeover switches 53 and 57 are set to the terminal P side and the repeat mode changeover switches 36 and 39 are set to the terminal b or c side. If they are switched and connected, the flow proceeds to step S11, and the sequencer 16 of FIG. 1 controls the digital mute circuit 11 to be in the ON state (muted state). Next, the sequencer 16 clears the counter 12 (zero reset) to set the count output that becomes the address Adr of the RAM 2 to 0 as shown in step S12 (Adr ← 0), and sets the overflow flag OVF of the counter 12 to 0. Reset (OVF ← 0).
The zero reset operation of the counter 12 may be performed by closing the gate circuit 15 and controlling the load of the counter 12, for example.

After the above initial setting operation is completed, step S1
Control is transferred to the digital recording operation of 4 to S19. In this digital recording operation, it is determined in step S14 whether or not the pause operation input has been made, and the following series of operations are repeated until the pause operation input is made. That is, in synchronization with the input timing of the synchronization pulse (sampling lock) in step S15, step S1
Write to RAM2 in 6 and address in step S17.
Adr is incremented (Adr ← Adr + 1), that is, the counting operation by the counter 12 is performed by 1 count,
Whether or not the counter 12 has overflowed in step S18,
That is, it is determined whether or not Adr = 0, and when a digit overflows, the overflow flag OVF is set to 1 (OVF ← 1) and the process returns to step S14. Therefore, until the pause operation is performed, the digital signal of the AD conversion output is successively written in sequence from the address 0 of RAM2 at the timing synchronized with the sampling lock, and this time is the repeat time (4 seconds or 8 seconds). When crossing
When the overflow flag OVF is set to 1, digital signals are sequentially written from the address 0 of RAM2, and the previous data is rewritten. In this case, the RAM 2 stores digital data for the repeat time immediately before the present time.

Next, when the pause operation input is detected in step S14, the control proceeds to step S20, and the interval timer operation and the digital reproduction operation are executed.

In step S20, the current address Adr from the counter 12 is taken into the latch circuit 13 by the control signal from the sequencer 16 (LA ← Adr), and the next step
At S21, the counter 12 is reset (Adr ← 0).
From this state of count value 0, the counting operation of the counter 12 proceeds in step S23 (Adr ← Adr + 1) while being synchronized with the synchronization pulse (sampling clock) in step S22, and the count value A in step S24.
The series of operations from step S22 are repeated until dr reaches the interval end value IEA. During this period, since the digital mute in step S11 remains turned on, a silent interval section is formed. The interval end is determined in step S24 by detecting that the output from the counter 12 has reached the predetermined value IEA by the interval time setting circuit 19. Therefore, the counter 12 is
It has both the function of RAM2 as an address counter and the function of the above interval timer.

When the interval end is detected in step S24, the process proceeds to the next step S25, and the digital reproduction operation for repeat reproduction as described above is started. First, in step S25, it is determined whether or not the overflow flag OVF is 1, and when it is 1, the process proceeds to step S26, and the value latched by the latch circuit 13 in the counter 12 through the gate circuit 15 is determined. Preset or load LA as the start address (Adr ← LA). When the OVF is 0, the process proceeds to step S27, and 0 is set as the start address in the counter 12 (Adr ← 0). After the start address is set in step S26 or S27, the process proceeds to step S28, the digital mute circuit 11 is controlled to the off state, and steps S29 to S33 are performed.
Thus, the actual read operation of the RAM 2 is sequentially performed.
That is, in step S29, it is determined whether or not the paused state is released,
RAM2 is read in step S31 while synchronizing with the sync pulse detection in step S30, and the address Adr is read in step S32.
Is incremented (Adr ← Adr + 1), that is, the counting operation by the counter 12 is performed by 1 count, and it is determined in step S33 whether or not the output of the counter 12 reaches the latch address LA which is an end address. The operation is repeated in sequence. When the count value Adr reaches LA in step S33 before releasing the pause, the process returns to step S21 to perform the interval timer operation, and then the process proceeds to step S25 again to repeat the digital reproduction operation. In this way, digital repeat reproduction is performed with a predetermined interval time interposed. When the pause is released during this time, the control moves from step S29 to step S11, and after the initial setting from step S11 to step S13 is performed,
The digital recording operation from step S14 to step S19 is executed.

Here, in the determination of the overflow flag OVF in the above step S25, the time from the pause cancellation time (or the power-on time of the digital circuit system) to the pause operation (pause-on) time is the repeat time (4 seconds or 8 seconds).
It is for determining whether it is long or short compared to the second), and if it is long, OVF is 1, and the latched count value becomes the start address and end address of repeat reproduction, while it is short. OVF is step S
It remains set to 0 in 13 and the start address of repeat reproduction becomes 0. Therefore, when the time from the pause release to the pause (ON) operation is shorter than the repeat time, the interval timer count operation for the predetermined time and the RAM2 from the address 0 as the start address to the latched end address are stored. Repeated reproduction is digitally realized by alternately repeating the operation of sequentially reading the contents.

G-4. Other Configuration Examples The present invention is not limited to the above-described embodiment, and for example, in the AD / DA converter of the embodiment, adaptive delta modulation is performed at the same time. Other, normal AD
Bit compression may be achieved by combining DA conversion with predictive coding processing such as adaptive differential PCM or orthogonal conversion processing such as Hadamard conversion. Also, each functional block of the digital control unit does not need to be configured as hardware,
Etc. may be program-controlled to be realized by software. Further, it goes without saying that the sampling clock frequency, the repeat time, the interval time, the number of bits per sample, etc. may be arbitrarily set according to the required sound quality, the purpose of repeat reproduction, and the like.

H. Effect of the Invention According to the audio signal recording / reproducing system of the present invention, when the counter output reaches the end address, the counter is used as an interval timer by the sequencer, and the interval is repeated between the audio reproducing sections of the repeat reproducing. (Silence section) is interposed, and repeat reproduction in a form suitable for language learning can be effectively performed.

Further, by performing a pause operation (from pause off to pause on) at a time interval shorter than the repeat time corresponding to the total storage capacity of the storage means such as RAM, etc., the repeat is performed with the stored contents that do not reach the storage capacity. In case,
Since the counter value (address) at the time of the pause (on) operation is latched as the end address, the contents from the initial value (address 0) such as RAM to this end address correspond to the stored contents before the pause operation. Repeated reading can be repeated without any inconvenience.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a main part for explaining an embodiment of the present invention, and FIG. 2 is a block circuit diagram schematically showing an entire tape recorder to which the present invention is applied. The figure is a flow chart for explaining the main operation of the present invention. 1 ... Digital signal input terminal 2 ... RAM 3 ... Digital signal output terminal 10 ... Digital control unit 11 ... Digital mute circuit 12 ... Counter 13 ... Latch circuit 14 ... Comparator 15 ... Gate circuit 16 ... … Sequencer 19 …… Interval time setting circuit 24a …… A / D converter 24b …… D / A converter 51 …… Recording / playback amplifier

Claims (1)

(57) [Claims] 1. An A / D conversion means for converting an input analog signal into a digital signal, a storage means for storing the digital signal from the A / D conversion means, and a digital signal from the storage means for conversion into an analog signal. D / A conversion means for controlling the storage means, and a digital control portion for controlling the storage means, wherein the digital control portion switches the count of the address and the interval time of the storage means and the address count output of the counter. Is temporarily stored, a comparing means for comparing the count output of the counter with the address of the output of the latch means, and an operation input, an address count output of the counter and an output of the comparing means. It is configured to have a counter and control means for controlling the latch means, and until the operation input is made, the A / D conversion means The digital signals are sequentially written in the storage means, and when the operation input is made, the address count output of the counter is stored in the latch means, and the storage means is switched to the reading mode.
Further, when an operation input is made and when the reading of the digital signal from the storage means is completed, the counter is switched to one for counting the interval time, and when the address count output of the counter coincides with the interval value, The address stored in the latch means is used as a read end address, and a digital signal up to the read end address is read from the storage means on the basis of the output of the comparison means to set the interval setting means. A recording / reproducing apparatus characterized by alternately repeating a time silent section forming operation and reading a digital signal from the storage means.