JP2517456Y2 - Calibration tool for analog IC tester - Google Patents

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention relates to a calibration jig for an analog IC tester that tests the quality of an image sensor, for example.

"Prior Art" Before describing the conventional calibration method for an analog IC tester according to the present invention, a calibration method for a conventional analog IC tester will be described.

FIG. 5 shows a schematic configuration of an image sensor tester as an example of an analog IC tester.

In the figure, 100 is an analog IC tester main body, 200 is an analog IC under test, and 300 is a DUT board for electrically connecting the analog IC under test 200 to the analog tester main body 100.

The analog tester main body 100 includes a signal source 110 for supplying a scan driving signal DS to the analog IC under test 200, and the analog IC 200 under test.
The analog signal output from the
The determination device 120 determines the quality of the IC 200.

The signal source 110 includes a timing generator 111, a pattern generator 112 that generates a predetermined pattern signal according to a timing signal supplied from the timing generator 111, and an actual scanning drive waveform according to the pattern data output from the pattern generator 112. Waveform generator group 113, a variable delay element group 114 for adjusting the timing of pattern data given from the pattern generator 112 to the waveform generator 113, a clamp circuit 304 and a sample hold circuit provided on the DUT board 300. A variable delay element group 115 for adjusting the timing of the pulse SP given to each 305 is provided.

The DUT board 300 includes a drive circuit group 301 and a DUT socket 302.
A buffer amplifier 303, a clamp circuit 304, a sample hold circuit 305, and a buffer amplifier 306.

In this example, the analog IC under test 200 is a semiconductor image sensor. Since the image sensor outputs an image pickup signal including dark current, a clamp circuit 304 is provided to remove the dark current.

The analog signal from which the dark current component has been removed by the clamp circuit 304 is sample-held by the sample-hold circuit 305, and the sample-hold output is buffer amplifier 306.
Through the judgment device 120 of the analog IC tester main body 100.

The determination device 120 includes an amplifier 121, an AD converter 122, and an image processing device 123.

The analog IC 200 under test is tested as follows.

The analog IC 200 to be tested is attached to the DUT socket 302 provided on the DUT board 300, and uniform white light is applied to the analog IC 200 to be tested. Give a DS.

When the scan drive signal DS is given, the analog IC under test 200 repeats line scanning and surface scanning, and outputs an image signal.

This image signal is input to the clamp circuit 304 through the buffer amplifier 303 and clamped to a predetermined level in, for example, the vertical blanking interval to remove the dark current component of the analog IC 200 under test.

The image signal from which the dark current component is removed is sampled and held by the sample and hold circuit 305 at the timing of each pixel, and the sample and hold value is input to the determination device 120.

The determination device 120 sequentially AD-converts the sample hold values of the image signals input line-sequentially, inputs the AD-converted image data to the image processing device 123, and writes the pixel data at each pixel position.

The image processing device 123 is a difference in the value of the image data between each pixel,
Etc., the unevenness of the brightness is detected, and if the unevenness is within a certain range, it is determined to be good, and if it is out of the range, it is determined to be defective, and the quality of the analog IC 200 under test is determined.

In the above-described image sensor tester, it is necessary to adjust the phases of the scan drive signals supplied from the drive circuit group 301 to the analog IC under test 200 to have a predetermined relationship.

That is, since each drive circuit has a variation in delay time, the variable delay element group 114 is provided in order to equalize the variation.
It is necessary to adjust the delay time of each variable delay element of the variable delay element group 114 so that the delay times of the respective drive circuits match.

Conventionally, prepare a standard image sensor judged as a good product, attach this image sensor to the DUT socket 302, give a scan drive signal DS to this standard image sensor, and output the image signal output from this image sensor. DU
Observing with an oscilloscope 400 connected to the output side of the T board 300, the delay time of the variable delay element group 114 is adjusted so that this waveform becomes a normal waveform.

“Problems to be solved by the device” It is difficult to adjust the mutual phase of the scan drive signals so that the image pickup output signal (white image signal) of the analog IC 200 under test has a regular waveform. Also, accurate adjustment is difficult.

An object of the present invention is to provide a jig for calibrating an analog IC tester that can easily and accurately adjust the phase of a scanning drive signal to be a normal phase.

"Means for solving the problem" In this invention, the analog IC to be tested implanted in the insulating substrate.
Connect the input terminal to a plurality of conductive pins that fit in the DUT socket to which is attached, and to the conductive pin at the position corresponding to the terminal to which the signal applied to the analog IC under test is given in these conductive pins. A calibration jig for an analog IC tester is composed of a multiplexer in which the output terminal is connected to a conductive pin at a position corresponding to the output terminal of the IC.

According to the configuration of this invention, by mounting the calibration jig according to this invention in the DUT socket instead of the analog IC under test during calibration, the signal applied to the analog IC under test is output by the multiplexer. It can be selectively taken out to the terminal corresponding to the terminal.

Therefore, the mutual phase of the signals selected and extracted by the multiplexer, that is, the delay time difference between the signals can be measured.

Since the signal applied to the analog IC under test can be taken out at the position of the DUT socket, the phase of the signal applied to the analog IC under test can be accurately obtained. The phases can be matched exactly.

"Embodiment" FIG. 1 shows an embodiment of the present invention. 300 in the figure is the fifth
A DUT board similar to that described in the figure is shown. This DUT board
A drive circuit group 301, a clamp circuit buffer 303, a clamp circuit 304, a sample hold circuit 305, and a buffer amplifier 306 are mounted outside the DUT socket 302 in the 300.

Although not particularly shown, an analog IC under test is attached to the DUT socket 302 during the test, and the analog IC under test is electrically connected to the analog tester main body through the DUT board 300.

Reference numeral 500 shown in FIG. 1 represents a calibration jig for an analog IC tester according to the present invention. The calibration jig of the analog IC tester according to the present invention has a plurality of conductive pins 502 on the back side of the insulating substrate 501.
, And the multiplexer 5 on the front side of the insulating substrate 501.
03 is implemented and configured.

The conductive pin 502 is embedded in the insulating substrate 501 in such a manner that it can be inserted into the DUT socket 302.

The input terminals H _{1 to} H _n and the output terminal Q of the multiplexer 503 are conductive pins 502 implanted in an insulating substrate 501 as shown in FIG.
Connected to A-502N and 502Q.

The conductive pins 502A to 502N have pin arrangements at positions corresponding to the input terminals of the analog IC under test. Therefore, the calibration jig 50
By mounting 0 on the DUT socket 302, the input terminals H _{1 to} H _n of the multiplexer 503 are connected to the output side of the drive circuit group 301 mounted on the DUT board 300.

Further, the conductive pin 502Q has a pin arrangement at a position corresponding to the output terminal of the IC under test. Therefore, by mounting the calibration jig 500 on the DUT socket 302, the output terminal Q of the multiplexer 503 is set to the buffer amplifier 30 mounted on the DUT board 300.
Connected to 3 input terminals.

Switching control of the multiplexer 503 is performed by applying a control signal using the conductive pins other than the connecting input terminal H ₁ to H _n, and an output terminal Q.

By mounting the above-described calibration jig 500 on the DUT socket 302, the signals to be input to the analog IC under test can be selected one by one by the multiplexer 503 and taken out to the output terminal Q. Therefore, the signal which is selected and taken out is, for example, the sample hold circuit 30 described with reference to FIG.
Input to 5 and drive circuit group with this sample hold circuit 305
By advancing and falling timing of the signal input through 301, the advance and the delay of the signal can be measured.

An example of a method of calibrating the timing of the analog IC tester using the calibration jig 500 will be described with reference to FIG.

In FIG. 3, 100 is an analog IC tester main body, and 300 is
The point of showing the DUT board is the same as the conventional technique described in FIG.

When performing timing calibration of the analog IC tester main body 100, the calibration jig 500 proposed by the present invention is attached to the DUT socket 302.

By mounting the calibration jig 500 on the DUT socket 302, any one of the input signals given from the drive circuit group 301, in this example, the scan drive signals can be selected and taken out to the output terminal.

Therefore, each scan drive signal can be selected and given to the sample hold circuit 305.

In this example, changeover switches 307A and 307B are provided before and after the clamp circuit 304, and the changeover switch 30
7A and 307B are brought down to the contact A, the clamp circuit 304 is removed thereby, and the scan drive selected by the multiplexer 503 can be directly input to the sample hold circuit 305.

FIG. 4 shows an example of the timing of the scan drive signal DS and the sampling pulse SP. The center of the rising and falling edges of the scan drive signal is taken as the reference timing, and the sampling pulse SP is given to this reference timing.

Therefore, when the scan drive signal DS has the center of rising and falling at the reference timings t ₁ and t ₂ as shown by the solid line in FIG. 4, the sample and hold circuit 30 as shown in FIG. 4C.
The sample hold value output from 5 is fixed to E ₀ ,
It does not change.

On the other hand, as shown by the dotted line F or D in FIG. 4, the delay time of the scanning drive signal advances, and if there is a delay, the sample hold value of the sample hold circuit 305 changes every time the sampling pulse SP is supplied. .

Therefore, this sampling value is amplified by the buffer amplifier 306 and the amplifier 121, AD-converted by the AD converter 122, and supplied to the delay error measuring means 124.

The delay error measuring means 124 is the image processing apparatus 1 described in FIG.
23 can be used as it is.

That is, the image processing device 123 is composed of a computer. It is possible to measure whether or not the delay time of the scan drive signal matches the reference value by operating this computer as a device for examining the change in the value of the AD converted signal in addition to the image processing.

“Effect of device” As described above, according to the present invention, the DUT socket 3
The calibration jig 500 is mounted on 02, the scanning drive signal DS given to the DUT socket 302 is selected by the calibration jig 500, and the selected scan drive signal is sampled and held.
At 305, the center of the rising edge and the center of the falling edge are sampled, and when the sample hold value changes, it can be determined that there is a delay error.

Therefore, in order to minimize this variation, the variable delay element group 11
Scan drive signal DS by adjusting the corresponding elements of 4
It is possible to match the phase of each drive circuit.

This adjustment can be easily performed, and the phases of the respective drive signals after the adjustment exactly match each other.

Therefore, according to the present invention, the adjustment is easy and the adjustment can be performed with high accuracy, and the effect is great for practical use.

[Brief description of drawings]

FIG. 1 is a side view for explaining one embodiment of the present invention,
FIG. 2 is a connection diagram for explaining the circuit structure of the calibration jig according to the present invention, FIG. 3 is a block diagram for explaining a practical example of the calibration jig according to the present invention, and FIG. 4 is its operation. FIG. 5 is a waveform diagram for explaining the above, and FIG. 5 is a block diagram for explaining the conventional calibration method of the analog IC tester. 100 ... Analog IC tester body, 200 ... Analog IC under test,
300… DUT board, 500… Calibration jig, 501… Insulation board, 50
2,502A to 502N, 502Q ... Conductive pins, 503 ... Multiplexers.

Continuation of the front page (56) References JP-A-2-187678 (JP, A) JP-A-2-6768 (JP, A) Jitsukaihei 1-87271 (JP, U)

Claims (1)

(57) [Scope of utility model registration request] 1. A. A plurality of conductive pins implanted in an insulating substrate in the same arrangement as the arrangement of the terminals of the IC under test, and B. Terminals mounted on the insulating substrate and to which signals are applied to the IC under test. A jig for analog IC tester calibration, which is composed of a multiplexer that connects the conductive pin at the corresponding position to the input terminal and the conductive pin at the position corresponding to the output terminal of the IC under test to the output terminal.