JP2513884B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a microprocessor adopting a variable-length instruction format, which is capable of efficiently decoding variable-length instructions and which is provided with an instruction decoder having a simple structure. A microprocessor for executing a variable-length instruction including an extension part added according to the designation of a part, by decoding the basic part, the presence or absence of the following basic part and the expansion part is determined, and the basic part transition A basic unit decoder that outputs a request or an extended unit transition request, and an extended unit decoder that decodes the extended unit to determine whether or not the extended unit is continued and outputs an extended unit continuation request; and the basic unit decoder, A decode sequencer for generating a control signal for instructing the extension decoder to perform decoding according to a predetermined sequence, wherein the decode sequencer generates a control signal for the base decoder in response to the base transition request. A control circuit; a second control circuit for generating a control signal for the extension decoder in response to the extension transition request or extension continuation request; the first control circuit and the second control circuit;
And a third control circuit connected to the control circuit and holding the operation of the first control circuit for the basic part transition request when there is the expansion part transition request or the expansion part continuation request.

[Industrial applications]

The present invention relates to a microprocessor adopting a variable length instruction format. In particular, the present invention relates to a microprocessor having an improved decode sequencer for controlling the decoding order of each part of a variable length instruction, which is composed of a plurality of basic parts of a single instruction and a variable length extension part.

[Conventional technology]

FIG. 10 is a conceptual diagram of the variable length instruction format. Figure 10 shows
It is shown that one instruction to the microprocessor is composed of up to N parts. Such instructions are decoded using multiple cycles. The basic part of each part includes an instruction code, and the extension part includes immediate data and the like. For example, the presence or absence of a subsequent extension part and the meaning of the basic part of the second part are specified based on the basic part of the first part. When there are N basic parts, a meaningful control signal is obtained only after decoding the N basic parts.

FIG. 11 is an example of an orthogonal instruction format assuming a 32-bit microprocessor, and is a diagram showing an instruction format in which an instruction having a maximum of three basic parts can be changed. In this instruction format, the instruction is configured in 16-bit units, and the OP includes an instruction code section and information indicating the presence or absence of the following basic section. R, _Ra , and _Rb are register designation sections, S is an operand size designation section, #I is immediate data, and disp is a displacement section. The operand designation part also includes information indicating the presence or absence of a subsequent extension part. The extension part has a length that is an integral multiple of 16 bits, is placed immediately after the operand specification part, and is used to expand the operand specification part. The extension part further includes information indicating the presence or absence of a subsequent extension part. 16×n (n is an integer including 0) indicates that the length of the extension part can be changed in 16-bit units. The shortened type shortens the execution speed by shortening the bit length of the general operand designation part by 2 bits. In such variable length instruction format, frequently used instructions are assigned to one operand format, and less frequently used instructions are assigned to two or more operand formats. By doing so, frequently used instructions can be executed in a short time, and the types of instructions can be increased. More specific examples of such variable length instructions are shown in FIGS. 12A to 12C.

12A and 12B are diagrams showing a specific example of a two-operand format instruction, and FIG. 12C is a diagram showing a specific example of a one-operand format instruction. FIG. 12A shows a two-operand general type instruction having an 8-bit effective address field, and the first basic part consisting of 16 bits has an instruction code OP, source operand size SS, source operand effective address.
The second basic part is composed of an instruction code OP, a destination operand size DD, and a destination operand effective address ead. Incidentally, exp16/3
Reference numeral 2 is an extension section consisting of 16 bits or 32 bits. No. 12B
The figure shows an 8-bit immediate type instruction. The first basic part is composed of an instruction code OP and immediate data #, and the second basic part is an instruction code, destination operand size DD, destination operand effective address. consists of ead. In this instruction, the expansion part exp16/32 is added only to the second basic part. Figure 12C shows the shortened register-memory transfer instruction, which has the instruction code O
P, register specification Rn, source operand size S
It consists of a basic part consisting of S, a source operand, an effective address or a destination operand, and an effective address eas/ead and an expanded part exp16/32.

As the decoding sequence of such variable length instruction,
The stage transition shown in the figure can be considered. FIG. 13 is a stage transition diagram for decoding an instruction having up to the third basic part at the longest. In addition, a circle indicates a decode stage of each unit, and an arrow indicates a state transition to another decode stage. When the instructions having only the first basic part are continuous, only the decode stage of the first basic part needs to be repeated, but when there are the second and third basic parts and the first, second, and third expansion parts, If the decoding of the succeeding stage is simply performed while referring to the preceding decoding stage, the decoding sequence becomes complicated. This is because the instruction code of the first basic part changes the meaning of the instruction code of the subsequent basic part, and the length of the extension part is also variable.

For example, in order to decode the instruction shown in FIG. 1, the first basic part is decoded, and it is determined from the decoding result that there is the first extension part. Next, the first extension unit is decoded, and if it is determined that the extension unit continues as a result, the decoding process of the first extension unit is repeated. The decoding of the first extension part is completed,
In addition, if it is determined as a result of the decoding of the first basic part that the second basic part is present, a transition is made to the decoding stage of the second basic part. When the second basic part is decoded and it is determined from the decoding result of the second basic part that there is the second expansion part, the process proceeds to the decoding stage of the second expansion part. Then, if it is determined from the decoding result of the second basic part that there is a third basic part, the third basic part is shifted to the decoding stage. If it is determined from the decoding result of the third basic part that the third extended part is present, the third extended part is decoded, and if it is determined from the decoding result of the third basic part that the third extended part and the fourth basic part are not present, Move to the instruction and perform decoding in the same decoding sequence as above. However, in such a decoding sequence, in order to shift to the decoding of the next basic part after the completion of decoding of each expansion part, it is necessary to confirm which basic part the expansion part is associated with and decode that basic part. It is necessary to know the decoding result of. The more state transitions, the more control signals are required to direct the transitions. Therefore, there is a problem that the circuit configuration of the decode sequencer for performing the stage transition shown in FIG. 4 becomes complicated. This problem becomes more serious as the number of basic parts and extension parts constituting one instruction increases. Also, the time required for the decoding process becomes long due to the complexity of the decoding sequencer.

[Problems to be Solved by the Invention]

It is an object of the present invention to provide a microprocessor that can efficiently decode variable length instructions and that has an instruction decoder with a simple configuration.

Another object of the present invention is to provide a microprocessor including an instruction decoder capable of decoding variable length instructions at high speed.

Still another object of the present invention is to provide a microprocessor structure suitable for high integration.

[Means for solving the problem]

The above problem is in a microprocessor that executes a variable length instruction including a basic part including an instruction code and an operand designating part, and an extension part added according to the designation of the basic part to extend the operand designating part. Therefore, by decoding the basic part, the presence or absence of the following basic part and extension part is determined, and a basic part decoder (28, 30, 32A, 32B) that outputs a basic part transition request or an expansion part transition request is used. , The extension unit is decoded to determine whether or not the extension unit is continued, and outputs an extension unit continuation request, an extension unit decoder (34), the basic unit decoder, and a control signal for instructing the extension unit decoder to perform decoding ( OP1 to OP3, ADDM, IMM2, IMM3) and a decoding sequencer (14) for generating a predetermined sequence,
The decode sequencer is responsive to the basic part transition request to generate a control signal for the basic part decoder (421 to 423, 104 to 106), and to respond to the extended part transition request or the extended part continuation request. Second control circuit (44, 120, 424) for generating a control signal for the extension decoder.
426, 114 to 116), the operation of the first control circuit connected to the first control circuit and the second control circuit and corresponding to the basic part transition request is suspended when there is the expansion part transition request or the expansion part continuation request. Third control circuit (101 to 103,111)
And a microprocessor.

[Action]

In the present invention, the decode stage is divided into a basic mode and an extended mode, and the decode stages of the basic portion and the extended portion are separated. Further, the decode stages of the first extension unit, the second extension unit, and the third extension unit are not divided, and the decode stage of each extension unit is made common to simplify the stage transition, thereby making it possible to simplify the configuration of the decode sequencer. .. If the decoding start of the basic part and the decoding start of the extension part conflict at this time, the signal that masks the decoding request of the subsequent basic part and starts the decoding of the extension part is given priority, and the decoding of each extension part is performed. The decoding sequencer is configured so that the decoding of the next basic part starts after the end.

〔Example〕

The stage transition of instruction decoding in one embodiment of the present invention will be described with reference to FIG. In the figure, the circles indicate the decode stages, and the arrows indicate the transitions of the decode stages.

In the present invention, the decode stage is divided into a basic mode and an extended mode, and the decode stages of the basic portion and the extended portion are separated. Further, as shown in FIG. 13, the first expansion portion, the second
The decode stages of the extension unit and the third extension unit are not separated, and the decode stages of the extension units are made common. As a result,
Compared to FIG. 13, in the embodiment of the present invention shown in FIG. 1, there are fewer kinds of state transitions in the decode stage, and the decode sequencer can be simplified.

In this embodiment, if there is no extension part in the instruction, or even if there is an extension part, if data and control signals necessary for operand processing can be prepared in the same decode cycle as the basic part, decoding is performed only in the basic mode. The stage transitions. When the instruction of only the first basic part continues, only the decode stage of the first basic part is repeated. In the case of commands that have up to the third basic part, the first basic part. The decode stage transits in the order of the second basic part and the third basic part, and then transits to the first basic part for decoding the next instruction.
On the other hand, when it is determined that the second basic portion exists and the first extension portion exists at the stage of decoding the first basic portion, and the data and control signal necessary for processing cannot be prepared within the same decoding cycle as the basic portion (for example, (If the immediate data length specified by the operand specification part is too long to be captured in one cycle), the transition request to the second basic part is made to wait in the holding state, and the transition to the extension mode is made to follow the extension part. To decode. As a result of decoding the subsequent extension part, if it is determined that the extension part will continue, the decoding stage of the extension part is repeated. The same applies to the second and third extension units. When it is determined that there is no subsequent extension part, the mode is returned to the basic mode again, and a transition is made to the decoding stage of the second basic part which was held. The stage transition shown in FIG. 5 is realized by including the instruction decoding unit shown in FIG. FIG. 2 shows the principle configuration of the present invention. The instruction to be decoded is a basic part having a predetermined bit length as shown in FIGS. 10, 11 and 12A to 12C, and an integer multiple of the predetermined bit length designated by the basic part. Is a variable length instruction having an extension part of and a base part subordinate to the preceding base part.

In FIG. 2, 1 is a transition request decoding unit, which sequentially reads an instruction from the beginning for each processing unit bit length and determines the presence or absence of a subsequent basic unit and extension unit. Reference numeral 2 denotes a storage circuit such as a latch circuit, which temporarily stores a signal indicating the presence/absence of the basic portion and the extension portion. Reference numeral 3 denotes a decode sequencer, which sequentially outputs a signal for starting decoding of the basic unit and the expansion unit corresponding to the holding decoder of the storage circuit 2 to the basic unit decoder 4A or the expansion unit decode 4B. At this time, when the decoding start of the basic part and the decoding start of the expansion part of the previous instruction conflict, the decoding sequencer 3 masks the decoding request of the subsequent basic part and starts the decoding of the expansion part. Is output with priority.

When the next basic part is decoded after the decoding of each expanded part, the information indicating that the basic part exists is stored in the memory circuit 2. Therefore, even if the decoding of the expanded part is prioritized by the previous period priority control, the subsequent It is possible to shift to the decoding start control of the basic part. This memory circuit 2 and decode sequencer 3
In combination with the priority control of, the configuration of the decode sequencer becomes simpler than in the past.

FIG. 3 is a stage transition diagram more specifically showing a decoding sequence which is an embodiment of the present invention. The states that can be taken in the decoding sequence of this embodiment are the following seven stages.

Basic mode A stage transition occurs when the operation code of the preceding basic part requires a subsequent operation code.

SG1: Instruction head (OP1), that is, test stage for decoding from the first basic part SG2: Stage for decoding second basic part (OP2) of the instruction SG3: Stage for decoding third basic part (OP3) of the instruction Extended mode In the basic mode, transition is made from the basic mode when the data and control signals necessary for the operand-specified Holland processing cannot be prepared within the decode cycle of the basic section.

ADDM: Decode stage in additional mode IMM2: Stage for extracting the second word of immediate data for long data IMM3: Stage for extracting the third word for immediate data for long data WAIT: Two cycles of subsequent circuit for one cycle of decoding In order to achieve synchronization in the case where is required, a transition request to each stage is required.

SGIREQ: Request for decoding of the first basic part (This request is also repeatedly issued when the instruction of only the first basic part continues) SG2REQ: Request for decoding the second basic part SG3REQ: Request for decoding the third basic part ADDMREQ: Addition mode Transition request to IMM2REQ: Transition request issued when there is immediate data in the second word IMM3REQ: Transition request issued when immediate data in the third word is present WAIT: Wait request In addition, ADDM stage, IMM2 stage, IMM3 stage , WA
Dashed arrows pointing from the IT stage to the basic mode indicate transitions to corresponding stages of SG1 to SG3 depending on the preceding basic part.

This is similar to the basic stage transition of the embodiment of the present invention and FIG. The difference from the figure is that the extended mode stage is shown in more detail. Here, the additional mode means an extension mode of an operand designating section in an addressing mode in which multiple indirection and scaling can be used. The transitions at the time of fetching the long immediate data are as follows. The decoding result of the first basic part is 2 on the SG1 stage
Or, if there is 3-word long immediate data, transition to IMM2 stage. Further, when the decoding result of the first basic portion has the 3-word long immediate data, the sequence is such that it transits to the IMM3 stage. Also, a transition request from the SG1 stage to the SG3 stage
SG3REQ is issued when it is determined that the basic part shown in FIG. 3 is present when the first basic part and the second basic part are simultaneously decoded. The weight request WAIT/REQ is SG
1, as it occurs in the SG3 stage.

By the decoding sequence shown in FIG. 3, for example, the MOV instruction shown in FIG. 8 is decoded as follows. Figure 4 shows TRON (The Realtime Operating system Neucleu
s) It is a figure which shows the format of the instruction based on the specification. This MOV
The instruction is a memory-to-memory transfer instruction and is represented as follows in the mnemonic.

MOV:G @@(disp,Rn),@Rm MOV indicates a transfer instruction, and G indicates a general type instruction shown in FIG. Also, @ means indirect addressing, @
@ Indicates double indirect addressing, disp indicates displacement, and Rn and Rm indicate index registers. The EA1 stores a code indicating that the first extension unit is in the additional mode, the EA2 stores the identification code of the indirect addressing of Rm, and the first extension unit uses the Rn as an additional mode.
And a code indicating double indirect addressing by a displacement value is stored. That is, in the above instruction, the memory is accessed at the address of the value obtained by adding the displacement disp to the value in the index register Rn to fetch the operand address. The source data is accessed based on the operand address and transferred to the address corresponding to the value in the index register Rm. OP1, S1, and EA1 in the command are the first basic part, and the part of the subsequent additional mode is the first extension part. OP2, S2 and EA2 are the 2nd basic part. OP1 has the information that it has the second basic part, and EA1 has the information that it has the first extension part.
The first extension (additional mode) is designated by OP1
Subordinate to the basic part. S1 and S2 are operand sizes.

FIG. 5 shows stage transitions when the MOV instruction is decoded based on the decoding sequence according to the present invention. The horizontal direction of FIG. 5 is the time axis, and shows the current stage for each cycle, the next stage identified based on the decoding result at the current stage, and the decoding operation within the cycle.

MOV instruction is 1st basic part + extended part (additional mode) + 2nd
Since it is configured as a basic part, by decoding OP1 at the SG1 stage, SG2 stage as the next stage, ADD
You can see that M stage is required. Since the ADDM stage corresponds to the first extension part, the transition to the SG2 stage is frozen and transitioned to the ADDM stage in the next cycle. In this case, since the length of the extension part is a length that can be processed in one cycle, transition to the SG2 stage occurs in the next cycle. However, because a WAIT request is coming, the decoding of OP2 is made to wait for one cycle (indicated by OP2W), and the current stage is kept as the SG2 stage. OP2 in next cycle
To decode. Since the MOV instruction is up to the second basic part, the next stage is SG1 stage.

Note that commands (registers such as MOV:G@(disp,Rn),@Rm)
In the case of accessing the memory at the address of the value obtained by adding the displacement disp to the value of Rn and transferring the data at that address to the address of the value of register Rm), the displacement disp is Since it can be prepared within the decode cycle, the transition to extended mode is not performed.

FIG. 6 is a block diagram of an instruction decoder which is an embodiment of the present invention for realizing the stage transition shown in FIG. This instruction decoder decodes the instruction supplied from the instruction queue 10 via the instruction queue bus 12.
Capture and decode based on the control signal from 14.

Hereinafter, the case of decoding the variable length instruction of the instruction format shown in FIG. 11 will be described as an example. 64 for instruction queue bus 12
The instruction queue 10 is a bus having a bit width and sends an instruction to the instruction queue bus 12 in units of 64 bits. The data (bit 63 to bit 0) on the instruction cuba 12 is latched by the latch circuit 16 at the timing based on the control signal from the decode sequencer 14.
Held at ~26. In the figure, the number in parentheses indicates the bit number input to the corresponding latch circuit. For example (63:4
8) indicates that 16 bits from bit 63 to bit 48 are input.

The first operation code (OP1) decoding unit 28, the second operation code (OP2) decoding unit 30, the addressing unit decoding unit 32B, and the next stage transition request decoding unit 32A are decoders for decoding the basic unit.
The additional mode decoding unit 34 is a decoder that decodes the extension unit. Immediate data, displacement data, etc. are fetched via the 64-bit input side instruction register 46 and output side instruction register 48. Latch circuit 16
12-bit latch, latch circuit 18 is a 2-input 8-bit latch, latch circuit 20 is a 16-bit latch, and latch circuit 22 is 2
The input 16-bit latch and the latch circuit 24 are 2-bit latches.

The first operation code (OP1) decoding unit 28
The operation code 12 included in the first basic portion fetched by the latch circuit 16 at the timing of the latch control signal S31.
Bits [(63:52), (50:48)] are decoded in the SG1 stage.

The second operation code (OP2) decoding unit 30
Operation code 8 included in the second basic portion fetched by the latch circuit 18 at the timing of the latch control signal S31
Bits (47:40) are decoded in the SG1 stage, and the operation code 8 bits (63:56) fetched in the latch circuit 18 at the timing of the latch control signal S32 are set in the SG2 stage.

The next stage transition request decoding unit 32A and the addressing decoding unit 32B receive the data of the latch circuits 20, 22, 24 to 24 and S41, S42, S43, and perform decoding. Next stage transition request decoding unit 32A The transition request to each stage shown in FIG. 7 is determined. The addressing decoding unit 32B decodes the addressing mode. 16 bits (63:48) are taken into the latch circuit 20 at the timing of the latch control signal S31, and this data is decoded at the SG1 stage. The latch circuit 22 is a 2-input latch,
The SG1 stage takes in 16 bits (47, 32) at the timing of the latch control signal S31, and the SG2 stage takes in 16 bits (63:48) of the latch control signal. The latch circuit 24 outputs 2 bits (57:56) to SG3 at the timing of the latch control signal S33.
Capture on stage.

The additional mode decoding unit 34 uses the 16-bit data (63:4) held in the latch circuit 26 at the timing of the latch control signal S34.
Decode the extension of 8) in the ADDMR stage.

The second operation code (OP2) decoding unit 28
However, it is the first basic part that decodes on the SG1 stage,
This is because the second basic part may be simultaneously decoded. In the case of a general type instruction having two or more operands, if the first operand is register direct (when the data in the register is used as an operand), the second halfword (47: 3
In 2), there is a second operation code to be decoded in the SG2 stage. Only at this time, the first and second operation codes of the instruction are simultaneously decoded. Therefore, SG1
In the stage, unconditionally the second operation decoding unit
18 and the latch circuits 18 and 2 of the addressing decoding unit 32B
If the second halfword is fetched into 2, and the instruction is general type due to the decoding of the first operation code by the OP1 decoding unit 28, and the first operand is register direct, the decoding result of the second operation code is validated. To do. On the other hand, the instruction is not of general type or of general type
When the operand is other than register direct, the decoding result of the second operation code is invalidated, and the decoding result of the first instruction operation code is validated.
At this time, if the first operand of the general type instruction is other than register direct, the SG2 stage transition request is asserted, and the second operation code is decoded in the next cycle (SG2 stage). On the SG2 stage,
The second operation code is the first on the instruction queue bus 12.
Since it is in halfword (63:48), the second operation code decoding unit 30 and the addressing decoding unit 32B
Latch circuits 18 and 22 fetch the first halfword (63:48) data on the instruction queue bus 12 and decode the second operation code and the second operand.

In the present embodiment, the instructions having the third basic portion include fixed bit length bit field instructions and loop instructions such as add compare branch and sub compare branch. These instructions are instructions having four operands, of which two operands are designated by the first operand and the second operand designating part of the general type first and second basic parts,
The third primitive is used to specify the remaining two operands. The third basic part does not have an operation code for discriminating an instruction (the instruction type has already been specified by the operation code of the first and second basic parts and has already been discriminated at the time of decoding the third basic part) register number or immediate Have data. Therefore, in SG3 stage, the decoder specifies the size of immediate data (57:5
The constant generation instruction is output only by inputting 6). Register number and immediate data are input instruction register
It is transmitted to the subsequent circuit through 46 and the output side instruction register.

In one embodiment, the extensions are used to implement additional mode addressing. The additional mode addressing is an addressing mode in which multiple indirection and scaling can be used. The operand address is basically obtained by the following formula, and multiple indirect addressing is realized by repeatedly applying this address calculation.

[Base address + index * scale + displacement]

Therefore, the base address of the first stage is designated by the operand designation part of the basic part, and the index, scale, and displacement are designated for each stage in the following format.

E: End designation I: Indirect designation Rn: Index register number M: Index designation XX: Scale designation D: Displacement designation D4: Displacement data (In the case of 16-bit and 32-bit, extended to EXP field of extension) Add this The mode addressing designation portion is decoded by the additional mode decoding, and the first half word (15:0) on the instruction queue bus 12 is latched and decoded in each stage in the ADDM stage. Operation code decoding unit 28,3
The decoding result of 0 is held in the latch circuits 36 and 38 at the timing of the latch control signal S03. One of the held outputs is selected to supply a micro address to the micro program ROM 65 shown in FIG. 9 and a tag to the pipeline control unit 64. The decoding results of the addressing decoding unit 32A and the next stage transition request decoding unit 34B are held in the latch circuit 42 at the timing of the latch control signal S03, and the decoding results of the additional mode decoding unit 34 are held in the latch circuit 44. These held data give an address calculation instruction and a constant generation instruction to the address generation section 68 and the constant generation section 67 which are the constituent elements of the instruction execution section 81 of FIG.

The control of the instruction decoder of FIG.
Done by FIG. 7 is a block diagram of the decode sequencer 14 which is an embodiment of the present invention.

In the decode sequencer of this embodiment, the presence or absence of the extension part is not taken into consideration in the transition of the basic state, and the above control signals are generated so that the basic transition request is frozen while the extended transition request is asserted. In addition, since the decoding spans a plurality of cycles, a decoding unit is provided to perform decoding corresponding to the first operation code, the second operation code, and the additional mode, and the decoded signal is referred to in the subsequent cycle by each stage signal. The latch circuit is controlled for each of the divided decoding units. Further, when there is a wait stage or a wait request from the outside, the output side latch is frozen and the state is held.

The details of the decode sequencer of this embodiment will be described below in detail. The decode sequencer in the present embodiment includes basic transition request signals S11, S12, S13 and extended transition request signal S1 output from the next stage transition request decoding unit 32A.
4, S15, S16, the extension continuation request signal S18 from the additional mode decoding unit 34, and the four-phase clock signals φ _{0 to} φ shown in FIG.
Based on ₃ , the latch control signal on the input side and the output side, and the enable signal for each decoding section are generated. The latch circuit 42a, which is a part of the latch circuit 42, temporarily holds the decode outputs S11 to S17 output from the next stage 25 transition request decoding unit 32A. The outputs of the bit latch circuits 421 to 423 are
It becomes the first basic stage transition request signal SG1REQ (S21), the second basic stage transition request signal SG2REQ (S22), and the third basic stage transition request signal SG3REQ (S23). The outputs of the bit latch circuits 424 to 427 are the additional mode stage transition request signal ADDM.REQ (S24), the 64-bit immediate transition request signal IMM2REQ (S25), the 96-bit immediate transition request signal IMM3REQ (S26), and the wait request signal WAIT, respectively.・
It becomes REQ (S27). The decode output S18 of the additional mode decoding unit 34 is temporarily held in the latch circuit 44 and output as the additional mode continuation signal ADDM•CN (S27). The data held in the bit latch circuits 421 to 423 is the AND gate 10 respectively.
It is held in the bit latch circuits 104, 105 and 106 at the timing of the clock signal φ ₁ via ₁ , 102 and 103. The AND gates 101 to 103 have a function of masking a basic part transition request while there is an extension part transition request. Bit latch circuit 104-1
The stored data S41, S42, S43 of 06 are input to the OR gate 107, and the logical sum output thereof is further supplied to one input terminal of the AND gate 108. The other input terminal of the AND gate 108 is supplied with the wait request signal WAITPL (S ₀₁ ) from the pipeline control unit 64 (see FIG. 9) via the inverter 109. The OR gate 107 has a function of detecting that the current stage is the basic unit stage. The AND gate 108 has a function of detecting that there is no wait request WAITPL and basic part transition request, and generating a signal for supporting the capture of the outputs S11 to S13 of the next stage transition request decoding unit. The output of the AND gate 108 is supplied to one input terminal of the AND gate 110, and the clock signal φ ₃ is supplied to the other input terminal of the AND gate 110. The output of the AND gate 110 is used as a latch timing signal for fetching the decode outputs S11 to S13 into the bit latch circuits 421, 422, 423. The other input terminals of the AND gates 101 to 103 are supplied with the output of the NOR gate 111 which controls the mask of the basic part transition request. To the input terminal of the NOR gate 111, the outputs of the bit latch circuits 424 and 426 are respectively supplied as signals S34 and S36 via the OR gate 112 and the AND gate 113, and further the data S25 and S27 held in the bit latch circuits 425 and 427 are directly supplied, The presence/absence of a transition request to the extension part is detected. The data S34, S25, S36 are respectively bit latch circuits 114, 11 at the timing of the clock signal φ _1.
It is held at 5,116, and the extension decode enable signal ADDM
(S44), IMM2 (S45) and IMM3 (S46) are output. Data S44 and S45 are bit latch circuits 117 and 118, respectively.
Are stored as data S54 and S55. The data S54 is supplied to one input terminal of the AND gate 120, and the data S55 is supplied to the other input terminal of the AND gate 113. The AND gate 113 has a function of transferring IMM3REQ to the bit latch circuit 116 when there is IMM3REQ in the IMM2 stage. The AND gate 120 has a function of detecting that it is determined that the extension mode continues as a result of decoding the extension portion during the extension mode, and transfers ADDM.REQ to the bit latch circuit 114. The output of the inverter 109 and the clock signal φ ₃ are supplied to the AND gate 119, and the AND gate 1
The output of 19 is used as a latch timing signal as a timing signal for engaging the decode outputs S14 to S17 to the bit latch circuits 117, 118, 424 to 427.

The decode output S18 from the additional mode decoding unit 34 is held in the latch circuit 44 at the output timing of the AND gate 119, and is supplied to the other input terminal of the AND gate 120 as the additional mode continuation signal ADDM.CN (S28). ..
Wait request signal WAIT REQ (S27) is clock signal φ ₁
It is held in the bit latch circuit 121 at the timing of and is supplied to the NOR gate 122 as a wait signal WAIT (S47). The NOR gate 122 has a function of detecting the presence or absence of WAIT or WAIT.PL. The output of the NOR gate 122 and the clock signal φ ₃ are supplied to the AND gate 123, and the latch control signal S03 is output from the AND gate 123 when there is no wait request. The latch control signal S03 is used as a latch timing signal for the latch circuits 36, 38, 44 and 48 shown in FIG. The output of the AND gate 101 is the latch control signal O
It is supplied as P1I (S31) to enable the latch circuits 16 to 20 shown in FIG. The output of the AND gate 102 is supplied as a latch control signal OP21 (S32) to enable the latch circuits 18 and 22 shown in FIG. The output of the AND gate 103 is the latch control signal OP3I (S3
As 3), it is supplied to enable the latch circuit 24 shown in FIG. The held data S41 of the bit latch circuit 104 is supplied to the OP1 decoding unit 28 and the addressing decoding unit 32B shown in FIG. 10 as the first basic unit decoding enable signal OP1. The data S42 held by the bit latch circuit 105 is supplied to the OP2 decoding unit 30 and the addressing decoding unit 32B shown in FIG. 6 as the second basic unit decoding enable signal OP2. The data S43 held in the bit latch circuit 106 is supplied to the addressing decoding unit 32B shown in FIG. 6 as the third basic unit decoding enable signal OP3. Each decoding unit starts decoding in response to the decode enable signals OP1 to OP3. Also, bit latch circuit
The held data S44, S45, S46 of 114 to 116 become extension decode enable signals ADDM, IMM2, IMM3, respectively. The extended portion decode enable signal ADDM is supplied to the additional mode decoding portion 34 in FIG. 6 to instruct the start of decoding of the extended portion. S45 and S46 are held in the latch circuit 44 as decode enable signals for instructing immediate and 64-bit immediate decoding, and the held data gives a constant generation instruction to the constant generation unit.

To explain the operation of the decode sequencer, FIG. 8 shows an operation timing at the time of decoding the memory-memory transfer instruction MOV shown in FIG. 4 as an example. still,
In FIG. 8, the same symbols as in FIG. 7 indicate the same signals.

After the processing of the previous instruction is completed, the first basic part transition request signal SG1REQ (S21) becomes “1” at the rising timing of the clock signal φ ₃ . At this time, the second basic part transition request signal SG2REQ
(S22), third basic part transition request signal SG3REQ (S23), extended part transition request signal ADDM/REQ (S24), IMM2REQ (S25), IM
M3REQ (S26), wait request signal WAIT.REQ (S27), and additional mode continuation signal ADDM.CN (S28) are all "0".
Therefore, the output of the NOR gate 111 is "1", and the latch control signal OP1I (S31) is "1", OP2I (S32) and OP3I (S33).
Is "0", the corresponding data on the instruction queue bus 12 is fetched into the latch circuits 16, 18, 20, 22. At the next rising timing of the clock signal φ ₁ , the first basic part decode enable signal OP1 (S41) becomes “1”, and the first basic part is decoded. At this time, the second basic part decode enable signal OP2 (S42) and the third basic part decode enable signal (S43) are "0", indicating the disable state.

At the rising timing of the next clock signal φ ₃ , the first
Basic part transition request signal SG1REQ (S21) is “0”, second basic part transition request signal SG2REQ (S22) and extended part transition request signal ADDM
・Both REQ (S24) become "1". However, Noah Gate 11
Since the output of 1 is "0", the second basic unit transition request signal SG2
REQ (S22) is masked by the AND gate 102, and the extension transition request signal ADDM.REQ (S24) has priority. Therefore, at the next rising timing of the clock signal φ ₁ , the second basic part decode enable signal OP2 (S42) remains “0” and the disabled state, and the extended part transition request signal.
ADDM·REQ (S24) is taken into the bit latch circuit 44,
The extension decode enable signal ADDM (S44) becomes "1", and the first extension (additional mode) is decoded.

The extension transition request signal ADDM•REQ (S24) becomes “0” at the next rising timing of the clock signal φ ₃ . At this time, the additional mode continuation signal ADDM•CN (S28) is "0", which indicates that there is no subsequent extension part, and therefore the end of the additional mode stage is instructed. In response to the end of the additional mode stage, NOR gate 111 becomes "1", and AND gate 101-
The mask by 103 is released. As a result, the latch control signal OP2I (S32) becomes "1", and the data on the instruction queue bus 12 is taken into the latch circuits 18 and 22. At the next rising timing of the clock signal φ ₁ , “1” of the second basic part transition request signal SG2REQ (S22) is taken in by the bit latch circuit 105 and the second basic part decode enable signal OP2 (S42).
Becomes "1", and the second basic part is decoded. However, at this time, the wait request signal from the pipeline control unit
WAIT/PL (S01) becomes "1" and a wait request is coming. Therefore, the output of the NOR gate 122 is "0", and the output side latch circuit control signal (S03) output from the AND gate 123
Is fixed to "0" regardless of the logic value of the clock signal phi _3, the decoding result of the second basic section also rises following the clock signal phi ₃ is not taken into the latch circuit 38. Similarly, since the AND gates 110 and 119 are closed in response to the wait request, new data is not taken into the bit latch circuit 42a. Therefore, the state of the decode sequencer does not change for one cycle and is in a waiting state.

At the next rising timing of the clock signal φ ₁ , the wait request signal WAITPL (S01) becomes "0" and the wait state is released. Since the latch circuit signal (S03) becomes "1" at the next rising timing of the clock signal φ ₃ , the decoding result of the second basic portion decoded in the previous cycle is fetched by the latch circuit 38. At this time, the first basic unit transition request signal SG1REQ (S21) and the latch control signal OP1I (S3
1) becomes “1” and the second basic part transition request signal SG2REQ (S2
2), the latch control signal OP2I (S32) becomes "0", and the decoding process of the MOVE instruction ends. In the next cycle, the decoding process of the following next instruction is started.

FIG. 9 is a block diagram showing a schematic configuration of a microprocessor which is an embodiment of the present invention. The microprocessor shown in the figure is configured as a monolithic LSI, and has an instruction control unit 80 that performs pipeline control, instruction decoding, and the like.
It includes an instruction execution unit 81 for executing instructions, a memory control unit 82 for controlling a built-in cache memory and the like, and a bus control unit 83 for controlling exchange of information with the outside of the LSI chip. The instruction control unit control unit 80 includes an instruction queue 61, an instruction decoder 62 having the configuration shown in FIGS. 11 and 12, and a decode sequencer.
63, a pipeline control unit 64, a microprogram ROM 65 for storing microcode and outputting a control signal based on a microaddress, and an instruction register 66. The instruction execution unit 81 includes a constant generation unit 67, an address generation unit 68 including an address adder and a program counter, a register file 70, and a calculation unit 70. The calculation unit 70
Equipped with ALU, barrel shifter, encoder, BCD checker, etc. The memory controller 82 includes an instruction access controller 71 and an operand access controller 72. The instruction access control unit 71 includes a cache memory for instructions, a TL
B, equipped with a protection check circuit, etc. The operand access control unit 72 includes an operand cache memory, a TLB, a protection check circuit, a store buffer and the like. The bus control unit 83 includes an address control unit 73 having an interface function with the outside of the LSI chip and having an address monitoring circuit and the like, a bus monitoring control unit 74 for generating control signals for block access, a data transmission/reception unit 75, and the like. Composed of. Needless to say, the decoder and the decode sequencer according to the present invention are not limited to the microprocessor having the configuration shown in FIG.

〔The invention's effect〕

As described above, according to the microprocessor of the present invention, the instruction is sequentially read from the head, the presence or absence of the subsequent basic unit and the extension unit is determined, the presence or absence thereof is temporarily stored in the memory circuit, and the presence of the subsequent basic unit When there is a conflict between the decode start request and the decode start request of the extension part, the decode sequencer configuration is simplified by controlling the decode start request of the basic part to be given priority over the decode start request. Can be converted. In addition, the simplification of the decoding sequencer improves the processing speed and is suitable for integration into an integrated circuit.

[Brief description of drawings]

FIG. 1 is a stage transition diagram of instruction decoding which is an embodiment of the present invention, FIG. 2 is a block diagram of an essential part of an instruction decoding unit which is an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. FIG. 4 is a stage transition diagram of the instruction decoding, FIG. 4 is a diagram showing an instruction format of the MOV instruction, FIG. 5 is a stage transition diagram when the MOV instruction is decoded according to an embodiment of the present invention, and FIG. 6 is the present invention. 7 is a block diagram of an instruction decoder which is an embodiment of the present invention, FIG. 7 is a block diagram of a decode sequencer which is an embodiment of the present invention, and FIG. 8 shows an operation of the decode sequencer shown in FIG. FIG. 9 is a timing chart for explaining, FIG. 9 is a block diagram of a microprocessor which is an embodiment of the present invention, FIG. 10 is a conceptual diagram of a variable length instruction, and FIG. 11 is variable up to an instruction having a third basic part. 12A and 12B are conceptual diagrams showing a two-operand general type instruction, FIG. 12C is a conceptual diagram showing a shortened register-memory transfer instruction, and FIG. 13 is a variable length. A stage transition diagram that can be considered as an instruction decoding sequence, 1... Transition request decoding unit 2... Memory circuit 3... Decoding sequencer 4A... Basic unit decoder 4B... Expansion unit decoder 10... Instruction queue 12... Instruction queue Bus 14... Decode sequencer 16,18,20,22,24,26,36,38,42,44……Latch circuit 28……First operation code decoding unit 30……Second operation code decoding unit 32A…… Next stage transition request decoding unit 32B ......Addressing mode decoding unit 34 ……Additional mode decoding unit 40 ……Selector 46 ……Input side register 48 ……Output side register

Claims (5)

(57) [Claims] 1. A microprocessor for executing a variable length instruction including a basic part including an instruction code and an operand designating part, and an extension part added according to the designation of the basic part to extend the operand designating part. By decoding the basic part, it is possible to determine the presence or absence of the following basic part and extension part, and a basic part decoder that outputs a basic part transition request or an expansion part transition request; and by decoding the expansion part, An extension section decoder that determines whether or not the extension section is continued and outputs an extension section continuation request; and a decoding sequencer that generates a control signal instructing the basic section decoder and the extension section decoder to perform decoding according to a predetermined sequence. The decode sequencer includes a first control circuit that generates a control signal for the basic section decoder in response to the basic section transition request, and the extended section decoder in response to the extended section transition request or the extended section continuation request. A second control circuit for generating a control signal for the first control circuit and a first control circuit connected to the first control circuit and the second control circuit and responding to the basic section transition request when there is the extended section transition request or the extended section continuation request. A microprocessor comprising a third control circuit for holding the operation of the circuit. 2. The microprocessor further holds an instruction bus for supplying an instruction, a first input latch circuit connected between the basic unit decoder and the instruction bus, and an output of the basic unit decoder. A first output latch circuit; and a second output latch circuit that holds the output of the extension decoder. Input operations of the first input latch circuit and the first and second output latch circuits are controlled by the decode sequencer. The microprocessor according to claim 1, wherein the microprocessor is provided. 3. The basic section decoder includes: an operation code decoding section for decoding an operation code, an addressing mode decoding section for decoding an addressing mode, and a next stage transition request decoding for determining the presence or absence of a subsequent basic section or extension section. The microprocessor according to claim 1, further comprising: 4. The operation code decoding unit comprises:
First to decode the operation code of the first basic part
An operation code decoding unit and a second decoding unit for decoding the operation code of the second basic unit
The microprocessor according to claim 3, further comprising an operation code decoding unit. 5. The first control circuit includes: a first latch circuit that holds the basic unit transition request; and a second latch circuit that holds the output of the first latch circuit and outputs it as a basic unit decode enable signal. A first gate circuit connected between the first latch circuit and a second latch circuit, wherein the second control circuit holds a third latch circuit that holds the extension transition request; A fourth latch circuit which holds the output of the third latch circuit and outputs it as an extension decode enable signal, and an output of the third latch circuit, and when there is the extension transition request or the extension continuation request, the first latch 2. The microprocessor according to claim 1, further comprising a second gate circuit that controls a gate circuit to prohibit the output of the first latch circuit from being transferred to the second latch circuit.