JP2504502B2 - Integrated circuit card - Google Patents

Description

The present invention relates to an integrated circuit card (hereinafter referred to as an IC card) having a semiconductor integrated circuit chip built therein, and particularly to data with a card reader. The present invention relates to a data protection circuit that saves, restores, and saves data in an IC card by detecting a failure when power is not supplied from the card reader side during communication.

(Prior Art) In some IC cards, an internal circuit operates when a power supply, a clock signal, and a reset signal are supplied from the card reader side during data communication with a card reader.

However, if the power is not supplied due to some cause (power failure, etc.) during the data communication, the data during communication at this time is stored in the storage circuit section of the internal circuit as it is, and thus the abnormal data is stored. As a result, the data communication with the card reader cannot be started normally next time.

(Problem to be Solved by the Invention) As described above, the present invention has a problem that abnormal data is stored when a failure occurs when power is not supplied from the card reader side during data communication between the card reader and the IC card. SUMMARY OF THE INVENTION It is an object of the present invention to provide an integrated circuit card capable of detecting a failure and performing protection processing such as saving, restoring, and saving of data.

[Structure of the Invention] (Means for Solving the Problems) An integrated circuit card of the present invention is an integrated circuit chip in which an internal circuit including a power cutoff detection circuit, a power supply switching circuit, an internal oscillator, and a control circuit is formed; In the integrated circuit card having a power supply, the power cutoff detection circuit has a function of detecting when the external power supply is cut off, and the power supply switching circuit replaces the external power supply by the detection output of the power cutoff detection circuit. The internal power supply has a function of switching and supplying to an internal circuit of an integrated circuit chip, the internal oscillator has a function of receiving a detection output of the power cutoff detection circuit and starting generation of an internal clock, and the control circuit has When the external power is supplied, the operation is controlled based on the clock supplied from the outside, and when the detection output of the power cutoff detection circuit is received, the internal oscillation is performed. On the basis of the internal clock generated in, check whether the data in the middle of the data communication that was performed when the external power supply was cut off is correct, if it is not correct, reject this data, if it is correct, protect the data, After the data protection processing operation is completed, the internal clock generating operation of the internal oscillator is stopped and the internal power supply to the internal circuit of the integrated circuit chip is cut off.

(Operation) When power is not supplied from the card reader side (when the power supply voltage is below the specified value), this is automatically detected and switching is made to use the internal power supply as the power supply for the chip internal circuit. After the internal clock is output from the internal oscillator to perform the data protection processing, the internal power supply to the chip internal circuit can be cut off.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a part of the circuit built in the IC card and a part of the terminals of the IC card. 1 is an external power supply terminal to which power is supplied from the card reader side, 2 is an external clock terminal to which an external clock signal is supplied from the card reader side,
Reference numeral 3 is an external reset terminal to which an external reset signal is supplied from the card reader side, and 4 is a ground terminal. Reference numeral 5 denotes an internal power source formed on the IC chip (or may be outside the IC chip, in short, built in the IC card). The power cutoff detection circuit 6 compares the external power supply terminal voltage with the internal power supply voltage to detect whether the former has become a predetermined value or less (that is, whether the external power supply has been stopped). This detection circuit 6
Is inverted by the inverter 7 and applied to the gate of the P-channel MOS transistor 8 for the first switch. One end of this transistor 8 is connected to the external power supply terminal 1, and the other end is connected to the internal power supply line 9,
The internal power supply line 9 is connected to a power supply terminal of a chip internal circuit (each circuit described later and memory not shown). The output of the inverter 7 becomes one input of the NAND gate 10, and the output of the NAND gate 10 is connected to the gate of the P-channel MOS transistor 11 for the second switch. One end of the transistor 11 is connected to the internal power supply 5, and the other end is connected to the internal power supply line 9. An internal power supply cutoff signal, which will be described later, is applied to the other input of NAND gate 10. The detection circuit 6, the inverter 7, and the NAND gate 10 are supplied with an internal power supply voltage as an operation power supply so that they can always operate.

Therefore, when the external power is supplied, the output of the detection circuit 6 is “1”, the output of the inverter 7 is “0”, the first switching transistor 8 is on, and the NAND gate 10 is turned on.
Is "1", the second switching transistor 11 is off, and the external power supply voltage is supplied to the chip internal circuit. On the other hand, when the external power is not supplied, the output of the detection circuit 6 is “0”, the output of the inverter 7 is “1”, the first switching transistor 8 is off, and the output of the NAND gate 10 is “0”. "The second switching transistor 11 is turned on, and the internal power supply voltage is supplied to the chip internal circuit. After that, when the NAND gate 10 is supplied with the "0" level internal power cutoff signal, its output becomes "0", and the second switching transistor 11 is turned off.
The internal power supply voltage is not supplied to the chip internal circuit.

On the other hand, 12 is an internal oscillator, which is supplied with an internal power supply voltage as an operating power supply, and when "1" is given to its clock enable terminal, starts an oscillation operation and outputs an internal clock. Since the output of the NAND gate 10 is inverted by the inverter 13 and input to the clock enable terminal, when the internal power supply voltage is supplied to the chip internal circuit (that is, the output of the NAND gate 10 is "0", The internal clock is output when the output of the inverter 13 is "1". Clock switching circuit 14
The external clock input is input via the input buffer 15, the internal clock is input, and the output of the detection circuit 6 is input as the switching control input. When the output of the detection circuit 6 is "1", the external clock is selected and output, when it is "0", the internal clock is selected and output, and the selected output is supplied to the chip internal circuit. Also,
External reset input is OR gate via input buffer 16
The output of the detection circuit 6 is inverted by the inverter 18 and becomes the other input of the OR gate 17. As a result, when the output of the detection output 6 is "1", the output of the inverter 18 becomes "0", and the external reset input is given as a reset input to the chip internal circuit via the input buffer 16 and the OR gate 17. On the other hand, when the output of the detection circuit 6 is "0", the output of the inverter 18 is "1" and the output of the OR gate 17 is "1".

On the other hand, the CPU (central processing unit) 19 has a built-in predetermined control program and fixed data, is capable of program control, and has a normal processing function for performing data communication between the IC card and the card reader. In addition, it has a function of data protection processing such as restoration, saving, and saving of data inside the card when power is not supplied from the card reader side.

Here, the flow of the data protection processing will be briefly described.
An interrupt occurs when the output of the detection circuit 6 becomes "0". In order to check whether this interrupt is an error due to external noise, etc., a "0" level ▲ ▼
A signal is output and the detection output buffer 20 is activated by this signal. The output of the detection circuit 6 is input to the buffer 20, and the output of the buffer 20 is fetched as external power supply monitoring data. In this case, if this data is "0", it means that the external power supply is not supplied, and therefore it is continuously checked whether or not the data in the middle of communication is correct. If it is not correct, this data is rejected, and if it is correct, it is saved in a memory unit (not shown), and then the internal power supply control register 21 is selectively designated and "1" is written in it. The output Q of the register 21 cuts off the internal power supply to the chip internal circuit (disconnects the internal power supply) to stop the operation of the chip internal circuit such as the CPU 19, but write "1" above. At the same time, if the internal power supply is disconnected, abnormal processing may occur, so a command that puts the CPU19 in a hardware-safe state (for example, a stop command such as HALT)
It is desirable to disconnect the above-mentioned internal power source after executing the above. Therefore, a delay timer circuit 23 including, for example, a plurality of stages of shift registers 22 ... . That is,
Input the output Q of the register circuit 21 to the timer circuit 23,
The output of the timer circuit 23 and the output Q of the register circuit 21
And are input to the NAND gate 24, and the output of the NAND gate 24 is used as an internal power cutoff signal. The above register
It is desirable that the 21 and the timer circuit 23 be used for the same reason as above even at the end of the normal data communication process. Generate a reset pulse to register above
21 and the reset input R of the timer circuit 23.

The present invention is not limited to the above embodiment, and various modifications can be made to the specific circuit for realizing the required function.

[Effects of the Invention] As described above, according to the integrated circuit card of the present invention, during the data communication between the card reader and the IC card, the failure of the power supply from the card reader side is detected to detect the data protection process. Since it can be performed, the reliability of the data of the IC card is increased, and the application field of the IC card can be expanded.

[Brief description of drawings]

FIG. 1 is a structural explanatory view showing an embodiment of an integrated circuit card of the present invention. 6 ... Power interruption detection circuit, 7 ... Inverter, 8,11 ...
Switch MOS transistor, 9 ... Internal power supply line, 10 ...
… NAND gate, 12… Internal oscillator, 14… Clock switching circuit, 19… CPU, 21… Control data register, 23…
… Timer circuit, 24… Nand gate.

Claims (1)

(57) [Claims] 1. An integrated circuit card comprising an integrated circuit chip in which an internal circuit including a power cutoff detection circuit, a power supply switching circuit, an internal oscillator and a control circuit is formed, and the power cutoff detection circuit is external. The power supply switching circuit has a function of detecting when power is cut off, and the power supply switching circuit has a function of switching and supplying the internal power supply to the internal circuit of the integrated circuit chip in place of the external power supply by the detection output of the power supply cutoff detection circuit. However, the internal oscillator has a function of receiving the detection output of the power cutoff detection circuit and starting the generation of an internal clock, and the control circuit operates on the clock supplied from the outside when the external power is supplied. Based on the internal clock generated by the internal oscillator when the detection output of the power cutoff detection circuit is received, the operation is controlled based on the internal clock generated when the external power supply is cut off. It is checked whether the data in the middle of the data communication that was made is correct, and if it is not correct, this data is rejected, and if it is correct, data protection processing is performed, and after the data protection processing operation is completed, the internal clock of the internal oscillator An integrated circuit card having a function of stopping generation operation and controlling internal power supply to an internal circuit of an integrated circuit chip.