JP2503266B2 - Thin film transistor matrix - Google Patents
Thin film transistor matrixInfo
- Publication number
- JP2503266B2 JP2503266B2 JP3697989A JP3697989A JP2503266B2 JP 2503266 B2 JP2503266 B2 JP 2503266B2 JP 3697989 A JP3697989 A JP 3697989A JP 3697989 A JP3697989 A JP 3697989A JP 2503266 B2 JP2503266 B2 JP 2503266B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- electrode
- film transistor
- scanning signal
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 27
- 239000011159 matrix material Substances 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 24
- 210000002858 crystal cell Anatomy 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 8
- 101100489584 Solanum lycopersicum TFT1 gene Proteins 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 210000004027 cell Anatomy 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】 〔概 要〕 アクティブマトリクス型液晶表示装置に用いる薄膜ト
ランジスタ(TFT)マトリクスに関し、 製造工程を複雑化することなく、液晶に印加する電圧
のシフトを無くして、完全な交流駆動を実現することを
目的とし、 一方の絶縁性基板上に、複数個の画素電極と該画素電
極に対応付けられた複数個の薄膜トランジスタとをマト
リクス状に配列し、該薄膜トランジスタの第1の被制御
電極を前記画素電極、第2の被制御電極をデータ信号
線、制御電極を走査信号線にそれぞれ接続し、且つ他方
の絶縁性基板上に前記画素電極と相対する共通電位に接
続された対向電極を配設した薄膜トランジスタマトリク
スの構成において、前記一方の絶縁性基板上にさらに薄
膜トランジスタと同一構成で且つ同一接続関係を有する
補償素子を該トランジスタマトリクスに対応して設ける
とともに、走査信号線に隣接して走査線を付設し、該付
加走査線に前記補償素子の制御電極を接続し、且つ前記
走査信号線に印加する走査信号の反転信号を印加するよ
うにした構成とする。DETAILED DESCRIPTION OF THE INVENTION [Outline] A thin film transistor (TFT) matrix used in an active matrix liquid crystal display device, a complete AC drive without complicating the manufacturing process and eliminating the voltage shift applied to the liquid crystal. In order to realize the above, a plurality of pixel electrodes and a plurality of thin film transistors associated with the pixel electrodes are arranged in a matrix on one insulating substrate, and a first controlled target of the thin film transistors is provided. A counter electrode having an electrode connected to the pixel electrode, a second controlled electrode connected to a data signal line, a control electrode connected to a scanning signal line, and connected to a common potential facing the pixel electrode on the other insulating substrate. In the structure of the thin film transistor matrix in which the above-mentioned one is disposed, the one thin film transistor has the same structure and the same connection relationship as the thin film transistor on the one insulating substrate. Compensation element is provided corresponding to the transistor matrix, a scanning line is provided adjacent to the scanning signal line, the control electrode of the compensation element is connected to the additional scanning line, and scanning is applied to the scanning signal line. The configuration is such that an inverted signal of the signal is applied.
本発明は、アクティブマトリクス型液晶表示装置に用
いる薄膜トランジスタ(TFT)マトリクスに関する。The present invention relates to a thin film transistor (TFT) matrix used in an active matrix type liquid crystal display device.
多数の表示セルをマトリクス状に配列し、その各表示
セルを薄膜トランジスタ(TFT)で駆動するアクティブ
マトリクス型液晶表示装置においては、液晶を安定化し
良好な表示を得るため、液晶層に印加される電圧から直
流成分を完全に除去し、交流電圧のみを印加する必要が
ある。In an active matrix liquid crystal display device in which a large number of display cells are arranged in a matrix and each display cell is driven by a thin film transistor (TFT), the voltage applied to the liquid crystal layer in order to stabilize the liquid crystal and obtain a good display. It is necessary to completely remove the DC component from the DC voltage and apply only the AC voltage.
第4図に従来のアクティブマトリクス型液晶表示装置
の画素1個分の等価回路を、第5図にTFTの駆動波形と
液晶に印加される電圧波形を示す。FIG. 4 shows an equivalent circuit of one pixel of the conventional active matrix type liquid crystal display device, and FIG. 5 shows a driving waveform of the TFT and a voltage waveform applied to the liquid crystal.
第5図に示すように、ゲート電圧VGがオフになる時、
ソース(画素)電圧V5がΔVだけ変化する現象がある
が、この変化の方向は正フレーム,負フレームともに同
一で、いずれもマイナス方向にシフトする。また、この
シフト量ΔVは次式で表される。As shown in FIG. 5, when the gate voltage V G is turned off,
There is a phenomenon that the source (pixel) voltage V 5 changes by ΔV, but the direction of this change is the same in both the positive frame and the negative frame, and both shift in the negative direction. Further, this shift amount ΔV is expressed by the following equation.
ΔV=(CGS/CLC+CGS)×VG …… ここで、CGSはゲート容量、CLCは液晶セル容量を示
す。ΔV = (C GS / C LC + C GS ) × V G ...... where C GS is the gate capacitance and C LC is the liquid crystal cell capacitance.
なお図の1は薄膜トランジスタ、G,S,Dはゲート電
極,ソース電極,ドレイン電極、VCは共通電位、VGは走
査信号、VDは表示データ電圧、VSはソース電極電位であ
る。In the figure, 1 is a thin film transistor, G, S and D are gate electrodes, source electrodes and drain electrodes, V C is a common potential, V G is a scanning signal, V D is a display data voltage, and V S is a source electrode potential.
従来この電圧シフトによる直流成分を補償して交流駆
動とするために、共通電極電位VCをΔVだけシフトする
方法が採られている。この方法では画素のオン,オフに
関係なく、全画素に対して共通電位VCをシフトしてしま
うので、直流成分を完全に補償することはできず、完全
な交流駆動とはならない。そのため、表示特性が悪化す
る問題を解消することはできない。Conventionally, in order to compensate the direct current component due to this voltage shift to drive the alternating current, a method of shifting the common electrode potential V C by ΔV has been adopted. In this method, the common potential V C is shifted for all pixels regardless of whether the pixel is on or off, so that the direct current component cannot be completely compensated and complete alternating current drive cannot be achieved. Therefore, the problem that the display characteristics are deteriorated cannot be solved.
その原因は、式の液晶セル容量CLCが液晶のオン状
態とオフ状態で異なり、その変化の割合が通常の液晶で
は非常に大きいためである。一例をあげれば、画素サイ
ズ250μm□,セルギャップ5μmの液晶セルの容量CLC
が、オフ状態の時1pFであるものが、オフ状態では0.5pF
となり、約2倍程度の差がある。The reason is that the liquid crystal cell capacitance C LC of the formula is different between the on-state and the off-state of the liquid crystal, and the change rate is very large in the normal liquid crystal. As an example, the capacitance C LC of a liquid crystal cell with a pixel size of 250 μm □ and a cell gap of 5 μm
Is 1pF in the off state, but 0.5pF in the off state
There is a difference of about 2 times.
このような不都合を無くするための方法の一つとし
て、従来、第6図に示すように、液晶セル容量CLCに並
列に蓄積容量CSを付加する方法が提案されている。As one of methods for eliminating such inconvenience, conventionally, as shown in FIG. 6, a method of adding a storage capacitor C S in parallel with a liquid crystal cell capacitor C LC has been proposed.
しかし、液晶セル容量CLCの変動の影響を無視し得る
ようにするには、蓄積容量CSの容量を液晶セル容量CLC
の10倍程度,即ち5〜10pFとする必要がある。このよう
な大容量を作成するには大きな面積を必要とし、また、
製造工程が複雑化して製造歩留りが低下するという問題
が生じる。However, in order to make the influence of the fluctuation of the liquid crystal cell capacitance C LC negligible, the capacitance of the storage capacitance C S is set to the liquid crystal cell capacitance C LC.
It should be about 10 times, that is, 5 to 10 pF. Creating such a large capacity requires a large area, and
There is a problem that the manufacturing process is complicated and the manufacturing yield is reduced.
以上述べた如く、従来は液晶層に印加される電圧から
直流成分を完全に除去できなかった。As described above, conventionally, the DC component cannot be completely removed from the voltage applied to the liquid crystal layer.
本発明は、製造工程を複雑化することなく、液晶に印
加する電圧のシフトを無くして、完全な交流駆動を実現
することを目的とする。An object of the present invention is to realize a complete AC drive without complicating the manufacturing process and eliminating the shift of the voltage applied to the liquid crystal.
本発明は、画素駆動用薄膜トランジスタと略同一構成
を有する補償素子を設け、これを上記薄膜トランジスタ
と背中合わせに接続したもので、この補償素子の被制御
端子の一方を上記薄膜トランジスタの被制御端子の一方
と共通に画素電極に接続し、制御電極には、上記薄膜ト
ランジスタの制御電極に印加する走査信号の反転信号を
印加するようにした。The present invention provides a compensating element having substantially the same configuration as a pixel driving thin film transistor, which is connected back to back with the thin film transistor, and one of the controlled terminals of the compensating element is connected to one of the controlled terminals of the thin film transistor. It is commonly connected to the pixel electrodes, and an inverted signal of the scanning signal applied to the control electrode of the thin film transistor is applied to the control electrode.
上記薄膜トランジスタと補償素子のゲート電極には、
大きさが同じで逆極性の走査信号とその反転信号を印加
するので、同じ電荷量を蓄積した2つのゲート容量が、
画素電極に逆向きに接続される。走査信号およびその反
転信号がオフとなると、2つのゲート容量中の電荷が流
出することにより、それぞれ画素電極電位をシフトさせ
るが、その大きさは同じで向きが反対であるため、互い
に相殺し合い、画素電極電位のシフトΔVは0となる。In the thin film transistor and the gate electrode of the compensation element,
Since the scanning signals having the same magnitude and the opposite polarity and the inverted signals thereof are applied, the two gate capacitors that have accumulated the same amount of charge are
It is connected to the pixel electrode in the opposite direction. When the scanning signal and its inversion signal are turned off, the electric charges in the two gate capacitors flow out to shift the pixel electrode potentials respectively, but since the magnitudes are the same and the directions are opposite, they cancel each other out, The pixel electrode potential shift ΔV becomes zero.
この補償は他の画素の影響を受けることなく、各画素
ごとに独立に行なわれるので、完全な補償が可能であ
り、また、共通電位VCは0〔V〕とすれば良く、付加容
量も不要となる。Since this compensation is performed independently for each pixel without being affected by other pixels, complete compensation is possible, and the common potential V C may be set to 0 [V], and the additional capacitance is also set. It becomes unnecessary.
本発明に係る補償素子は、画素駆動用の薄膜トランジ
スタと略同一構成であるので、これを作成するに際して
は、使用するフォトマスクを一部変更するのみでよく、
製造方法そのものは何ら異なるところはないので、製造
工程を複雑化することがない。Since the compensating element according to the present invention has substantially the same structure as the pixel driving thin film transistor, it is only necessary to partially change the photomask to be used when manufacturing the thin film transistor.
Since the manufacturing method itself is not different, it does not complicate the manufacturing process.
以下本発明の一実施例を第1図(a),(b)により
説明する。An embodiment of the present invention will be described below with reference to FIGS. 1 (a) and 1 (b).
同図において、1は薄膜トランジスタ(TFT)、1′
は補償素子、G,S,DはそれぞれTFT1のゲート電極(制御
電極),ソース電極(第1の被制御電極),ドレイン電
極(第2の被制御電極)、G′,S′,D′はそれぞれ補償
素子1′のゲート電極,ソース電極,ドレイン電極、DB
は表示データを供給するデータ信号線、SBは上記ゲート
電極Gに走査信号を供給する走査信号線、SB′は上記走
査信号の反転信号を供給する付加走査線、CLCは液晶セ
ル容量、CGSおよびCGS′はそれぞれTFT1および補償素子
1′のゲート容量、VGは走査信号、G′は走査信号の
反転信号(以下単に反転信号と略記する)である。In the figure, 1 is a thin film transistor (TFT), 1 '
Is a compensating element, G, S, D are the gate electrode (control electrode), source electrode (first controlled electrode), drain electrode (second controlled electrode), G ′, S ′, D ′ of the TFT 1, respectively. Are the gate electrode, source electrode, drain electrode, and DB of the compensating element 1 ', respectively.
Is a data signal line for supplying display data, SB is a scanning signal line for supplying a scanning signal to the gate electrode G, SB 'is an additional scanning line for supplying an inverted signal of the scanning signal, C LC is a liquid crystal cell capacitance, C LC GS and C GS ′ are the gate capacitances of the TFT 1 and the compensation element 1 ′, V G is a scanning signal, and G ′ is an inverted signal of the scanning signal (hereinafter simply referred to as an inverted signal).
TFT1は正の電圧で駆動され、電子アキュムメーション
型TFTとして動作し、補償素子1′はTFT1と同一構造を
有し、ゲート電極G′に負の電圧を掛けて駆動すること
により、ホールアキュムレーション型TFTとして動作す
る。The TFT1 is driven by a positive voltage and operates as an electronic accumulation type TFT, and the compensating element 1'has the same structure as the TFT1, and the negative accumulation voltage is applied to the gate electrode G'to drive the hole accumulation type TFT. Operates as a TFT.
TFT1および補償素子1′のゲート電極G,G′はそれぞ
れ走査信号線SB,付加走査線SB′に、ソース電極S,S′は
いずれも液晶セル容量CLCの一端(画素電極E)に、ド
レイン電極D,D′はいずれもデータ線DBに接続し、液晶
セル容量CLCの他端(対向電極)は共通電位に保つ。The gate electrodes G and G'of the TFT1 and the compensating element 1'are respectively to the scanning signal line SB and the additional scanning line SB ', and the source electrodes S and S'are both to one end (pixel electrode E) of the liquid crystal cell capacitance C LC , The drain electrodes D and D ′ are both connected to the data line DB, and the other end (counter electrode) of the liquid crystal cell capacitance C LC is kept at a common potential.
このように構成した本実施例を駆動するに際しては、
付加走査線SB′に走査信号線SBの電圧と逆極性の電圧を
印加する。When driving the present embodiment configured as described above,
A voltage having the opposite polarity to the voltage of the scanning signal line SB is applied to the additional scanning line SB '.
以下その動作を第2図(a)〜(c)により説明す
る。The operation will be described below with reference to FIGS.
同図は上記構成の液晶セルを駆動した時の、各部の電
位変化を示した。TFT1の動作は、従来と同じで、走査信
号VGが印加された時(選択時)、ソース電圧VS,即ち画
素電極Eの電圧は、表示データVDの電圧まで上昇し、VG
がオフとなった時(非選択時)には、負の電圧シフトΔ
V1を生じる〔同図(a)参照〕。This figure shows the potential change of each part when the liquid crystal cell having the above structure is driven. The operation of the TFT1 is the same as the conventional one, and when the scanning signal V G is applied (when selected), the source voltage V S , that is, the voltage of the pixel electrode E rises to the voltage of the display data V D , and V G
Is turned off (when not selected), negative voltage shift Δ
V 1 is generated [see (a) in the figure].
補償素子1′のゲート電極G′にはTFT1の走査信号VG
の反転信号Gを印加するので、これのソース電圧VS′
は正方向にΔV1′だけシフトする〔同図(b)参照〕。The scanning signal V G of the TFT1 is applied to the gate electrode G'of the compensating element 1 '.
Since an inversion signal G of this is applied, its source voltage V S ′
Shifts in the positive direction by ΔV 1 ′ (see FIG. 7B).
上記ΔV1とΔV1′は式に見るVGの極性が逆となるだ
けでその大きさは等しいので、互いに打ち消し合う。従
って、これらを重ね合わせた波形は同図(c)に示す如
く、電圧シフトは完全に0となる。The above ΔV 1 and ΔV 1 ′ are equal in magnitude only with the opposite polarities of V G seen in the equation, and therefore cancel each other out. Therefore, the waveform obtained by superimposing these is completely zero in voltage shift as shown in FIG.
第1図(c)は第2図(a)〜(c)をまとめた図で
あって、同図に見られるように、本実施例では電圧シフ
トそのものを0とすることができるので、直流成分は除
去され、完全な交流駆動が実現し、良好な表示が安定し
て得られる。FIG. 1 (c) is a diagram summarizing FIGS. 2 (a) to 2 (c). As can be seen in FIG. 1, the voltage shift itself can be set to 0 in the present embodiment. The components are removed, complete AC driving is realized, and good display is stably obtained.
次ぎに、本発明の変形例を第3図により説明する。 Next, a modified example of the present invention will be described with reference to FIG.
上記一実施例では、補償素子1′のドレイン電極D′
をデータ線DBに接続したが、ゲート容量CGS′に蓄積さ
れる電荷量は、ソース電圧VS′とゲート電圧Gにより
決定されるので、補償素子1′のドレイン電極D′は強
いて接続しておく必要はない。In the above embodiment, the drain electrode D'of the compensating element 1'is
Is connected to the data line DB, the amount of charge accumulated in the gate capacitance C GS ′ is determined by the source voltage V S ′ and the gate voltage G, so the drain electrode D ′ of the compensating element 1 ′ is strongly connected. There is no need to keep it.
そこで本変形例では、補償素子1′のゲート電極G′
とソース電極S′のみを上記一実施例と同様に接続し、
ドレイン電極D′は遊ばせておく。Therefore, in this modification, the gate electrode G'of the compensating element 1'is
And only the source electrode S ′ are connected in the same manner as in the above-mentioned embodiment,
The drain electrode D'is left free.
またこの場合、TFT動作の必要はなく、容量として動
作すればよいので、ソース・ドレインのブロッキング層
はTFT1と同じ材料でよい。Further, in this case, since it is not necessary to perform the TFT operation and it may operate as a capacitor, the blocking layer for the source / drain may be made of the same material as the TFT1.
以上のように本実施例は、製造工程は従来と全く同じ
ものとなる。As described above, the manufacturing process of this embodiment is exactly the same as the conventional one.
以上説明した如く本発明によれば、電圧シフトそのも
のを無くすことができるので、液晶を完全に交流駆動す
ることができ、良好な表示が安定して得られる。As described above, according to the present invention, since the voltage shift itself can be eliminated, the liquid crystal can be completely AC-driven and a good display can be stably obtained.
第1図(a),(b)は本発明一実施例の説明図、 第2図は上記一実施例の駆動波形図、 第3図は本発明の変形例の等価回路図、 第4図は従来の薄膜トランジスタマトリクス1画素分の
等価回路図、 第5図は従来の薄膜トランジスタマトリクスの駆動波形
図、 第6図は従来の蓄積容量を付加した薄膜トランジスタマ
トリクス1画素分の等価回路図である。 図において、 1はTFT(薄膜トランジスタ)、 1′は補償素子、 G,G′はゲート電極(制御電極)、 S,S′はソース電極(第1の被制御電極)、 D,D′はドレイン電極(第2の被制御電極)、 DBはデータ信号線、 SBは走査信号線、SB′は付加走査線、 VGは走査信号、Gは走査信号の反転信号、 VS,VS′はソース電圧、 VDは表示データ、 VCは共通電位、 CLCは液晶セル容量、 CGS,CGS′はゲート容量を示す。1 (a) and 1 (b) are explanatory views of an embodiment of the present invention, FIG. 2 is a drive waveform diagram of the above embodiment, FIG. 3 is an equivalent circuit diagram of a modified example of the present invention, and FIG. Is an equivalent circuit diagram of one pixel of a conventional thin film transistor matrix, FIG. 5 is a drive waveform diagram of a conventional thin film transistor matrix, and FIG. 6 is an equivalent circuit diagram of one pixel of a thin film transistor matrix to which a conventional storage capacitor is added. In the figure, 1 is a TFT (thin film transistor), 1'is a compensating element, G and G'are gate electrodes (control electrodes), S and S'are source electrodes (first controlled electrodes), and D and D'are drains. Electrode (second controlled electrode), DB is a data signal line, SB is a scanning signal line, SB 'is an additional scanning line, V G is a scanning signal, G is an inversion signal of the scanning signal, V S and V S ′ are Source voltage, V D is display data, V C is common potential, C LC is liquid crystal cell capacitance, and C GS and C GS ′ are gate capacitances.
フロントページの続き (72)発明者 井上 淳 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 長廣 紀雄 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内(72) Inventor Jun Inoue 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Norio Nagahiro, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited
Claims (1)
(E)と該画素電極に対応付けられた複数個の薄膜トラ
ンジスタ(1)とをマトリクス状に配列し、該薄膜トラ
ンジスタ(1)の第1の被制御電極(S)を前記画素電
極(E)、第2の被制御電極(D)をデータ信号線(D
B)、制御電極(G)を走査信号線(SB)にそれぞれ接
続し、且つ他方の絶縁性基板上に前記画素電極と相対す
る共通電位に接続された対向電極を配設した薄膜トラン
ジスタマトリクスの構成において、 前記一方の絶縁性基板上にさらに薄膜トランジスタ
(1)と同一構成で且つ同一接続関係を有する補償素子
(1′)を該トランジスタマトリクスに対応して設ける
とともに、走査信号線(SB)に隣接して走査線(SB′)
を付設し、該付加走査線(SB′)に前記補償素子
(1′)の制御電極(G′)を接続し、且つ前記走査信
号線(SB)に印加する走査信号(VG)の反転信号
(G)を印加するようにしたことを特徴とする薄膜ト
ランジスタマトリクス。1. A plurality of pixel electrodes (E) and a plurality of thin film transistors (1) associated with the pixel electrodes are arranged in a matrix on one insulating substrate, and the thin film transistors (1) are arranged. Of the first controlled electrode (S) of the pixel electrode (E) and the second controlled electrode (D) of the data signal line (D).
B), a structure of a thin film transistor matrix in which a control electrode (G) is connected to a scanning signal line (SB) and an opposite electrode connected to a common potential facing the pixel electrode is provided on the other insulating substrate. In the above-mentioned one insulative substrate, a compensating element (1 ′) having the same configuration and the same connection relationship as the thin film transistor (1) is further provided corresponding to the transistor matrix and adjacent to the scanning signal line (SB). Then scan line (SB ')
Annexed to, and connect the additional scan lines (SB ') the compensating element (1') the control electrode of the (G '), and the inverse of the scanning signal applied to the scanning signal lines (SB) (V G) A thin film transistor matrix, wherein a signal ( G ) is applied.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3697989A JP2503266B2 (en) | 1989-02-15 | 1989-02-15 | Thin film transistor matrix |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3697989A JP2503266B2 (en) | 1989-02-15 | 1989-02-15 | Thin film transistor matrix |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02214819A JPH02214819A (en) | 1990-08-27 |
JP2503266B2 true JP2503266B2 (en) | 1996-06-05 |
Family
ID=12484872
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3697989A Expired - Lifetime JP2503266B2 (en) | 1989-02-15 | 1989-02-15 | Thin film transistor matrix |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2503266B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7545210B2 (en) | 2016-11-04 | 2024-09-04 | 武田薬品工業株式会社 | Adeno-associated virus preparations |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0456453B1 (en) * | 1990-05-07 | 1995-09-06 | Fujitsu Limited | High quality active matrix-type display device |
US6893906B2 (en) | 1990-11-26 | 2005-05-17 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
TW209895B (en) | 1990-11-26 | 1993-07-21 | Semiconductor Energy Res Co Ltd | |
KR970009405B1 (en) * | 1991-10-05 | 1997-06-13 | Fujitsu Ltd | Active matrix type display device |
JP2001249319A (en) * | 2000-03-02 | 2001-09-14 | Hitachi Ltd | Liquid crystal display device |
JP3906090B2 (en) | 2002-02-05 | 2007-04-18 | シャープ株式会社 | Liquid crystal display |
CN103454823B (en) * | 2013-09-09 | 2016-01-06 | 深圳市华星光电技术有限公司 | A kind of array base palte and display panels |
-
1989
- 1989-02-15 JP JP3697989A patent/JP2503266B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7545210B2 (en) | 2016-11-04 | 2024-09-04 | 武田薬品工業株式会社 | Adeno-associated virus preparations |
Also Published As
Publication number | Publication date |
---|---|
JPH02214819A (en) | 1990-08-27 |
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