JP2500775B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit, and more particularly to an input circuit of a semiconductor integrated circuit composed of CMOS.

[0002]

2. Description of the Related Art In a CMOS inverter, an input voltage V _IN
If is + 5V, n-type MOS transistor is turned on and p-type MO
The S transistor is turned off and the output voltage becomes about 0V. If the output terminal has a load capacitance CL, the charge is discharged (see FIG. 4A). On the other hand, if the input voltage V _IN is 0V, n-type MO
The S transistor is turned off, the p-type MOS transistor is turned on, and the output voltage becomes about 5V. If the output terminal has a load capacitance CL, it is charged with electric charge (see FIG. 4B).

By the way, the input voltage of the CMOS inverter
When V _IN is an intermediate voltage between the power supply voltage (+ 5V) and the ground voltage (eg + 2.5V), n-type MOS transistor and p-type MO
The S transistors are turned on at the same time, and a through current flows from the power source V _DD to the ground V _SS (see FIG. 4C). Generally, when the input voltage is about 1/2 of the power supply voltage V _DD , the through current becomes maximum.

A conventional input / output circuit (Japanese Patent Laid-Open No. 61-33039) having a mechanism for suppressing this shoot-through current will be described with reference to FIG.

As shown in FIG. 2, the conventional input / output circuit is
Input / output terminal 1 has a gate input and an input buffer including a p-type MOS transistor 21 and a first n-type MOS transistor 22, and a read / write signal 18 has a gate input and is inserted between the first n-type MOS transistor 22 and GND. The second n-type MOS transistor 23 is provided.

The output of the input buffer is input to the first transfer gate 13 which is controlled by the read / write signal 18, and the output thereof is input to the second tri-state buffer 24 which is controlled by the control signal 19 to the internal bus. It is output to 20.

The input / output circuit of the conventional example is the internal bus 2
First latch 1 that receives data from 0 and holds it
6, and a first tri-state buffer 15 that receives the output of the first latch 16 and outputs it to the input / output terminal 1.
Further, the first tri-state buffer 15 is provided with the first inverter 10 for inputting the read / write signal 18 and controlling the second transfer gate 14, and the first tri-state buffer 15 receives data under the control of the output of the first inverter 10. Output to output terminal 1.

The output of the latch 16 is passed through the second transfer gate 14 to the second tri-state buffer 24.
, And becomes a data signal to the internal bus when the read / write signal 18 is at a high level.

Here, the read / write signal 18 is a signal for switching the input / output of the input / output terminal 1 (for example, input at high level, output at low level).

When the control signal 19 is at high level, the first
Of the transfer gate 13 or the second transfer gate 14 of the second tri-state buffer 2
It is a signal which is output to the internal bus 20 through 4 and makes the second tri-state buffer 24 high impedance when it is at a low level.

When data is fetched from the input / output terminal 1, the read / write signal 18 is set to a high level to make the output of the first tri-state buffer 15 high impedance and prevent the data output of the first latch 16. At the same time, since the first transfer gate 13 is turned on and the second transfer gate 14 is turned off, the captured data is input to the second tri-state buffer 24 through the input buffer and the first transfer gate 13. Internal bus 20 when control signal 19 goes high
Output to

When outputting data to the input / output terminal 1,
By setting the read / write signal 18 to a low level, the second n-type MOS transistor 23 is turned off, the first transfer gate 13 is turned off, the second transfer gate 14 is turned on, and the first tristate buffer 15 is active. Therefore, the value held in the first latch 16 is output to the input / output terminal 1.

At this time, the input / output terminal 1 is affected by an external circuit or output data and the p-type MOS transistor 2
Even when both the first and first n-type MOS transistors 22 are turned on, the gate input of the second n-type transistor 23 (that is, the read / write signal 18) is at the low level, and thus the p-type MOS transistor 21, first n
A through current does not flow between the power supply and the ground through the type MOS transistor 22 and the second n-type MOS transistor 23.

As described above, according to the conventional example, in the input circuit having the input / output terminals, the input buffer is activated only during the input period, so that the through current can be prevented from flowing through the input buffer.

[0015]

In the conventional input / output circuit having a common input / output terminal, the input buffer becomes inactive only during the output period, and the output signal or the external circuit connected to the input / output terminal affects the shoot-through current. However, since there is only one input buffer having a specific threshold value, an input signal of a voltage level at which both the p-type and n-type transistors forming the input buffer are conductive during the input period is input. In that case, there is a problem that a through current flows.

The generation of shoot-through current in the input circuit will be described in detail with reference to FIG.

[0017] FIG. 3 (A) illustrates the input level of a typical CMOS interface in correspondence with the power supply voltage V _{D D.} In a typical CMOS interface, VI
H (high level input voltage) is 0.7 × _VDD , VIL (low level input voltage) is 0.3 × _VDD , and the threshold is 0.5 × _VDD . The power supply voltage V _DD is set to 5V ± 10%.

Further, in FIG. 3B, VIH = 2.2V, VIL = 0.
It shows the input level of a typical TTL interface with 8V, threshold = 1.4V.

In the conventional example, the input buffer is a CMO.
When only the S interface is satisfied, when an input signal satisfying the TTL interface is input to this input buffer, (VIH of the TTL interface) of FIG. 3B is C of FIG. 3A, that is, the CMOS input buffer. Since it is close to the threshold value of, the above-mentioned through current will flow.

Further, in the case where the input buffer of the conventional example satisfies only the TTL interface, when an input signal satisfying the CMOS interface is input to this input buffer, B (CMOS interface of FIG. 3A). VIL) is close to the threshold of the TTL input buffer shown in FIG. 3B, so that a through current flows.

Therefore, the present invention solves the above problems and, in an input circuit of a semiconductor integrated circuit composed of CMOS, an input circuit in which a through current does not flow even if the input level changes to the CMOS or TTL level. The purpose is to provide.

[0022]

In order to solve the above-mentioned problems, the present invention enables a plurality of input buffer circuits connected to input terminals and having different thresholds, and one of the plurality of input buffer circuits being effective. The input level selection signal for selectively inputting the input signal from the input terminal to the one input buffer circuit and the transmission of the output signal of the input buffer circuit invalidated by the input level selection signal are suppressed and enabled. An input signal transmission circuit for transmitting the output signal of the input buffer circuit, and an input signal output means for inputting the output of the input signal transmission circuit and outputting the input signal to an internal circuit by a read strobe signal. Provided is a semiconductor integrated circuit.

In the semiconductor integrated circuit according to the present invention, two types of input voltage detection circuits having different thresholds are provided.
Provided is a semiconductor integrated circuit including a TTL level input buffer and a CMOS level input buffer.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

As shown in FIG. 1, the input circuit of this embodiment has a NAND gate 8 having the input buffer selection signal 2 and the input / output terminal 1 as input, and a second inverter having the output of the NAND gate 8 as input. 11 and the second inverter 1
A first transfer gate 13 which receives the output of 1 as an input and is controlled by the input buffer selection signal 2; a first inverter 10 which receives the input buffer selection signal 2; an input buffer selection signal 2 and an input / output terminal 1. A NOR gate 9 that receives the input, a third inverter 12 that receives the output of the NOR gate 9, and a second inverter that receives the output of the third inverter 12 and that is controlled by the output of the first inverter 10.
Of the first transfer gate 13 and the outputs of the first transfer gate 13 and the second transfer gate 14 of FIG.
It comprises a second latch 17 for outputting

Further, the present embodiment includes an output circuit, which receives the output data signal 7 as an input and which has a first latch 16 controlled by the first strobe signal 4 and a first latch 16.
First, which receives the output of the latch 16 of the input terminal and outputs the data to the input / output terminal 1 by the output enable signal 3
3 tri-state buffer 15.

In this embodiment, the NAND gate 8 and the second inverter 11 have CMOS level (high level input voltage: VIH = 0.7 × V _DD , low level input voltage: VIL = 0.3 × V _DD ,
It is a CMOS input buffer satisfying V _DD = 4.5 to 5.5 V), and the NOR gate 9 and the third inverter 12 satisfy TTL level (VIH = 2.2 V, VIL = 0.8 V, V _DD = 4.5 to 5.5 V). TTL input buffer.

Since the TTL level input buffer is required to have a large beta ratio, the CMOS NOR
The gate is used as a TTL level input buffer.

The input buffer selection signal (also called "input level selection signal") 2 is a signal for selecting either the CMOS input buffer (8, 11) or the TTL input buffer (9, 12). CM when signal 2 is high
When OS input buffer is selected and low level, TTL
Input buffer is selected.

Further, the output enable signal 3 is
At the high level, the output of the first latch 16 is output to the input / output terminal 1 through the first tri-state buffer 15.
At the low level, the first tri-state buffer 15
Is high impedance.

When the first strobe signal 4 is at the high level or at the rising edge, the output data signal 7 is fetched in the first latch 16 and output to the first tri-state buffer 15, and when it is at the low level, the first strobe signal 4 is output. The latch 16
Hold the output of.

When the second strobe signal 5 is at the high level or at the rising edge, the output of the first transfer gate 13 or the second transfer gate 14 is taken into the second latch 17 and the input data signal 6 is input. Is output, and the output of the second latch 17 is held at the low level.

When a TTL level signal is input from the input / output terminal 1, the input buffer selection signal 2 is set to a low level to turn off the first transfer gate 13 and turn on the second transfer gate 14. The input TTL level signal is input to the second latch 17 through the TTL input buffer composed of the NOR gate 9 and the third inverter 12, and when the second strobe signal 5 becomes high level, the input data is input. It is captured as signal 6.

When a CMOS level signal is input from the input / output terminal 1, the input buffer selection signal 2 is set to a high level so that the first transfer gate 1
Since 3 is turned on and the second transfer gate 14 is turned off, the input CMOS level signal is input to the second latch 17 through the CMOS input buffer including the NAND gate 8 and the second inverter 11. , Is taken in as the input data signal 6 when the second strobe signal 5 becomes high level.

In any case, when the input signal is taken in, the output enable signal 3 is set to the low level and the first tri-state buffer 15 is set to the high impedance, so that the value held by the first latch 16 is obtained. It is possible to prevent collision with input data.

On the other hand, when outputting data to the input / output terminal 1, the first tri-state buffer 15 becomes conductive by setting the output enable signal 3 to a high level, so that the first strobe signal is generated. 4, the output data signal 7 is output to the input / output terminal 1.

In this embodiment, when outputting data, C
Output data is input to the MOS input buffer and the TTL input buffer, but two are input to the first stage of the input buffer.
Since an input NAND gate and a two-input NOR gate are used, and the input terminal of the gate is fixed to the high level or the low level by the input buffer selection signal 2, no through current flows between the power supply and the ground. However, since the output data is transmitted to the second latch 17, the second strobe signal 5 needs to be at a low level.

In the present embodiment, the CMOS input buffer or the TTL input buffer is selected by the user in advance depending on the output level of the device connected to the input circuit. However, when the output of a device whose output signal dynamically changes between the TTL level and the CMOS level is input, the input buffer selection signal 2 changes the input level by, for example, a comparator. It can also be detected and controlled.

Further, the present invention is not limited to the configuration of the two buffers shown in the embodiment, and an input signal of an arbitrary input level is adapted to correspond to the input level according to the configuration of the present invention. By adding logic for controlling the input buffer selection signal, it is possible to suppress shoot-through current in any case.

[0041]

As described above, according to the present invention, there are provided a plurality of input buffers connected to the input terminals and having different thresholds, and an input level selection signal for validating the input signals to the plurality of input buffers. With the provision, there is an advantage that the through current can be prevented even if the input level changes to the CMOS or TTL level.

Further, according to the present invention, even if an input signal having an arbitrary input level is added with a logic for controlling the input level selection signal so as to correspond to the input level, the shoot-through current can be obtained in any case. The effect is that it can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional input / output circuit.

FIG. 3A is a diagram showing an input level of a CMOS interface. (B) It is a figure which shows the input level of a TTL interface.

FIG. 4 is an explanatory diagram of the operation of the CMOS inverter. (A) Shows the operation when the input voltage is 5V. (B) The operation at 0 V input voltage is shown. (C) Shows the occurrence of through current.

[Explanation of symbols]

 1 Input / Output Terminal 2 Input Buffer Select Signal 3 Output Enable Signal 4 First Strobe Signal 5 Second Strobe Signal 6 Input Data Signal 7 Output Data Signal 8 NAND Gate 9 NOR Gate 10 First Inverter 11 Second Inverter 12 Third Inverter 13 First Transfer Gate 14 Second Transfer Gate 15 First Tri-State Buffer 16 First Latch 17 Second Latch 18 Read / Write Signal 19 Control Signal 20 Internal Bus 21 p-type MOS Transistor 22 First n-type MOS transistor 23 Second n-type MOS transistor 24 Second tri-state buffer

Claims (3)

(57) [Claims] 1. A plurality of input buffer circuits connected to an input terminal and having different thresholds, and one of the plurality of input buffer circuits is enabled, and an input signal from the input terminal is input to the one input buffer circuit. Transmission of the input level selection signal selectively input to the input buffer circuit and the transmission of the output signal of the input buffer circuit invalidated by the input level selection signal, and transmission of the output signal of the input buffer circuit that is validated. A semiconductor integrated circuit comprising: an input signal transmission circuit; and an input signal output means for inputting an output of the input signal transmission circuit and outputting the input signal to an internal circuit by a read strobe signal. 2. The semiconductor integrated circuit according to claim 1, wherein the plurality of input buffer circuits include a TTL level input buffer and a CMOS level input buffer. 3. A latch circuit having a common input / output terminal for latching an output signal from an internal circuit, and the output signal of the latch circuit being input to the common input / output terminal according to an output enable signal. 3. The semiconductor integrated circuit according to claim 1, further comprising an output buffer circuit for transmitting.