JP2025110693A - Power supply circuit and drive circuit - Google Patents

Abstract

To provide a power supply circuit capable of preventing the potential at an output terminal from rising to exceed the withstand voltage of a load as an electric current flows to the output terminal from outside when an input voltage rises.SOLUTION: A power supply circuit comprises a voltage regulator which has a first transistor for output control connected between a voltage input terminal and a voltage output terminal, and an amplifier. A diode for protection is so provided between the voltage output terminal and the gate terminal of the first transistor as to have its cathode terminal connected to the gate terminal. A second transistor for pull-down is provided between the gate terminal of the first transistor and a reference potential point, and a third transistor in which an external control signal is input is provided between the gate terminal of the second transistor and the reference potential point. Then a voltage generated by a resistance element connected in series between the voltage input terminal and reference potential point and a reversely-connected diode is applied to the gate terminal of the second transistor.SELECTED DRAWING: Figure 1

Description

The present invention relates to technology that is effective when used in power supply circuits and drive circuits.

Power supply circuits are used to supply an appropriate power supply voltage to loads such as ICs (semiconductor integrated circuits) and circuit blocks within ICs. Various types of power supply circuits are known, such as linear regulators and switching regulators. Patent Document 1, for example, describes an invention relating to a power supply circuit comprising a linear regulator.
Furthermore, Patent Document 2 describes an invention for avoiding problems that occur in a load that uses the output voltage of a linear power supply circuit due to a steep rise in the input voltage in the linear power supply circuit.

Japanese Patent Application Laid-Open No. 2022-153719 Japanese Patent Application Laid-Open No. 2023-115986

Some power supply circuits use a series regulator to supply power to a drive circuit that drives a load such as a motor. Systems using such power supply circuits are provided with an overvoltage protection circuit to prevent overvoltage from being supplied to the load. In general, the purpose of an overvoltage protection circuit is to prevent overvoltage from being applied to the load during normal operation after power-on.
On the other hand, the present inventor has found that in a power supply circuit including a series regulator REG configured to be operated by an enable signal EN from a control device as shown in FIG. 4(A), when the input voltage rises, the output voltage VRG may rise and exceed the withstand voltage of the element.

Specifically, the regulator REG shown in FIG. 4A is provided with a circuit for turning off the gate terminal of the output control MOS transistor NM0 by lowering it to a low level while the enable signal EN is negated.
This circuit includes a pull-down MOS transistor NM1 connected between the gate terminal of transistor NM0 and ground, and an inverter INV as a logic circuit that generates a gate control voltage for transistor NM1. The inverter INV receives an enable signal EN and controls the gate terminal of the pull-down transistor NM1 with an inverted signal. The transistor NM0 is an N-channel type, and a voltage protection diode D1 is provided between the gate terminal and output terminal OUT so that it is in the forward direction when viewed from the output terminal OUT side.

4A starts operating when the input voltage VDD and the operating voltage VDD of the inverter INV are supplied. Here, the voltage VDD is a voltage generated according to the input voltage VDD, and just before the voltage VDD rises, the inverter INV outputs a high-level signal to the gate terminal of the pull-down transistor NM1 to turn NM1 on and turn off the output control transistor NM0.
However, because the logic circuit (inverter INV) operates on voltage DVDD, it can only output a low level before timing t2 when voltage DVDD rises, as shown in Figure 5. Therefore, the pull-down transistor NM1 is turned off, and the gate terminal of the output control transistor NM0 becomes high impedance.

Also, because transistor NM1 is in the off state, NM1 appears to be a high-resistance element. As a result, if current flows into regulator REG from output terminal OUT for some reason, as shown in Figure 4(B), the current flows through protective diode D1 to the high-resistance element (NM1), causing the gate potential VG0 of output control transistor NM0 to rise. Here, because the potential of the output terminal OUT is determined by VG0 - (Vth + Veff), if the gate potential VG0 of NM0 rises, the potential of the output terminal OUT also rises, posing the risk that the output voltage VRG may exceed the withstand voltage of the element.

The above-mentioned problem is specific to the case where the output control MOS transistor NM0 is an N-channel type. Furthermore, the phenomenon of current flowing from the output terminal OUT into the regulator REG can occur as a backflow from the pre-driver when the regulator is used as a power supply circuit that supplies power supply voltage to a pre-driver that constitutes a motor drive system.
The present invention has been made in light of the above-mentioned background, and its object is to provide a power supply circuit and a drive circuit using the same that can prevent the potential of the output terminal from rising and exceeding the breakdown voltage of the element due to current flowing into the output terminal from the outside when the input voltage rises.

In order to achieve the above object, a power supply circuit according to the present invention comprises:
a voltage regulator having a first transistor for output control connected between a voltage input terminal and a voltage output terminal and an amplifier for controlling the first transistor, for converting a DC voltage input to the voltage input terminal into a predetermined DC voltage and outputting the DC voltage;
the first transistor is an N-channel insulated gate field effect transistor,
a protection diode is provided between the voltage output terminal and the gate terminal of the first transistor such that a cathode terminal of the diode is connected to the gate terminal;
a second transistor for pull-down is provided between the gate terminal of the first transistor and a reference potential point;
a third transistor having a gate terminal to which an external control signal is input is provided between a gate terminal of the second transistor and a reference potential point;
A voltage generated by a first passive element and a second passive element connected in series between the voltage input terminal and a reference potential point is applied to the gate terminal of the second transistor.

With a power supply circuit having the above configuration, when the voltage input to the voltage input terminal rises, the first passive element and the second passive element turn on the second pull-down transistor, lowering its resistance. Therefore, when current flows into the output terminal from the outside, the current flows through the protective diode to the second pull-down transistor, which is in a low-resistance state. As a result, it is possible to prevent the potential of the output terminal from rising due to current flowing into the output terminal from the outside and exceeding the breakdown voltage of the element.

The power supply circuit of the present invention has the advantage of preventing current from flowing into the output terminal from the outside when the input voltage rises, causing the potential at the output terminal to rise and exceed the breakdown voltage of the element.

1A is a circuit diagram showing an embodiment of a power supply circuit according to the present invention, and FIG. 1B is a system diagram showing an application example of the power supply circuit according to the embodiment. 4 is a time chart showing operation timings of the power supply circuit according to the embodiment; 1 is a circuit diagram showing an example of the configuration of a motor drive IC to which a power supply circuit according to the present invention is applied and a motor drive system using the same; 1A is a diagram showing an example of the configuration of a power supply circuit that was studied prior to the present invention, and FIG. 1B is a diagram showing the path of a current flowing in from an output terminal. 5 is a time chart showing the operation timing of the power supply circuit of FIG. 4;

Preferred embodiments of the present invention will now be described with reference to the accompanying drawings.
FIG. 1 is a circuit diagram of an embodiment of a power supply circuit according to the present invention, and FIG. 2 shows its operation timing.
As shown in FIG. 1A, the power supply circuit of this embodiment is configured with a series regulator (hereinafter referred to as regulator) 10.

The regulator 10 includes an output control transistor NM0, which is an N-channel MOSFET (insulated gate field effect transistor), connected between a voltage input terminal IN to which a DC voltage VDD supplied from a battery or the like is input, and a voltage output terminal OUT. The regulator 10 also includes an error amplifier 11 that generates a gate control voltage for the transistor NM0, and a voltage divider circuit 12 consisting of series resistors R1 and R2 connected between the source terminal of the transistor NM0 and ground GND, with the source terminal of the transistor NM0 connected to the output terminal OUT.

The voltage divided by the voltage divider circuit 12 is fed back to the non-inverting input terminal of the error amplifier 11. A reference voltage VBG generated by a circuit such as a BGR (bandgap reference) circuit is input to the inverting input terminal of the error amplifier 11, and a voltage corresponding to the potential difference between the reference voltage VBG and the feedback voltage VFB is applied to the gate terminal of transistor NM0. As a result, the error amplifier 11 controls transistor NM0 to match the feedback voltage VFB with the reference voltage VBG. The voltage VRG generated at the source terminal of transistor NM0 is then output from the output terminal OUT.

A Zener diode D1 for voltage protection is provided between the gate terminal of the transistor NM0 and the output terminal OUT.
A pull-down N-channel MOS transistor NM1 is connected between the gate terminal of the transistor NM0 and the ground GND, and an N-channel MOS transistor NM2 is connected between the gate terminal of this transistor NM1 and the ground GND.

Furthermore, resistor R3 and reverse diode D2 are connected in series between the voltage input terminal IN and ground GND, and the potential at the connection node between resistor R3 and diode D2 is applied to the gate terminal of transistor NM1. Diode D2 is preferably a Zener diode. The resistance value of resistor R3 is preferably set so that when a reverse current flows through diode D2, the reverse voltage of D2 is higher than the threshold voltage of transistor NM1.

In the regulator 10 of Figure 1(A), when the enable signal EN is set to high level and transistor NM2 is turned on, unnecessary current flows through resistor R3 and transistor NM2. Therefore, even if the resistance of R3 is set to a relatively large value to suppress the current flowing through R3 and NM2 when NM2 is on, by using diode D2 as a passive element in series with resistor R3 as described above, it is possible to generate a voltage at the cathode terminal of D2 that is sufficient to turn on pull-down transistor NM1 when the input voltage rises.

The power supply voltage VBIAS of the error amplifier 11 may be the DC voltage VDD at the input terminal IN, or it may be a voltage obtained by boosting the output voltage VRG using a charge pump circuit or the like. In this variant, after the DC voltage VDD is raised to start the power supply circuit, the power supply voltage VBIAS can be switched once the voltage obtained by boosting the output voltage VRG using the charge pump circuit reaches a predetermined level. This allows the error amplifier 11 to operate in the saturation region, preventing the output voltage VRG from dropping. To achieve the above-mentioned VBIAS switching function, it is advisable to provide, for example, a circuit such as a multiplexer that switches between the DC voltage VDD and the boosted voltage of VRG, and a comparator that detects when the boosted voltage has reached a predetermined level.

Furthermore, as shown in Figure 1(B), if a charge pump circuit 20 is provided downstream of the regulator 10, in a system equipped with a drive circuit such as a motor drive system, the output voltage VRG of the regulator 10 can be used as the power supply for the low-side pre-driver, and the voltage boosted by the downstream charge pump circuit 20 can be used as the power supply for the high-side pre-driver.

When the output voltage of regulator 10 is configured to be supplied as a power supply voltage for a pre-driver of a motor drive system, backflow from the pre-driver may occur. However, in the regulator of this embodiment, even if such a current flows into the output terminal OUT, transistor NM1 is turned on, thereby preventing the output voltage from rising significantly.
Furthermore, when a power supply circuit consisting of a regulator and a charge pump circuit is used in the motor drive system described above, the charge pump circuit can be shared as both a circuit that generates a voltage that causes error amplifier 11 to operate in the saturation region and a circuit that generates power for the high-side driver.

Next, the operation of regulator 10 shown in FIG. 1 when the input voltage rises will be described with reference to the time chart shown in FIG.
As shown in Figure 2, when the input DC voltage VDD begins to rise at timing t1, the pull-down transistor NM1 is off at this point, and the gate terminal of the output control transistor NM0 is at high impedance. Therefore, the gate voltage VG0 of the output transistor NM0 rises following VDD via the gate capacitance of NM0. Furthermore, as VDD rises, the gate voltage VG1 of the pull-down transistor NM1 also rises following VDD via resistor R3. At this time, the output voltage VRG also rises following VDD.

When the potential at the connection node between resistor R3 and diode D2 exceeds the reverse voltage of diode D2, a reverse current flows through diode D2, maintaining a nearly constant potential. This potential is applied to the gate terminal of transistor NM1, turning NM1 on and causing the gate voltage VG0 of output transistor NM0 to fall to ground potential (timing t2). This turns off output control transistor NM0, causing the output voltage VRG to fall.

In this state, if for some reason current flows from the output terminal OUT into the regulator REG and flows through the protective diode D1 to the pull-down transistor NM1, NM1 will be turned on and its resistance will be reduced, so the gate potential VG0 of the output transistor NM0 will not rise significantly. This prevents the potential at the output terminal OUT from rising and causing the output voltage VRG to exceed the breakdown voltage of the element.

Furthermore, at timing t3, when the external enable signal EN changes from low to high, transistor NM2 turns on, the gate voltage of pull-down transistor NM1 drops to ground potential, and NM1 turns off. As a result, the gate terminal of output control transistor NM0 becomes controlled by the output voltage of error amplifier 11, and the output voltage VRG rises.

Next, with reference to FIG. 3, a case will be described in which the power supply circuit of the present invention is applied to a power supply circuit built into a drive IC that constitutes a motor drive system, as an example.
3 has a function of converting DC voltage VDD supplied from a DC power supply into AC voltage to be supplied to a motor 200 serving as a load, and includes a high-side transistor M1 that feeds current into the motor 200, a low-side transistor M2 that draws current from the motor 200, and a drive IC 100 that drives these transistors M1 and M2. The load 200 is not limited to a motor.

The driving IC 100 is a pre-driver that drives transistors M1 and M2 externally attached to the IC. Although there is no particular limitation, N-channel field effect transistors (FETs) are used for the transistors M1 and M2 here.
The driving IC 100 also incorporates a power supply circuit 101 that generates a voltage for operating the driving circuit, and the power supply circuit of the above embodiment (FIG. 1) is used as the power supply circuit 101 .

The driving IC 100 in FIG. 3 switches (on or off) the transistors M1 and M2 by driving the transistors M1 and M2 in accordance with signals (clock CLK, high-side command signal HIN, and low-side command signal LIN) supplied from a controller not shown.
The high-side command signal HIN and the low-side command signal LIN change in synchronization with the clock CLK. In accordance with the high-side command signal HIN and the low-side command signal LIN, the driving IC 100 alternately turns on the transistors M1 and M2 with a dead time in between to turn off the transistors M1 and M2.

The driving IC 100 also includes a control circuit 130, a high-side source current source 111, a high-side sink current source 112, a low-side source current source 121, and a low-side sink current source 122. The driving IC 100 also includes a high-side driving terminal GH, an intermediate terminal SH, a low-side driving terminal GL, and a ground terminal PGND.

The control circuit 130 controls the source current source 111, which turns on transistor M1, and the sink current source 112, which turns off transistor M1. The control circuit 130 also controls the source current source 121, which turns on transistor M2, and the sink current source 122, which turns off transistor M2. To achieve these functions, the control circuit 130 includes a logic circuit 131, a high-side control circuit 132, and a low-side control circuit 133.

The logic circuit 131 generates a source control drive command HHIN and a sink control drive command HLIN based on the high-side command signal HIN and the low-side command signal LIN. The logic circuit 131 also generates a source control drive command LHIN and a sink control drive command LLIN based on the high-side command signal HIN and the low-side command signal LIN. The enable signal EN input to the regulator 10 in FIG. 1 is generated by the logic circuit 131. The logic circuit 131 may be located outside the control circuit 130 or even outside the drive IC 100.

The high-side control circuit 132 controls the source current generated by the high-side source current source 111 in accordance with the source control drive command HHIN. The high-side control circuit 132 also controls the sink current generated by the high-side sink current source 112 in accordance with the sink control drive command HLIN. Furthermore, the high-side control circuit 132 alternately turns on the output transistors of current sources 111 and 112, with dead times in between to turn off the output transistors of current sources 111 and 112, in accordance with the drive commands HHIN and HLIN.

The low-side control circuit 133 controls the source current generated by the low-side source current source 121 in accordance with the source control drive command LHIN. The low-side control circuit 133 also controls the sink current generated by the low-side sink current source 122 in accordance with the sink control drive command LLIN. Furthermore, the low-side control circuit 133 alternately turns on the output transistors of current sources 121 and 122, with dead times in between to turn off the output transistors of current sources 121 and 122, in accordance with the drive commands LHIN and LLIN.

The source current source 111 is an output transistor formed of a P-channel MOSFET, and generates a source current to be fed into the gate of the transistor M1. The source current source 111 is connected between the drive terminal GH connected to the gate of the transistor M1 and the power supply node of the high-side power supply voltage VCP.
The power supply voltage VCP is equal to the sum of the DC voltage VDD and the low-side power supply voltage (regulator voltage VRG). The power supply voltage VCP is generated by the charge pump circuit 20 in the power supply circuit 101, for example, using the DC voltage VDD and the regulator voltage VRG.

The driving IC 100 charges the gate of the transistor M1 and turns on the transistor M1 by injecting a source current from the PMOS output transistor of the source current source 111 to the driving terminal GH. The driving IC 100 also draws a sink current from the driving terminal GH into the NMOS output transistor of the sink current source 112, thereby discharging the gate of the transistor M1 and turning off the transistor M1.
Similarly, the driving IC 100 charges the gate of the transistor M2 and turns on the transistor M2 by injecting a source current from the PMOS output transistor of the source current source 121 to the driving terminal GL, and also discharges the gate of the transistor M2 and turns off the transistor M2 by drawing a sink current from the driving terminal GL into the NMOS output transistor of the sink current source 122.

Furthermore, the driving IC 100 includes a high-side source current source 111 as a first driving source 110 that uses a boosted voltage (power supply voltage VCP) generated by a charge pump in the power supply circuit 101. The driving IC 100 includes a low-side source current source 121 as a second driving source 120 that uses a regulator voltage VRG generated by a regulator in the power supply circuit 101.
In the driving IC 100, the output signal RDY of the comparator provided in the regulator 10 or the charge pump circuit 20 of the power supply circuit in the modified example of the embodiment may be supplied to the logic circuit 131, or a signal delayed by a predetermined number of seconds by a counter may be generated and supplied. The comparator functions as a voltage monitoring circuit that monitors the voltage VCP generated by the charge pump circuit 20.

When the voltage VCPH generated by the charge pump circuit 20 becomes higher than a predetermined potential and the output signal RDY of the voltage monitoring circuit (comparator) is asserted, the logic circuit 131 enables the operation of the high-side source current source 111 and the low-side source current source 121. This causes the logic circuit 131 to start generating the source control drive command HHIN and the sink control drive command HLIN based on the high-side command signal HIN and the low-side command signal LIN.

In addition, the logic circuit 131 begins generating the source control drive command LHIN and the sink control drive command LLIN based on the high-side command signal HIN and the low-side command signal LIN. In this way, by asserting the output signal RDY of the voltage monitoring circuit (comparator), the first drive source 110 and the second drive source 120 can prevent the first drive source 110 and the second drive source 120 from driving the transistors M1 and M2 when the power supply voltage VCP generated by the boost operation of the charge pump has not risen sufficiently.

Although the present invention has been described above based on the embodiments, the present invention is not limited to the above embodiments. For example, in the above embodiments, the circuit that generates the gate voltage of the pull-down transistor NM1 is configured with a resistor R3 and a diode D2 connected in series between the input terminal IN and the ground point, but it is also possible to use a passive element other than a diode, such as a resistive element, in place of the diode D2.
Furthermore, in the above embodiment, an example of the use of regulator 10 has been described in which it is used as a power supply circuit within an IC for driving a motor, but the regulator of the present invention can be widely used as a power supply circuit within an IC that drives a load other than a motor, or as a standalone power supply circuit.

10...Regulator, 11...Error amplifier, 12...Voltage divider circuit, 20...Charge pump circuit, M0...Output transistor, M1...Pull-down transistor, D1...Voltage protection diode, 100...Driver IC, 101...Power supply circuit, 110...First drive source, 120...Second drive source, 130...Control circuit, 131...Logic circuit, 200...Load (motor)

Claims (4)

A power supply circuit including a voltage regulator having a first transistor for output control connected between a voltage input terminal and a voltage output terminal, an amplifier for controlling the first transistor, and converting a DC voltage input to the voltage input terminal into a predetermined DC voltage and outputting the DC voltage,
the first transistor is an N-channel insulated gate field effect transistor,
a protection diode is provided between the voltage output terminal and the gate terminal of the first transistor such that a cathode terminal of the diode is connected to the gate terminal;
a second transistor for pull-down is provided between the gate terminal of the first transistor and a reference potential point;
a third transistor having a gate terminal to which an external control signal is input is provided between a gate terminal of the second transistor and a reference potential point;
a power supply circuit configured such that a voltage generated by a first passive element and a second passive element connected in series between the voltage input terminal and a reference potential point is applied to a gate terminal of the second transistor. The power supply circuit of claim 1, wherein the first passive element is a resistor, the second passive element is a reverse-connected diode, and the potential of the connection node between the resistor and the diode is applied to the gate terminal of the second transistor. The power supply circuit of claim 2, further comprising a charge pump circuit that boosts the output voltage of the voltage regulator. A power supply circuit according to claim 3,
a drive circuit for turning on and off a first drive means for injecting current into a load and a second drive means for drawing current from the load,
a first drive source that receives a first output voltage from the power supply circuit and turns on the first drive means;
a second drive source that receives a second output voltage from the power supply circuit and turns on the second drive means,
A drive circuit characterized in that the output voltage of the charge pump circuit is supplied to the first drive source as the first output voltage, and the output voltage of the voltage regulator is supplied to the second drive source as the second output voltage.