JP2025061400A - MEMORY COMPRISING MULTIPLE PORTIONS AND USED TO REDUCE PROGRAM DISTURBANCE AND METHOD FOR PROGRAMMING SAME - Patent application - Google Patents

Abstract

To provide a memory and a program method for reducing program disturbance and pass voltage disturbance when operating a three-dimensional memory.SOLUTION: A memory 100 includes a first portion 110, a second portion 120 and a controller 190. The first portion includes a first word line to the k-th word line. The second portion is formed above the first portion and includes the (k+1)th word line to the m-th word line. When the x-th word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to the (x-2)th word line, a second voltage to the (x-1)th word line, and a third voltage to the (x+1)th word line. x, k and m are positive integers.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a memory and a programming method, and more particularly to a memory that includes multiple portions and is used to reduce program disturbance, and a programming method thereof.

To increase memory capacity, three-dimensional memory structures have been developed. For example, three-dimensional stacked NAND flash memory is now available.

The 3D structure of memory can contain multiple layers to store more data in the same area. This structure has proven effective for increasing memory capacity.

However, as the number of layers increases, program disturb becomes more pronounced. Program disturb increases the failure rate of programming the memory. Also, pass-through voltage disturb occurs when using multiple layers of memory.

Therefore, there is a need in the art for a solution to reduce program disturb and pass voltage disturb when operating 3D memories.

One embodiment provides a memory including a first portion, a second portion, and a controller. The first portion includes, from bottom to top, a first word line to a kth word line. The second portion is formed on the first portion and includes, from bottom to top, a (k+1)th word line to an mth word line. When the xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to the (x-2)th word line, a second voltage to the (x-1)th word line, and a third voltage to the (x+1)th word line. x, k, and m are positive integers.

One embodiment provides a memory including a first portion, a second portion, and a controller. The first portion includes, from bottom to top, the (m+1)th word line to the nth word line. The second portion is formed below the first portion and includes, from bottom to top, the (k+1)th word line to the mth word line. When the xth word line is used to perform a program operation, the controller is used to apply a first voltage to the (x+2)th word line to the nth word line, a second voltage to the (x+1)th word line, a third voltage to the (x-1)th word line, a fourth voltage to the (m+1)th word line to the (x-2)th word line, and a fifth voltage to the (k+1)th word line to the mth word line. x, k, and m are integers. The fifth voltage is lower than the fourth voltage.

One embodiment provides a program method used to operate a memory. The memory includes a first portion and a second portion. The first portion includes, from bottom to top, a first word line to a kth word line. The second portion is formed on the first portion and includes, from bottom to top, a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the program method includes applying a first voltage to the first word line to the (x-2)th word line, applying a second voltage to the (x-1)th word line, and applying a third voltage to the (x+1)th word line.

One embodiment provides a program method used to operate a memory. The memory includes a first portion and a second portion formed below the first portion. The first portion includes, from bottom to top, the (m+1)th word line to the nth word line. The second portion includes, from bottom to top, the (k+1)th word line to the mth word line. The program method includes applying a first voltage to the (x+2)th word line to the nth word line, applying a second voltage to the (x+1)th word line, applying a third voltage to the (x-1)th word line, applying a fourth voltage to the (m+1)th word line to the (x-2)th word line, and applying a fifth voltage to the (k+1)th word line to the mth word line, when the xth word line is used to perform a program operation. x, k, and m are integers. The fifth voltage is lower than the fourth voltage.

These and other objects of the present invention will no doubt become obvious to those skilled in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 2 illustrates a memory according to one embodiment. 2 illustrates the memory of FIG. 1 operating under different conditions. FIG. 2 illustrates a memory according to another embodiment. FIG. 4 illustrates the memory of FIG. 3 operating under other conditions. FIG. 4 illustrates the memory of FIG. 3 operating under other conditions. FIG. 2 illustrates a memory according to another embodiment. FIG. 2 illustrates a memory according to another embodiment. 8 illustrates the memory of FIG. 7 operating under different conditions. FIG. 2 illustrates a memory according to another embodiment. 10 illustrates the memory of FIG. 9 operating under different conditions. FIG. 2 illustrates a memory according to another embodiment. FIG. 2 illustrates a flowchart of a programming method according to an embodiment. FIG. 13 shows a flowchart of a programming method according to another embodiment.

FIG. 1 illustrates a memory 100 according to one embodiment. The memory 100 may include a first portion 110, a second portion 120, and a controller 190. The first portion 110 may include, from bottom to top, a first word line WL1 to a kth word line WLk. The second portion 120 may be formed on top of the first portion 110 and may include, from bottom to top, a (k+1)th word line WL(k+1) to an mth word line WLm.

In this document, when a word line is said to be programmed, it may mean that the word line is used to perform a program operation. The program operation referred to in this document may be, for example, an operation to program a memory cell formed using a set of transistors.

When the xth word line WLx is used to perform a program operation, the controller 190 may apply a program voltage Vpgm to the xth word line WLx, the controller 190 may apply a first voltage V1 to the first word line WL1 to the (x-2)th word line WL(x-2), the controller 190 may apply a second voltage V2 to the (x-1)th word line WL(x-1), and the controller 190 may apply a third voltage V3 to the (x+1)th word line WL(x+1). x, k, and m are positive integers, 1<k<m, and 3≦x.

As shown in FIG. 1, the controller 190 may apply a fourth voltage V4 from the (x+2)th word line WL(x+2) to the mth word line WLm when the xth word line WLx is used to perform a program operation, where x<m-1.

In FIG. 1, as an example, the xth word line WLx is arranged in the first portion 110. However, the xth word line WLx may be arranged in the second portion 120 under different conditions.

Figure 2 shows the memory 100 of Figure 1 operating under another condition. In Figure 2, the xth word line WLx is located in the second portion 120. With respect to the applied voltages, Figure 2 can be similar to Figure 1, which is not repeated.

Figures 1 and 2 are merely examples, and each of the above word lines WL(x-2), WL(x-1), WL(x+1), and WL(x+2) can be located in the first portion 110 or the second portion 120.

For memory 100, the first voltage V1 may have a first level when the xth word line WLx is in the first portion 110 and may have a second level when the xth word line WLx is in the second portion 120, and the first level may be lower than the second level. For example, the first voltage V1 in FIG. 1 may have a lower value than the first voltage V1 in FIG. 2.

Figure 3 illustrates a memory 300 according to another embodiment. As with memories 100 and 300, memory 300 may include a third portion 130 in addition to first portion 110 and second portion 120.

The third portion 130 may be formed on the second portion 120 and includes, from bottom to top, the (m+1)th word line WL(m+1) to the nth word line WLn. As shown in FIG. 3, the controller 190 may apply the fourth voltage V4 to the (x+2)th word line WL(x+2) to the nth word line WLn, where m<n and x<(n-1), when the xth word line WLx is used to perform a program operation.

Figures 4 and 5 show the memory 300 of Figure 3 operating under other conditions. In Figure 3, the xth word line WLx used to perform a program operation is in the first portion 110. In Figures 4 and 5, the xth word line WLx is in the second portion 120 and the third portion 130, respectively.

Figures 3 to 5 are merely examples, and each of the above word lines WL(x-2), WL(x-1), WL(x+1), and WL(x+2) can be located in the first portion 110, the second portion 120, or the third portion 130.

For memory 300, the first voltage V1 may have a first level when the xth word line WLx is in the first portion 110, a second level when the xth word line WLx is in the second portion 120, and a third level when the xth word line WLx is in the third portion 130, where the first level may be lower than the second level and the second level may be lower than the third level. For example, the first voltage V1 in FIG. 3 may have a lower value than the first voltage V1 in FIG. 4, and the first voltage V1 in FIG. 4 may have a lower value than the first voltage V1 in FIG. 5.

6 shows a memory 600 according to another embodiment. The memory 600 may be similar to the memory 100 of FIG. 1 and FIG. 2. However, the structures of FIG. 1 and FIG. 2 may include only one deck, and the memory 600 may have a two-deck structure. In other words, the memory 100 may have a one-deck structure, and the memory 600 may have a two-deck structure. As shown in FIG. 6, the first portion 110 is of the deck DECK1, and the second portion 120 is of the deck DECK2. The two decks DECK1 and DECK2 may be separated by a junction oxide layer OL. The memory 600 may include a lower dummy word line DL, an upper dummy word line DU, and a junction oxide layer OL. The lower dummy word line DL may be formed on the first portion 110. The upper dummy word line DU may be formed under the second portion 120. The junction oxide layer OL may be formed between the lower dummy word line DL and the upper dummy word line DU. The voltages applied to the one-deck structure may be like the voltages applied to the two-deck structure according to the embodiment. For example, the voltages applied to the word lines of memory 600 may be like the voltages applied to the word lines of memory 100 of FIGS. 1 and 2 and are not repeatedly described.

7 and 8 show a memory 700 operating in two conditions according to another embodiment. The memory 700 may include a first portion 710, a second portion 720, and a controller 190. The first portion 710 may include, from bottom to top, the (m+1)th word line WL(m+1) to the nth word line WLn. The second portion 720 may be formed below the first portion 710 and may include, from bottom to top, the (k+1)th word line WL(k+1) to the mth word line WLm.

When the xth word line is used to perform a program operation, the controller 190 may apply a first voltage V71 to the (x+2)th word line WL(x+2) to the nth word line WLn, the controller 190 may apply a second voltage V72 to the (x+1)th word line WL(x+1), and the controller 190 may apply a third voltage V73 to the (x-1)th word line WL(x-1).

As shown in FIG. 7, when the word line WLx is disposed in the second portion 720, the controller 190 may apply the fifth voltage V75 to the (k+1)th word line WL(k+1) to the (x-2)th word line WL(x-2) when the xth word line is used to perform a program operation. In FIG. 7, x, k, and m are integers, and (k+2)<x<(m+1). The state of FIG. 7 may be substantially similar to the state of FIG. 1. However, FIG. 7 is provided to introduce FIG. 8 to FIG. 11.

As shown in FIG. 8, when the word line WLx used to perform the program operation is disposed in the first portion 710, the first voltage V71, the second voltage V72, and the third voltage V73 may be applied by the controller 190 as shown in FIG. 7. However, the controller 190 may apply a fourth voltage V74 from the (m+1)th word line WL(m+1) to the (x-2)th word line WL(x-2). The controller 190 may apply a fifth voltage V75 from the (k+1)th word line WL(k+1) to the mth word line WLm. In FIG. 8, x, k, and m are integers, 0≦k<m, and (m+2)<x<(n-1). The fifth voltage V75 may be lower than the fourth voltage V74.

According to another embodiment, as shown in FIG. 6, the first portion 710 and the second portion 720 shown in FIG. 7 and FIG. 8 may each be of two decks, and the two decks may be separated by a bond oxide layer. As shown in FIG. 6, the two decks may each have an upper dummy word line and a lower dummy word line.

Figure 9 illustrates memory 900 according to another embodiment. Figure 10 illustrates memory 900 of Figure 9 operating under different conditions.

As shown in FIG. 9, the memory 900 may have three portions 910, 920, and 930. The first portion 910 and the second portion 920 may be similar to the portions 710 and 720 shown in FIG. 7. The third portion 930 may be formed on the first portion 910 and includes, from bottom to top, a plurality of word lines WL(n+1) to WLq. The conditions in FIG. 9 may be similar to FIG. 7, where the word line WLx used to perform the program operation is located at the bottom 920. The controller 190 may apply a first voltage V71 to the plurality of word lines WL(n+1) to WLq in FIG. 9. The variable q is an integer, q>(n+1).

The memory 900 of FIG. 10 may have the same structure as that shown in FIG. 9. The conditions of FIG. 10 may be similar to FIG. 8, in which the word line WLx used to perform the program operation is located in the portion 910 above the bottom 920. The voltages applied to the portions 910 and 920 may be like the voltages applied to the portions 710 and 720 of FIG. 8. As shown in FIG. 9, the controller 190 may apply a first voltage V71 to the multiple word lines WL(n+1) to WLq of the portion 930.

11 shows a memory 1100 according to another embodiment. The first portion 1110 and the second portion 1120 of the memory 1100 may be like the portions 710 and 720 of FIG. 8, and the memory 1100 may further include a third portion 1130 formed below the second portion 1120. Similarly, the xth word line WLx may be used to perform a program operation. Thus, the memory 1100 may include three portions and may have a structure like the memory 900 of FIG. 9 and FIG. 10. As shown in FIG. 11, the third portion 1130 may include, from bottom to top, the first word line WL1 to the kth word line WLk. The controller 190 may apply a sixth voltage V76 to the first word line WL1 to the kth word line WLk. 0<k, and the sixth voltage V76 is lower than the fifth voltage V75.

Although the numbering of the portions and word lines is not the same, memories 900 and 1100 shown in Figures 9 through 11 can be considered the same memory operating under different conditions.

In FIG. 9, the word line (e.g., WLx) used to perform the program operation is located at the bottom of the three sections.

In FIG. 10, the word line (e.g., WLx) used to perform a program operation is located in the second lowest of the three sections.

In FIG. 11, the word line (e.g., WLx) used to perform the program operation is located at the top of the three sections.

As shown in Figures 9 to 11, when the word lines WLx used to perform the program operation are located in different portions, different voltages can be applied to the word lines below the word lines WLx according to the corresponding portions.

In the examples of Figures 9-11, the relationship between the voltages may be V76<V75<V74. In other words, the same voltage may be applied to the word line in the portion located below the corresponding portion of the word line (e.g., WLx) used to perform the program operation, and a lower voltage may be applied to the word line in the portion located lower.

Figure 12 shows a flow chart of a programming method 1200 according to one embodiment. The programming method 1200 may be used to operate the memory 100 of Figures 1 and 2, and the memory 300 of Figures 3 to 5. The method 1200 may include the following steps.
Step 1210: When the xth word line WLx is used to perform a program operation, the program method includes applying a first voltage V1 to the first word line WL1 to the (x-2)th word line WL(x-2);
Step 1220: Apply a second voltage V2 to the (x-1)th word line WL(x-1);
Step 1230: Apply a third voltage V3 to the (x+1)th word line WL(x+1).

Steps 1210 through 1230 may be performed when the xth word line WLx is used to perform a program operation. Furthermore, when the xth word line WLx is used to perform a program operation, the fourth voltage V4 may be applied as shown in FIGS. 1 through 5 and as described above. The relationships between the voltages (e.g., V1, V2, V3, and V4) shown in FIGS. 1 through 5 may be as described above.

Figure 13 shows a flow chart of a programming method 1300 according to one embodiment. The programming method 1300 may be used to operate the memory 700 of Figure 8, the memory 900 of Figures 9 and 10, and the memory 1100 of Figure 11. The method 1300 may include the following steps.
Step 1310: if the xth word line WLx is used to perform a program operation, apply a first voltage V71 from the (x+2)th word line WL(x+2) to the nth word line WLn;
Step 1320: Apply a second voltage V72 to the (x+1)th word line WL(x+1);
Step 1330: Apply a third voltage V73 to the (x-1)th word line WL(x-1);
Step 1340: Applying a fourth voltage V74 from the (m+1)th word line WL(m+1) to the (x-2)th word line WL(x-2);
Step 1350: Apply a fifth voltage V75 to the (k+1)th word line WL(k+1) through the mth word line WLm.

Steps 1310 through 1350 may be performed when the xth word line WLx is used to perform a program operation. Furthermore, when the xth word line WLx is used to perform a program operation, the sixth voltage V76 may be applied as shown in FIG. 11 and as described above. The relationships between the voltages shown in FIG. 7 through FIG. 11 (e.g., V71, V72, V73, V74, V75, and V76) may be as described above.

In summary, by using a memory partitioned to have multiple portions and applying voltages to the word lines of the memory depending on the portion, program disturb and pass voltage disturb can be reduced according to simulations and experiments. Furthermore, by using the same voltage source to apply voltages to the word lines of the same portion or the word lines of different portions, fewer voltage sources are required and the area of the system can be reduced. Thus, the problems in the art can be reduced.

Those skilled in the art will readily observe that numerous modifications and variations of the devices and methods may be made while retaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

100 Memory
110 First Part
120 Second Part
130 Third Part
190 Controller
300 Memory
600 Memory
700 Memory
710 First Part
720 Second Part
900 Memory
910 First Part
920 Second Part
1100 Memory
1110 First Part
1120 Second Part
1130 Third Part
1200 Programming Method
1300 Programming Method

Claims (20)

a first portion including, from bottom to top, a first word line through a kth word line;
a second portion formed on the first portion and including, from bottom to top, a (k+1)th word line through an mth word line;
a controller configured to apply a first voltage from the first word line to a (x-2)th word line, a second voltage to the (x-1)th word line, and a third voltage to the (x+1)th word line when the xth word line is used to perform a program operation;
A memory, where x, k, and m are positive integers, 1<k<m, and 3≦x. The memory of claim 1, wherein the controller is further configured to apply a fourth voltage from the (x+2)th word line to the mth word line when the xth word line is used to perform the program operation, where x<(m-1). a third portion formed on the second portion and including, from bottom to top, an (m+1)th word line through an nth word line;
2. The memory of claim 1, wherein the controller is further configured to apply a fourth voltage from the (x+2)th word line to the nth word line when the xth word line is used to perform the program operation, where m<n and x<(n-1). when the xth word line is in the first portion, the first voltage has a first level;
when the xth word line is in the second portion, the first voltage has a second level;
when the xth word line is in the third portion, the first voltage has a third level;
The memory of claim 3 , wherein the first level is lower than the second level, and the second level is lower than the third level. when the xth word line is in the first portion, the first voltage has a first level;
when the xth word line is in the second portion, the first voltage has a second level;
The memory of claim 1 , wherein the first level is lower than the second level. a lower dummy word line formed over the first portion;
an upper dummy word line formed below the second portion;
a junction oxide layer formed between the lower dummy word line and the upper dummy word line,
The memory of claim 1 , wherein the memory has a two-deck structure. a first portion including, from bottom to top, the (m+1)th word line through the nth word line;
a second portion formed below the first portion and including, from bottom to top, a (k+1)th word line through an mth word line;
a controller configured to apply a first voltage from the (x+2)th word line to the nth word line, a second voltage to the (x+1)th word line, a third voltage to the (x-1)th word line, a fourth voltage from the (m+1)th word line to the (x-2)th word line, and a fifth voltage from the (k+1)th word line to the mth word line when an xth word line is used to perform a program operation;
A memory, wherein x, k, and m are integers, 0≦k<m, (m+2)<x<(n-1), and the fifth voltage is less than the fourth voltage. a third portion formed below the second portion, the third portion including, from bottom to top, a first word line through a kth word line;
8. The memory of claim 7, wherein the controller is further configured to apply a sixth voltage from the first word line to the kth word line when the xth word line is used to perform the program operation, where 0<k and the sixth voltage is lower than the fifth voltage. a third portion formed on the first portion, the third portion comprising a plurality of word lines;
The memory of claim 7 , wherein the controller is further configured to apply the first voltage to the plurality of word lines if the xth word line is used to perform the program operation. an upper dummy word line formed below the first portion;
a lower dummy word line formed over the second portion;
a junction oxide layer formed between the upper dummy word line and the lower dummy word line,
The memory of claim 7 , wherein the memory has a two-deck structure. 1. A method of programming a memory, the memory comprising a first portion and a second portion, the first portion comprising, from bottom to top, a first word line through a kth word line, the second portion being formed on the first portion and comprising, from bottom to top, a (k+1)th word line through an mth word line, the method comprising:
applying a first voltage to a first word line through an (x-2)th word line when the xth word line is used to perform a program operation;
applying a second voltage to the (x-1)th word line;
applying a third voltage to the (x+1)th word line;
A programming method, wherein x, k, and m are positive integers, 1<k<m, and 3≦x. applying a fourth voltage from the (x+2)th word line to the mth word line;
12. The method of claim 11, wherein x<(m-1). the memory further comprises a third portion formed on the second portion, the third portion comprising, from bottom to top, an (m+1)th word line through an nth word line, and the programming method further comprises:
applying a fourth voltage from the (x+2)th word line to the nth word line;
12. The method of claim 11, wherein m<n and x<(n-1). when the xth word line is in the first portion, the first voltage has a first level;
when the xth word line is in the second portion, the first voltage has a second level;
when the xth word line is in the third portion, the first voltage has a third level;
14. The method of claim 13, wherein the first level is lower than the second level, and the second level is lower than the third level. when the xth word line is in the first portion, the first voltage has a first level;
when the xth word line is in the second portion, the first voltage has a second level;
12. The method of claim 11, wherein the first level is lower than the second level. The memory comprises:
a lower dummy word line formed over the first portion;
an upper dummy word line formed below the second portion;
a junction oxide layer formed between the lower dummy word line and the upper dummy word line,
12. The method of claim 11, wherein the memory has a two-deck structure. 1. A method of programming a memory, the memory comprising a first portion and a second portion formed below the first portion, the first portion comprising, from bottom to top, an (m+1)th word line through an nth word line, the second portion comprising, from bottom to top, a (k+1)th word line through an mth word line, the method comprising:
applying a first voltage from a (x+2)th word line to the nth word line when the xth word line is used to perform a program operation;
applying a second voltage to the (x+1)th word line;
applying a third voltage to the (x-1)th word line;
applying a fourth voltage to the (m+1)th word line through the (x-2)th word line;
applying a fifth voltage to the (k+1)th word line through the mth word line;
A method of programming, wherein x, k, and m are integers, 0≦k<m, (m+2)<x<(n-1), and the fifth voltage is less than the fourth voltage. the memory further comprises a third portion formed below the second portion, the third portion comprising, from bottom to top, a first word line through a kth word line, and the programming method further comprises:
applying a sixth voltage to the first word line through the kth word line;
20. The method of claim 17, wherein 0<k and the sixth voltage is less than the fifth voltage. the memory further comprising a third portion formed over the first portion, the third portion comprising a plurality of word lines, and the programming method further comprising:
20. The method of claim 17, further comprising applying the first voltage to the word lines in the third portion. The memory comprises:
an upper dummy word line formed below the first portion;
a lower dummy word line formed over the second portion;
a junction oxide layer formed between the upper dummy word line and the lower dummy word line,
20. The method of claim 17, wherein the memory has a two-deck structure.