JP2025014421A - Transistor driving device, inverter device, transistor driving method, and transistor driving program - Google Patents

Abstract

To provide a transistor driving device, etc. that can suppress effectively surge or noise in a control signal to be applied by a driver on a transistor.SOLUTION: A transistor driving device 30 includes a driver 135 that generates a control signal (switching pulse) to be applied to a control terminal of a transistor in accordance with an input driving pulse (PWM signal), and a driver power source circuit 40 that supplies power to the driver 135 and temporarily decreases the voltage to be supplied to the driver 135 in a period where the driving pulse (PWM signal) rises. The driving pulse (PWM signal) is also input to the driver power source circuit 40. At a timing based on the input driving pulse (PWM signal), the driver power source circuit 40 temporarily decreases the voltage to be supplied to the driver 135.SELECTED DRAWING: Figure 4

Description

This disclosure relates to a transistor driving device, etc.

Patent document 1 discloses an inverter device that converts direct current to alternating current. The inverter device typically includes multiple transistors that output alternating current by switching operations in response to control signals applied to control terminals such as the gate and base. A driver provided in the front stage of the transistor generates a control signal (switching signal) to be applied to the control terminal of the transistor in response to a drive pulse based on PWM (Pulse Width Modulation) or the like.

JP 2020-171100 A

Since each drive pulse contained in a PWM signal rises sharply, there is a risk that momentary surges or noise will occur in the control signal generated by the driver in response.

This disclosure has been made in light of these circumstances, and aims to provide a transistor driver and the like that can effectively suppress surges and noise in the control signal that a driver applies to a transistor.

To solve the above problem, a transistor driving device according to one embodiment of the present disclosure includes a driver that generates a control signal to be applied to a control terminal of a transistor in response to an input driving pulse, and a driver power supply circuit that supplies power to the driver and temporarily reduces the voltage supplied to the driver during the rising edge of the driving pulse.

According to this aspect, during the rising period of the drive pulse input to the driver, the voltage supplied to the driver temporarily drops, effectively suppressing surges and noise in the control signal that the driver outputs to the transistor.

Another aspect of the present disclosure is an inverter device. This device includes a transistor that converts direct current to alternating current by switching operation according to a control signal applied to a control terminal, a driver that generates a control signal according to an input drive pulse, and a driver power supply circuit that supplies power to the driver and temporarily reduces the voltage supplied to the driver during the rising edge of the drive pulse.

Yet another aspect of the present disclosure is a transistor driving method. This method includes generating a control signal to be applied to a control terminal of a transistor by a driver in response to an input drive pulse, and temporarily reducing the voltage supplied to the driver by a driver power supply circuit that supplies power to the driver during the rising edge of the drive pulse.

In addition, any combination of the above components, or expressions of these converted into methods, devices, systems, recording media, computer programs, etc., are also included in the present disclosure.

This disclosure makes it possible to effectively suppress surges and noise in the control signals that the driver applies to the transistors.

1 shows a schematic diagram of an inverter device that supplies polyphase AC to a motor. 2A and 2B show schematic diagrams of a drive pulse input to a driver and a control signal output from the driver to a control terminal of a transistor. 13 shows a schematic diagram of the output of a driver according to the magnitude of a resistance. 2A and 2B are schematic diagrams illustrating an example of the configuration of a transistor driving device. A specific configuration example of the driver power supply circuit will be described. 4 shows examples of a drive pulse, a voltage reduction pulse, and a driver voltage. 4 shows examples of a drive pulse, a voltage reduction pulse, and a driver voltage. 11 is a table illustrating a schematic operation of a drive circuit. The effect of this embodiment will be illustrated diagrammatically.

In the following, the form for carrying out the present disclosure (hereinafter also referred to as the embodiment) will be described in detail with reference to the drawings. In the description and/or drawings, the same or equivalent components, members, processes, etc. will be given the same reference numerals, and duplicate descriptions will be omitted. The scale and shape of each part shown in the figures are set for convenience in order to simplify the description, and are not to be interpreted as being limiting unless otherwise specified. The embodiment is an example, and does not limit the scope of the present disclosure in any way. All features and their combinations presented in the embodiment are not necessarily essential to the present disclosure. The embodiment is presented for convenience, broken down into components for each function and/or each group of functions that realize it. However, one component in the embodiment may actually be realized by a combination of multiple components that are separate, and multiple components in the embodiment may actually be realized by one component that is integrated.

Figure 1 shows a schematic diagram of an inverter device 10 according to the present embodiment, which supplies multi-phase AC to a motor 20. The inverter device 10 includes a converter 11 that rectifies three-phase AC, R-phase, S-phase, and T-phase supplied from a commercial power source or the like, and converts it into DC (pulsating current), a capacitor 12 that smoothes the DC converted by the converter 11 to form a waveform, and an inverter 13 that converts the DC smoothed by the capacitor 12 into AC.

Converter 11 is equipped with diodes 111 to 116 that rectify three-phase (R, S, T) AC supplied from a commercial power source or the like in a fixed direction (from bottom to top in the figure). Diode 111 passes current when the R-phase AC voltage is positive, diode 112 passes current when the R-phase AC voltage is negative, diode 113 passes current when the S-phase AC voltage is positive, diode 114 passes current when the S-phase AC voltage is negative, diode 115 passes current when the T-phase AC voltage is positive, and diode 116 passes current when the T-phase AC voltage is negative. These diodes 111 to 116 connected in a bridge form cause a pulsating current with a fixed direction and fluctuating magnitude to appear between the output terminals of converter 11. Capacitor 12 supplies DC that has been smoothed from the pulsating current obtained by converter 11 to inverter 13.

In the following, the DC voltage input between the high potential input terminal 131 and the low potential input terminal 132 of the inverter 13 via the converter 11 and the capacitor 12 is represented as V _DC . If the potential of the high potential line to which the high potential input terminal 131 is connected is V _dd and the potential of the low potential line to which the low potential input terminal 132 is connected is V _ss , then V _DC = V _dd - V _ss .

The inverter 13 outputs three-phase AC by switching operations of three-phase transistor pairs of U-phase, V-phase, and W-phase, which are connected in parallel between a high-potential line supplying a high DC potential _Vdd and _a low-potential line supplying a low DC potential Vss. In other words, the inverter 13 generates three-phase AC based on _{a DC} voltage VDC input between a high-potential input terminal 131 and a low-potential input terminal 132. Specifically, a U-phase inverter 13U that generates a U-phase AC based on _{the DC} voltage VDC, a V-phase inverter 13V that generates a V-phase AC based on _{the DC} voltage VDC, and a W-phase inverter 13W that generates a W-phase AC based on _{the DC} voltage VDC are provided in parallel. Since the inverters 13U, 13V, and 13W of each phase have a common configuration, they will be collectively referred to as inverter 13 as appropriate and described below.

The inverter 13 includes a high potential input terminal 131 to which a high DC power supply potential _Vdd is input, a low potential input terminal 132 to which a low DC power supply potential _Vss is input, and an AC output terminal 133 that is provided between a high potential line to which the high potential input terminal 131 is connected and a low potential line to which the low potential input terminal 132 is connected and outputs an AC voltage that fluctuates between _Vdd and _Vss . A high potential side transistor 134H is connected between the high potential line and the AC output terminal 133, and a low potential side transistor 134L is connected between the low potential line and the AC output terminal 133.

The high-side transistor 134H performs a switching operation to switch the conductive state of the current path in response to a pulse (control signal) supplied from the high-side driver 135H connected to its control terminal as a driver. The low-side transistor 134L performs a switching operation to switch the conductive state of the current path in response to a pulse (control signal) supplied from the low-side driver 135L connected to its control terminal as a driver. In the following, the high-side transistor 134H and the low-side transistor 134L are collectively referred to as transistor 134 or transistor pair 134 as appropriate, and the high-side driver 135H and the low-side driver 135L are collectively referred to as driver 135 or driver pair 135 as appropriate. In the following description, "H" meaning "high side" and "L" meaning "low side" are omitted as appropriate, but in the drawings, "H" and "L" are added to the end of the symbols as necessary.

In the illustrated example, the transistor 134 is an insulated gate bipolar transistor (IGBT) having a gate 31 as a control terminal, a collector 32 as a high-potential side terminal connected to the high-potential line side, and an emitter 33 as a low-potential side terminal connected to the low-potential line side. However, the transistor 134 may be a field effect transistor (FET) having a gate as a control terminal, a drain as a high-potential side terminal, and a source as a low-potential side terminal, or a bipolar transistor having a base as a control terminal, a collector as a high-potential side terminal, and an emitter as a low-potential side terminal.

In the high-side transistor 134H, the gate 31H is connected to the high-side driver 135H, the collector 32H is connected to the high-side input terminal 131 or the high-side line, and the emitter 33H is connected to the AC output terminal 133 and the collector 32L of the low-side transistor 134L. In the low-side transistor 134L, the gate 31L is connected to the low-side driver 135L, the collector 32L is connected to the AC output terminal 133 and the emitter 33H of the high-side transistor 134H, and the emitter 33L is connected to the low-side input terminal 132 or the low-side line. In the above configuration, the connection point between the emitter 33H of the high-side transistor 134H and the collector 32L of the low-side transistor 134L forms the AC output terminal 133.

In each transistor 134, the current path or channel between the collector 32 and the emitter 33 switches its conductive state in response to a pulse (control signal) applied to the gate 31 from each driver 135. A protective diode 34 is provided in parallel with this current path or channel as a protective diode element. The protective diode 34 may be a discrete element separate from the transistor 134, or may be formed integrally or monolithically with the transistor 134 during the semiconductor manufacturing process for manufacturing the transistor 134. The protective diode 34 is provided so as to pass current only in the direction from the low potential line side to the high potential line side.

The driver 135, which may be configured as an integrated circuit (IC), supplies a switching pulse to the gate 31 of the transistor 134 as a control signal for the switching operation. For example, the driver 135 applies a pulse whose duty ratio is controlled by PWM to the gate 31 of the transistor 134. The transistor 134 performs a switching operation between an on state and an off state depending on the presence or absence of a pulse. Specifically, while a pulse is applied to the gate 31, the transistor 134 is in an on state, and the channel between the collector 32 and the emitter 33 is in a conductive state. Meanwhile, while a pulse is not applied to the gate 31, the transistor 134 is in an off state, and the channel between the collector 32 and the emitter 33 is in a non-conductive state.

The driver 135 of each phase converts DC to AC of each phase by performing switching control to complementarily switch the conductive state of a transistor pair consisting of a high-side transistor 134H and a low-side transistor 134L under the control of a control unit (not shown). Here, "complementarily switching" means controlling so that the transistor pairs of each phase are not simultaneously turned on. In other words, when one transistor in each phase is turned on, the other transistor in the phase is controlled to be turned off. However, it is permitted that the transistor pairs of each phase are simultaneously turned off. Specifically, for the U phase, when the high-side transistor 134H is turned on, the low-side transistor 134L is controlled to be turned off, and when the low-side transistor 134L is turned on, the high-side transistor 134H is controlled to be turned off. Therefore, when the high potential side transistor 134H is on, a high potential _Vdd appears at the U-phase AC output terminal 133U, and when the low potential side transistor 134L is on, a low potential _Vss appears at the U-phase AC output terminal 133U. By periodically repeating such switching control, a U-phase AC is generated in which the high potential _Vdd and the low potential _Vss appear alternately at the U-phase AC output terminal 133U.

The three-phase AC generated by the inverter 13 as described above is supplied to the motor 20 that generates rotational power. The motor 20 is, for example, a three-phase brushless motor equipped with three-phase coils 20U, 20V, and 20W of U-phase, V-phase, and W-phase. A U-phase current flows from the AC output terminal 133U of the U-phase inverter 13U to the U-phase coil 20U, a V-phase current flows from the AC output terminal 133V of the V-phase inverter 13V to the V-phase coil 20V, and a W-phase current flows from the AC output terminal 133W of the W-phase inverter 13W to the W-phase coil 20W. The inverters 13U, 13V, and 13W of each phase apply three-phase AC of different phases to the coils 20U, 20V, and 20W of each phase based on the rotational position of the rotor detected by the hall elements H1, H2, and H3 of the motor 20 to generate a rotating magnetic field. The desired rotational power can be obtained from the rotor that rotates by this rotating magnetic field. Note that motor 20 may be another type of motor driven by AC. Furthermore, the number of phases of motor 20 is not limited to three and may be any natural number. Similarly, the number of phases of the AC input to converter 11 is not limited to three and may be any natural number.

FIG. 2 shows, as an example, a driver 135 for the high-side transistor 134H in the U-phase inverter 13U, and diagrammatically illustrates the drive pulse input to the driver 135 and the control signal output by the driver 135 to the control terminal of the transistor 134. The drive pulse in the illustrated example is a PWM signal whose duty ratio is controlled by PWM. The driver 135 generates a switching pulse as a control signal in response to this PWM signal (drive pulse). For example, the driver 135 generates a switching pulse whose width is based on each drive pulse included in the PWM signal. In this way, the switching pulse itself generated based on the drive pulse as a PWM signal may constitute a PWM signal whose width or duty ratio is controlled.

A resistor 136 such as a gate resistor through which a switching pulse (control signal) passes may be provided between the driver 135 and the transistor 134. FIG. 3 shows a schematic diagram of the output of the driver 135 (or the input of the transistor 134) according to the magnitude of the resistor 136. As shown in the schematic diagram at the top of FIG. 3, the drive pulse that is the input to the driver 135 rises vertically.

When resistor 136 is small (gate resistance: small), a sudden rise in the drive pulse can cause a momentary surge or overshoot in the control signal. Such a surge or overshoot can place an excessive load on the transistor 134 that receives it, potentially shortening the lifespan of the transistor 134. In addition, the momentary surge or overshoot can also cause noise in the switching operation of transistor 134, which can lead to increased emissions (emission of unwanted electromagnetic noise).

By increasing the resistance 136 (gate resistance: large), it is possible to suppress momentary surges and noise in the control signal. However, in this case, the rise of the control signal will be delayed (the waveform will become dull), which may worsen the efficiency of the switching operation of transistor 134.

As described above, there is a trade-off or a trade-off between the size of resistor 136. In other words, it is difficult to achieve both suppression of momentary surges and noise in the control signal (when resistor 136 is small) and a steep rise in the control signal (when resistor 136 is large) using resistor 136 alone.

To solve these problems, this embodiment proposes a transistor driving device 30 having a configuration as shown in FIG. 4. The transistor driving device 30 includes the aforementioned driver 135 that generates a control signal to be applied to the control terminal of the transistor 134 in response to an input driving pulse, and a driver power supply circuit 40 that supplies power to the driver 135. As will be described later with reference to a specific example, the driver power supply circuit 40 temporarily reduces the voltage supplied to the driver 135 during the rising period of the driving pulse. In this way, the driving pulse is also input to the driver power supply circuit 40 so that the driver power supply circuit 40 can perform a voltage reduction process synchronized with the driving pulse.

Figure 5 shows a specific example of the configuration of the driver power supply circuit 40. As long as at least some of the functions and/or effects of the driver power supply circuit 40 described below are realized, the driver power supply circuit 40 may be configured in a manner different from the example shown. The driver power supply circuit 40 in the figure includes a delay circuit 41, a voltage drop pulse generating circuit 42, a voltage drop limit generating unit 43, a comparison circuit 44, a drive circuit 45, and a pair of transistors 46H and 46L. These components and/or functional blocks may be realized as analog circuits and/or analog parts, or may be realized digitally by the cooperation of hardware resources such as the arithmetic processing unit, memory, input device, output device, and peripheral devices connected to the computer and/or processor, and software executed using them.

Although details will be described later, Figures 6 and 7 show examples of the drive pulse (PWM signal) that is the input to the driver power supply circuit 40, the voltage reduction pulse at "point A" in Figure 5 (a point between the delay circuit 41/voltage reduction pulse generating circuit 42 and the drive circuit 45), and the driver voltage Vout that is the output of the driver power supply circuit 40.

The delay circuit 41 adds a predetermined voltage drop delay to the input drive pulse (PWM signal). The voltage drop pulse generating circuit 42 generates a voltage drop pulse with a predetermined voltage drop period at a timing based on the input drive pulse (PWM signal). As shown in the schematic diagram, the delay circuit 41 and the voltage drop pulse generating circuit 42 may be configured as substantially a single circuit.

As shown in FIG. 6 and FIG. 7, at "point A" in FIG. 5, a predetermined voltage drop delay D is added to the PWM signal (drive pulse) by the delay circuit 41, and a voltage drop pulse of a predetermined voltage drop period W generated by the voltage drop pulse generating circuit 42 appears. In other words, a voltage drop pulse of a voltage drop width W is generated after the voltage drop delay D has elapsed from the rising time of the PWM signal (drive pulse). Here, the voltage drop delay D by the delay circuit 41 and/or the voltage drop period W (voltage drop width W) by the voltage drop pulse generating circuit 42 can be set arbitrarily. In other words, the delay circuit 41/voltage drop pulse generating circuit 42 can generate a voltage drop pulse of an arbitrary width (voltage drop period W) that is delayed by an arbitrary time (voltage drop delay D) from the PWM signal (drive pulse).

The voltage drop limit generating unit 43 generates the voltage drop limit Vref, which is an arbitrary limit (lower limit) when the driver power supply circuit 40 temporarily drops the voltage (driver voltage Vout) supplied to the driver 135, based on the power supply potential (VCC).

The comparison circuit 44 compares the arbitrary voltage drop limit Vref generated by the voltage drop limit generation unit 43 with the driver voltage Vout, which is the output of the driver power supply circuit 40. Details will be described later with reference to FIG. 7, but when the driver voltage Vout, which is the power supplied to the driver 135, drops to the voltage drop limit Vref, the driver power supply circuit 40 stops the temporary voltage drop process.

The drive circuit 45 generates a drive signal for a pair of subsequent transistors 46H, 46L according to the voltage drop pulse at "point A" generated by the delay circuit 41/voltage drop pulse generation circuit 42 and the result of the comparison between the driver voltage Vout and the voltage drop limit Vref in the comparison circuit 44.

In a pair of push-pull transistors 46H, 46L, one is controlled to be in an on state and the other to be in an off state in response to a drive signal from the drive circuit 45. In the illustrated example, an NPN type high potential side (or source side) transistor 46H and a PNP type low potential side (or sink side) transistor 46L are connected in series between a high potential such as a power supply potential (VCC) and a low potential such as ground. The connection point between the high potential side transistor 46H and the low potential side transistor 46L constitutes a voltage output terminal from which the driver power supply circuit 40 outputs the driver voltage Vout. The same drive signal from the drive circuit 45 is applied to the bases, which serve as control terminals of the transistors 46H, 46L, but the on and off states are reversed because the transistor types (models) are different.

When the high-side transistor 46H is on and the low-side transistor 46L is off, the driver voltage Vout is a high potential such as the power supply potential (VCC). On the other hand, when the low-side transistor 46L is on and the high-side transistor 46H is off, the driver voltage Vout drops from a high potential such as the power supply potential (VCC). As a rule, both transistors 46H and 46L are not on at the same time, so there is a low risk of a through current occurring between the high and low potentials.

In the driver power supply circuit 40 configured as described above, the drive circuit 45 generates a drive signal that turns on one of the high-side transistor 46H (Q1) and the low-side transistor 46L (Q2) and turns off the other in accordance with the table shown in FIG. 8.

When the level of the voltage reduction pulse at "point A" generated by the delay circuit 41/voltage reduction pulse generating circuit 42 is "Low," the high-side transistor 46H (Q1) is controlled to the ON state and the low-side transistor 46L (Q2) is controlled to the OFF state, regardless of the magnitude relationship between the driver voltage Vout and the voltage reduction limit Vref. In this case, the driver voltage Vout becomes a high potential such as the power supply potential (VCC).

When the level of the voltage reduction pulse at "point A" generated by the delay circuit 41/voltage reduction pulse generating circuit 42 is "High" and the driver voltage Vout is greater than the voltage reduction limit Vref, the low-potential side transistor 46L (Q2) is controlled to the ON state and the high-potential side transistor 46H (Q1) is controlled to the OFF state. In this case, the driver voltage Vout drops from a high potential such as the power supply potential (VCC).

When the level of the voltage drop pulse at "point A" generated by the delay circuit 41/voltage drop pulse generating circuit 42 is "High" and the driver voltage Vout is equal to or lower than the voltage drop limit Vref, the high-side transistor 46H (Q1) is controlled to the ON state and the low-side transistor 46L (Q2) is controlled to the OFF state. In this case, the driver voltage Vout rises from the voltage drop limit Vref to a high potential such as the power supply potential (VCC).

The examples of Figures 6 and 7 show cases where the voltage drop period W (voltage drop width W) of the voltage drop pulse generated by the voltage drop pulse generating circuit 42 is different. In Figure 6, the voltage drop period W is relatively short, and in Figure 7, the voltage drop period W is relatively long.

In the example of FIG. 6, the delay circuit 41/voltage reduction pulse generating circuit 42 raises a voltage reduction pulse with a width of a voltage reduction period W at a timing delayed by a voltage reduction delay D from the rising edge of the PWM signal (drive pulse) (point A). During this voltage reduction period W, the low-potential side transistor 46L (Q2) is turned on, so the driver voltage Vout temporarily drops from the power supply potential (VCC).

In the example of FIG. 6, where the voltage drop period W is relatively short, the driver voltage Vout does not drop to the voltage drop limit Vref, so the low-side transistor 46L (Q2) is maintained in the on state throughout the voltage drop period W. Then, when this voltage drop period W ends, the high-side transistor 46H (Q1) is switched to the on state, and the temporarily dropped driver voltage Vout rises again to the power supply potential (VCC).

In the example of FIG. 7, the delay circuit 41/voltage reduction pulse generating circuit 42 also raises a voltage reduction pulse with a width of the voltage reduction period W at a timing delayed by the voltage reduction delay D from the rising edge of the PWM signal (drive pulse) (point A). During this voltage reduction period W, the low-potential side transistor 46L (Q2) is turned on, so the driver voltage Vout temporarily drops from the power supply potential (VCC).

In the example of FIG. 7, where the voltage drop period W is relatively long, the driver voltage Vout drops to the voltage drop limit Vref, so the drive circuit 45 switches the high-side transistor 46H (Q1) to the ON state according to the table in FIG. 8. In this way, in the example of FIG. 7, the voltage drop process is forcibly stopped without waiting for the end of the voltage drop period W. This effectively prevents the driver voltage Vout from dropping too much beyond the lower voltage drop limit Vref. After the voltage drop process is forcibly stopped, the driver voltage Vout, which has dropped to the voltage drop limit Vref, rises again to the power supply potential (VCC). Note that at the time of this re-rise, the condition "Vout > Vref" for switching the low-side transistor 46L (Q2) to the ON state is formally met, but the low-side transistor 46L (Q2) is maintained in the OFF state at least until the end of the current voltage drop period W.

As described above, in this embodiment, the driver power supply circuit 40 temporarily reduces the driver voltage Vout supplied to the driver 135 during the rising period of the input drive pulse (PWM signal) (e.g., at least the first half of the drive pulse) at a timing synchronized with the input drive pulse.

Figure 9 shows the effect of this embodiment. Figure 9(A) shows the rising edge period of a drive pulse (driver input) such as a PWM signal input in parallel to both the driver 135 and the driver power supply circuit 40 as shown in Figure 4. Figure 9(B) shows the driver voltage Vout shown in Figures 6 and 7. As described above, the driver voltage Vout temporarily drops during the rising edge period of the drive pulse.

The driver voltage Vout in FIG. 9(B) is divided into three periods, t1, t2, and t3. The first period t1 is the delay from the rising edge of the drive pulse in FIG. 9(A) until the driver voltage Vout starts to drop. This delay corresponds to the voltage drop delay D caused by the delay circuit 41 described above. The second period t2 is a period in which the driver voltage Vout temporarily drops due to the low-side transistor 46L being turned on, as illustrated in FIGS. 6 and 7. The third period t3 is a period in which the driver voltage Vout rises again due to the high-side transistor 46H being switched on, as illustrated in FIGS. 6 and 7.

The lengths of the first period t1, the second period t2, and the third period t3 can be set independently of each other. They may be the same as each other or different from each other. For example, the third period t3 may be set longer than the second period t2 in order to suppress ringing that may occur in the driver output.

Figure 9 (C) shows a schematic diagram of the control signal (driver output) as a switching pulse output by the driver 135 when the driver voltage Vout temporarily drops as in Figure 9 (B) (i.e., when the driver power supply circuit 40 constitutes a variable power supply). As shown in the figure, the driver output rises sharply as usual in the first period t1 before the driver voltage Vout drops. In the second period t2 when the driver voltage Vout drops, the rate of rise (slope) of the driver output becomes smaller (surge is suppressed). In the third period t3 when the driver voltage Vout rises again, the driver output drops gently and settles at the target value.

As a comparative example to FIG. 9(C), FIG. 9(D) shows a schematic diagram of a control signal (driver output) as a switching pulse output by the driver 135 when the driver voltage Vout is constant (i.e., when the driver power supply circuit 40 constitutes a fixed power supply). This is the same as the "Gate resistance: small" case in FIG. 3. That is, in response to the steep rise of the drive pulse in FIG. 9(A), a momentary surge or overshoot occurs in the driver output.

In contrast, in FIG. 9(C), during the rising period of the drive pulse input to the driver 135 (FIG. 9(A)), the voltage supplied to the driver 135 temporarily drops (FIG. 9(B)), effectively suppressing or reducing surges and noise in the control signal output by the driver 135 to the transistor 134. In addition, compared to the "large gate resistance" case in FIG. 3, the driver output (control signal) rises faster (waveform rounding is reduced), improving the efficiency of the switching operation of the transistor 134. This is particularly advantageous for motor drive devices (such as the inverter device 10 in this embodiment) that require high-speed operation and high responsiveness.

The present disclosure has been described above based on the embodiments. Various modifications are possible to the combinations of the components and processes in the exemplary embodiments, and it will be obvious to those skilled in the art that such modifications are included within the scope of the present disclosure.

In the above embodiment, an inverter device 10 is shown as an example of an application of this disclosure, but this disclosure can be applied to any device that has a driver for driving any transistor.

The configuration, action, and function of each device and method described in the embodiments can be realized by hardware resources or software resources, or by the cooperation of hardware resources and software resources. For example, a processor, ROM, RAM, and various integrated circuits can be used as hardware resources. For example, an operating system, an application, and other programs can be used as software resources.

10 inverter device, 13 inverter, 20 motor, 30 transistor drive device, 40 driver power supply circuit, 41 delay circuit, 42 voltage drop pulse generating circuit, 43 voltage drop limit generating unit, 44 comparison circuit, 45 drive circuit, 134 transistor, 135 driver.

Claims (8)

a driver that generates a control signal to be applied to a control terminal of a transistor in response to an input drive pulse;
a driver power supply circuit that supplies power to the driver and temporarily reduces a voltage supplied to the driver during a rising period of the drive pulse;
A transistor driver comprising: The drive pulse is also input to the driver power supply circuit,
the driver power supply circuit temporarily reduces a voltage supplied to the driver at a timing based on the input drive pulse;
2. The transistor driver according to claim 1. The transistor drive device according to claim 2, wherein the driver power supply circuit includes a delay circuit that adds a predetermined voltage drop delay to the input drive pulse, and temporarily reduces the voltage supplied to the driver at the timing when the voltage drop delay is added. The transistor drive device according to claim 2, wherein the driver power supply circuit includes a voltage reduction pulse generating circuit that generates a voltage reduction pulse for a predetermined voltage reduction period at a timing based on the input drive pulse, and reduces the voltage supplied to the driver over the voltage reduction period. The transistor drive device according to any one of claims 2 to 4, wherein the driver power supply circuit stops the voltage reduction process when the amount of reduction in the voltage supplied to the driver reaches a predetermined voltage reduction limit. a transistor that converts direct current into alternating current by a switching operation in response to a control signal applied to a control terminal;
A driver that generates the control signal in response to an input drive pulse;
a driver power supply circuit that supplies power to the driver and temporarily reduces a voltage supplied to the driver during a rising period of the drive pulse;
An inverter device comprising: generating a control signal to be applied to a control terminal of a transistor in response to a drive pulse input by a driver;
a driver power supply circuit that supplies power to the driver temporarily reduces a voltage supplied to the driver during a rising period of the drive pulse;
A transistor driving method for performing the above. generating a control signal to be applied to a control terminal of a transistor in response to a drive pulse input by a driver;
a driver power supply circuit that supplies power to the driver temporarily reduces a voltage supplied to the driver during a rising period of the drive pulse;
A transistor driving program that causes a computer to execute the above.

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