JP2025010712A - Power supply control device, switching power supply - Google Patents

Abstract

To switch a control state in accordance with a load with high accuracy.SOLUTION: A power supply control device controls an output stage of a switching power supply for generating an output voltage from an input voltage. The power supply control device comprises: a first ON-time setting circuit that is constructed so as to set a first ON-time in accordance with a difference between a feedback voltage and a predetermined reference voltage in accordance with the output voltage; a second ON-time setting circuit that is constructed so as to set a second ON-time in accordance with an output duty of the output stage; a control driving circuit that is constructed so as to drive the output stage in a predetermined switching frequency by using longer one of the first ON-time and second ON-time as an ON-time of the output stage; and a zero cross detection circuit that detects a zero cross of an inductor current flowing in the output stage. The second ON-time setting circuit adjusts the second ON-time in accordance with a detection result of the zero cross detection circuit.SELECTED DRAWING: Figure 12

Description

This disclosure relates to a power supply control device and a switching power supply using the same.

Conventionally, a power supply control device has been proposed that is configured to switch between continuous and intermittent operation of the output stage of a switching power supply depending on the weight of the load.

An example of related prior art is Patent Document 1.

JP 2021-045046 A

[overview]
However, in the conventional power supply control device, there is room for improvement in terms of drive switching control.

For example, the power supply control device according to the present disclosure is configured to control the output stage of a switching power supply that generates an output voltage from an input voltage, and includes a first on-time setting circuit configured to set a first on-time according to the difference between a feedback voltage corresponding to the output voltage and a predetermined reference voltage, a second on-time setting circuit configured to set a second on-time according to the output duty of the output stage, a control drive circuit configured to drive the output stage at a predetermined switching frequency with the longer of the first on-time and the second on-time as the on-time of the output stage, and a zero-cross detection circuit configured to detect zero-crossing of an inductor current flowing through the output stage, and the second on-time setting circuit adjusts the second on-time according to the detection result of the zero-cross detection circuit.

FIG. 1 is a diagram showing a first embodiment of a switching power supply. FIG. 2 is a diagram showing a light load control waveform (intermittent) in the first embodiment. FIG. 3 is a diagram showing a control flow of the intermittent drive. FIG. 4 is a diagram showing a light load control waveform (continuous) in the first embodiment. FIG. 5 is a diagram showing a heavy load control waveform (continuous) in the first embodiment. FIG. 6 is a diagram showing a light load control waveform (intermittent) under the first condition. FIG. 7 is a diagram showing a control switching load waveform under the first condition. FIG. 8 is a diagram showing a light load control waveform (intermittent) under the second condition. FIG. 9 is a diagram showing a control switching load waveform under the second condition. FIG. 10 is a diagram showing a light load control waveform (intermittent) under the third condition. FIG. 11 is a diagram showing a light load control waveform (intermittent) under the fourth condition. FIG. 12 is a diagram showing a second embodiment of the switching power supply. FIG. 13 is a diagram illustrating an example of the configuration of the reference voltage generating circuit. FIG. 14 is a diagram showing a light load control waveform (intermittent) in the second embodiment. FIG. 15 is a diagram showing a control switching load waveform in the second embodiment. FIG. 16 is a diagram showing a modified example of the second on-time setting circuit.

Detailed Description
<Switching power supply (first embodiment)>
1 is a diagram showing a first embodiment of a switching power supply (corresponding to a comparative example to be compared with a second embodiment described later). A switching power supply A of this embodiment generates a desired output voltage Vo from an input voltage Vi and supplies the output voltage Vo to a load (not shown). With reference to this figure, the switching power supply A includes a power supply control device 1 and an output stage 2.

The power supply control device 1 is a semiconductor device (a so-called power supply control IC [integrated circuit]) that controls the output stage 2 as the main controller of the switching power supply A.

The output stage 2 is controlled by the power supply control device 1. The output stage 2 generates a square-wave switch voltage SW from the input voltage Vi. The output stage 2 rectifies and smoothes the switch voltage SW to generate the output voltage Vo.

The output stage 2 is formed by a plurality of elements that are integrated into or externally attached to the power supply control device 1. In accordance with this diagram, the output stage 2 includes an output transistor M1 (e.g., a PMOSFET [P-channel type metal oxide semiconductor field effect transistor]), a synchronous rectification transistor M2 (e.g., an NMOSFET [N-channel type MOSFET]), a capacitor C1, an inductor L1, and resistors R1 and R2.

The first end of the inductor L1 is connected to the application end of the switch voltage SW. The second end of the inductor L1 and the first ends of the capacitor C1 and resistor R1 are all connected to the application end of the output voltage Vo. The second end of the resistor R1 and the first end of the resistor R2 are all connected to the application end of the feedback voltage FB. The second ends of the capacitor C1 and resistor R2 are all connected to the ground end (= the application end of the ground voltage GND).

The output transistor M1 corresponds to the upper switch of the output stage 2. The source of the output transistor M1 is connected to the application terminal of the input voltage Vi. The drain of the output transistor M1 is connected to the application terminal of the switch voltage SW. The gate of the output transistor M1 is connected to the application terminal of the upper gate signal HG. The output transistor M1 is in the on state when the upper gate signal HG is at a low level, and in the off state when the upper gate signal HG is at a high level.

The synchronous rectifier transistor M2 corresponds to the lower switch of the output stage 2. The source of the synchronous rectifier transistor M2 is connected to the ground terminal. The drain of the synchronous rectifier transistor M2 is connected to the application terminal of the switch voltage SW. The gate of the synchronous rectifier transistor M2 is connected to the application terminal of the lower gate signal LG. The synchronous rectifier transistor M2 is in the ON state when the lower gate signal LG is at a high level, and in the OFF state when the lower gate signal LG is at a low level.

The output transistor M1 and the synchronous rectifier transistor M2 are turned on/off in a complementary manner in response to the upper gate signal HG and the lower gate signal LG. This on/off operation generates a square-wave switch voltage SW at the first end of the inductor L1, which is pulse-driven between the input voltage Vi and the ground voltage GND. The term "complementary" above includes cases where the on/off states of the output transistor M1 and the synchronous rectifier transistor M2 are completely reversed, as well as cases where a period during which both transistors are simultaneously off (dead time) is provided.

In this way, the output stage 2 may be a step-down type with a synchronous rectification method. However, the rectification method of the output stage 2 is not limited to the above synchronous rectification method, and a diode rectification method using a rectifier diode as a lower switch may be adopted. When the synchronous rectification method is adopted, the drain-source voltage of the synchronous rectification transistor M2 (=Ron(M2)×IL, where Ron(M2) is the on-resistance of the synchronous rectification transistor M2) may be used as the current information of the inductor current IL flowing through the synchronous rectification transistor M2. On the other hand, when the diode rectification method is adopted, a means for detecting the current information is separately required. Also, the output transistor M1 may be replaced with an NMOSFET. However, in that case, a circuit (such as a bootstrap circuit or a charge pump circuit) for raising the high level of the upper gate signal HG to a voltage level higher than the input voltage Vi is required.

In particular, when a high voltage is applied as the input voltage Vi, it is preferable to use high-voltage elements such as a power MOSFET, an IGBT [insulated gate bipolar transistor], and a SiC transistor as the output transistor M1 and the synchronous rectification transistor M2, respectively. Also, GaN devices may be used as the output transistor M1 and the synchronous rectification transistor M2, respectively.

<Power supply control device>
Continuing with reference to Fig. 1, the configuration and operation of the power supply control device 1 will be described. The power supply control device 1 includes a first on-time setting circuit 10, a second on-time setting circuit 20, an oscillator 30, an OR gate 40, a control drive circuit 50, a zero-cross detection circuit 60, and a feedback voltage detection circuit 70.

The first on-time setting circuit 10 sets the first on-time Ton1 according to the difference between the feedback voltage FB, which corresponds to the output voltage Vo, and a predetermined reference voltage VREF. The first on-time Ton1 corresponds to the on-time Ton of the output transistor M1 in a heavy load control state (during continuous driving). This will be described in detail later.

With reference to this diagram, the first on-time setting circuit 10 includes an error voltage generating circuit 11, a first ramp voltage generating circuit 12, an adder circuit 13, and a comparator 14.

The error voltage generating circuit 11 may be an error amplifier that generates an error voltage AMPOUT according to the difference between a feedback voltage FB applied to the inverting input terminal (-) and a reference voltage VREF applied to the non-inverting input terminal (+). The error voltage AMPOUT corresponds to voltage feedback information according to the output voltage Vo. For example, the error voltage AMPOUT rises when the feedback voltage FB is lower than the reference voltage VREF. On the other hand, the error voltage AMPOUT falls when the feedback voltage FB is higher than the reference voltage VREF. The error amplifier used as the error voltage generating circuit 11 may be a current output type amplifier that generates a charge/discharge current for a phase compensation capacitor (not shown).

The feedback voltage FB may be, for example, a divided voltage of the output voltage Vo. When the output voltage Vo is within the input dynamic range of the error voltage generating circuit 11, the output voltage Vo may be directly input to the error voltage generating circuit 11 as the feedback voltage FB. The reference voltage VREF may be, for example, a bandgap voltage with a relatively flat temperature characteristic.

The first ramp voltage generating circuit 12 generates a first ramp voltage VRAMPPWM that rises during the on-time Ton of the output transistor M1. With reference to this figure, the first ramp voltage generating circuit 12 includes a current source 121, a capacitor 122, and a transistor 123 (e.g., an NMOSFET). The current source 121 generates a charging current for the capacitor 122. The charging voltage (= voltage between both ends) of the capacitor 122 corresponds to the first ramp voltage VRAMPPWM. The transistor 123 functions as a discharge switch for the capacitor 122. For example, the first ramp voltage VRAMPPWM starts to rise from a zero value when the output transistor M1 is turned on, and is reset to a zero value when the output transistor M1 is turned off.

The adder circuit 13, for example, adds the switch voltage SW (corresponding to current feedback information according to the inductor current IL) detected during the on-time Ton of the output transistor M1 to the error voltage AMPOUT. The adder circuit 13 may also subtract the switch voltage SW detected during the on-time Ton of the output transistor M1 from the first ramp voltage VRAMPPWM. The inductor current IL may be detected by any method. For example, the voltage across a sense resistor connected in series to the output transistor M1 may be detected. Alternatively, the drain-source voltage of a current detection transistor connected in parallel to the output transistor M1 may be detected.

The comparator 14 generates the first reset signal XRSTPWM by comparing the error voltage AMPOUT input to the non-inverting input terminal (+), or more precisely, the offset error voltage (AMPOUT+SW) to which the switch voltage SW is added, with the first ramp voltage VRAMPPWM input to the inverting input terminal (-).

The first reset signal XRSTPWM is at a high level when VRAMPPWM<AMPOUT, and is at a low level when VRAMPPWM>AMPOUT. Therefore, the falling timing of the first reset signal XRSTPWM becomes slower the higher the error voltage AMPOUT is, and becomes earlier the lower the error voltage AMPOUT is.

By the above comparison process, the first on-time setting circuit 10 sets the intersection timing of the error voltage AMPOUT and the first ramp voltage VRAMPPWM as the end timing of the first on-time Ton1.

The second on-time setting circuit 20 sets the second on-time Ton2 according to the output duty Don of the output stage 2. The output duty Don is defined as the ratio of the on-time Ton of the output transistor M1 to the switching period Tsw (=Ton/Tsw). The second on-time Ton2 corresponds to the on-time Ton of the output transistor M1 in a light load control state (during continuous driving or intermittent driving). This point will be described in detail later.

With reference to this diagram, the second on-time setting circuit 20 includes a reference voltage generating circuit 21, a second ramp voltage generating circuit 22, and a comparator 23.

The reference voltage generating circuit 21 generates a reference voltage VTONLLM according to the output duty Don of the output stage 2. That is, the reference voltage VTONLLM becomes higher as the output duty Don increases, and becomes lower as the output duty Don decreases. In addition, an offset ΔVofs according to the bottom value IL_btm of the inductor current IL may be added to the reference voltage VTONLLM.

The second ramp voltage generating circuit 22 generates a second ramp voltage VRAMPLLM that rises during the on-time Ton of the output transistor M1. With reference to this figure, the second ramp voltage generating circuit 22 includes a current source 221, a capacitor 222, and a transistor 223 (e.g., an NMOSFET). The current source 221 generates a charging current for the capacitor 222. The charging voltage (= voltage between both ends) of the capacitor 222 corresponds to the second ramp voltage VRAMPLLM. The transistor 223 functions as a discharge switch for the capacitor 222. For example, the second ramp voltage VRAMPLLM starts to rise from a zero value when the output transistor M1 is turned on, and is reset to a zero value when the output transistor M1 is turned off.

The comparator 23 generates a second reset signal XRSTLLM by comparing the reference voltage VTONLLM input to the non-inverting input terminal (+) with the second ramp voltage VRAMPLLM input to the inverting input terminal (-).

The second reset signal XRSTLLM is at a high level when VRAMPLLM<VTONLLM, and is at a low level when VRAMPLLM>VTONLLM. Therefore, the falling timing of the second reset signal XRSTLLM becomes slower as the reference voltage VTONLLM is higher, and becomes earlier as the reference voltage VTONLLM is lower.

By the above comparison process, the second on-time setting circuit 20 sets the intersection timing of the reference voltage VTONLLM and the second ramp voltage VRAMPLLM as the end timing of the second on-time Ton2.

The oscillator 30 generates a set signal SET (corresponding to an on signal) that is pulse-driven at a predetermined switching frequency Fsw (=1/Tsw). The pulse generation timing (e.g., falling edge timing) of the set signal SET corresponds to the start timing of each of the first on time Ton1 and the second on time Ton2 described above, and further corresponds to the start timing of the on time Ton.

The OR gate 40 generates a reset signal XRST (corresponding to an off signal) by performing a logical OR operation on the first reset signal XRSTPWM and the second reset signal XRSTLLM. The reset signal XRST becomes high level when at least one of the first reset signal XRSTPWM and the second reset signal XRSTLLM is at a high level. The reset signal XRST becomes low level when both the first reset signal XRSTPWM and the second reset signal XRSTLLM are at a low level.

The control drive circuit 50 generates the upper gate signal HG and the lower gate signal LG in response to the set signal SET and the reset signal XRST. For example, the control drive circuit 50 sets both the upper gate signal HG and the lower gate signal LG to a low level at the falling edge of the set signal SET. As a result, the output transistor M1 is turned on and the synchronous rectification transistor M2 is turned off. On the other hand, the control drive circuit 50 resets both the upper gate signal HG and the lower gate signal LG to a high level at the falling edge of the reset signal XRST. As a result, the output transistor M1 is turned off and the synchronous rectification transistor M2 is turned on.

Therefore, the on-time Ton of the output transistor M1 (= the high-level period of the switch voltage SW) becomes longer as the falling timing of the reset signal XRST becomes later, and conversely, becomes shorter as the falling timing of the reset signal XRST becomes earlier.

As mentioned above, the reset signal XRST is a logical OR signal of the first reset signal XRSTPWM and the second reset signal XRSTLLM. Therefore, the control drive circuit 50 drives the output stage 2 at a predetermined switching frequency Fsw so that the on time Ton of the output stage 2 is the longer of the first on time Ton1 determined according to the falling timing of the first reset signal XRSTPWM and the second on time Ton2 determined according to the falling timing of the second reset signal XRSTLLM.

The zero-cross detection circuit 60 detects the zero crossing of the inductor current IL flowing through the output stage 2 and generates the zero-cross detection signal ZX. For example, the zero-cross detection circuit 60 may be a comparator that compares the switch voltage SW input to the non-inverting input terminal (+) with the ground voltage GND input to the inverting input terminal (-) to generate the zero-cross detection signal ZX. In this case, the zero-cross detection signal ZX is at a high level when the switch voltage SW is positive (>GND) and at a low level when the switch voltage SW is negative (<GND).

That is, the zero-cross detection signal ZX is at a low level (= the logic level when a zero cross is not detected) when the inductor current IL flows from the ground terminal through the synchronous rectification transistor M2 toward the inductor L1. On the other hand, the zero-cross detection signal ZX is at a high level (= the logic level when a zero cross is detected) when the inductor current IL flows from the inductor L1 toward the ground terminal through the synchronous rectification transistor M2.

The feedback voltage detection circuit 70 detects increases and decreases in the feedback voltage FB in a light load control state. For example, the feedback voltage detection circuit 70 includes a comparator 71 and a selector 72.

The comparator 71 generates a feedback voltage detection signal FBDET, for example, by comparing the feedback voltage FB input to the non-inverting input terminal (+) with the threshold voltage LLMREF input to the inverting input terminal (-).

When the feedback voltage detection signal FBDET is at a high level, the selector 72 selects the lower threshold voltage LLMREFL as the threshold voltage LLMREF. On the other hand, when the feedback voltage detection signal FBDET is at a low level, the selector 72 selects the upper threshold voltage LLMREFH as the threshold voltage LLMREF.

Therefore, when the feedback voltage detection signal FBDET is at a low level, if the feedback voltage FB exceeds the upper threshold voltage LLMREFH, the feedback voltage detection signal FBDET rises to a high level. On the other hand, when the feedback voltage detection signal FBDET is at a high level, if the feedback voltage FB falls below the lower threshold voltage LLMREFL, the feedback voltage detection signal FBDDET falls to a low level.

The zero-cross detection signal ZX and the feedback voltage detection signal FBDET are input to the control drive circuit 50 and are used for intermittent drive control in a light load control state (details will be described later).

Figure 2 is a diagram showing light load control waveforms (intermittent) in the first embodiment. From the top, the diagram shows the output voltage Vo, feedback voltage FB, switch voltage SW, inductor current IL, zero cross detection signal ZX, feedback voltage detection signal FBDET, set signal SET, second ramp voltage VRAMPLLM, second reset signal XRSTLLM, first ramp voltage VRAMPPWM, first reset signal XRSTPWM, reset signal XRST, and control state signal PWMCTL.

The control state signal PWMCTL is understood to be an internal signal of the control drive circuit 50. For example, the control state signal PWMCTL is at a high level when the first on-time Ton1 is longer than the second on-time Ton2. On the other hand, the control state signal PWMCTL is at a low level when the second on-time Ton2 is longer than the first on-time Ton1.

That is, in a state where the on-time Ton of the output transistor M1 is determined by the first on-time Ton1 (heavy load control state), the control state signal PWMCTL is at a high level. On the other hand, in a state where the on-time Ton of the output transistor M1 is determined by the second on-time Ton2 (light load control state), the control state signal PWMCTL is at a low level.

In this diagram, the second on-time Ton2 is longer than the first on-time Ton1. Therefore, the second reset signal XRSTLLM is output as the reset signal XRST. As a result, the on-time Ton of the output transistor M1 is determined by the second on-time Ton2.

That is, the control drive circuit 50 is in a light load control state (XRSTLLM = XRST, PWMCTL = L). In the light load control state, intermittent drive control of the output stage 2 is performed in response to the zero cross detection signal ZX and the feedback voltage detection signal FBDET.

In accordance with this diagram, when the feedback voltage detection signal FBDET rises to a high level and then the zero-cross detection signal ZX rises to a high level, the control drive circuit 50 keeps the output transistor M1 in the off state and also turns off the synchronous rectification transistor M2. In other words, the control drive circuit 50 stops driving the output stage 2 when the feedback voltage FB exceeds the upper threshold voltage LLMREFH and then a zero crossing of the inductor current IL is detected.

When the drive of the output stage 2 is stopped, both the output transistor M1 and the synchronous rectification transistor M2 are turned off. As a result, the switch voltage SW is approximately equal to the output voltage Vo. When the drive of the output stage 2 is stopped, the generation of the set signal SET is also stopped.

On the other hand, when the feedback voltage detection signal FBDET rises to a low level, the control drive circuit 50 resumes the generation of the set signal SET and turns on the output transistor M1 again. In other words, the control drive circuit 50 resumes driving the output stage 2 when the feedback voltage FB falls below the lower threshold voltage LLMREFL while the driving of the output stage 2 is stopped.

By the above series of controls, intermittent driving of the output stage 2 is performed in the light load control state. As a result, the feedback voltage FB repeatedly rises and falls in a voltage range higher than the reference voltage VREF.

Figure 3 is a diagram showing the control flow of intermittent drive in the light load control state (XRSTLLM = XRST, PWMCTL = L) described above. First, in step S1, the output stage 2 is put into a drive state. In the following step S2, it is determined whether the feedback voltage detection signal FBDET has been raised to a high level. If the determination is yes here, the flow proceeds to step S3. On the other hand, if the determination is no, the flow returns to step S1 and the output stage 2 is maintained in a drive state.

If the answer is yes in step S2, then in step S3 it is determined whether the zero-cross detection signal ZX has been raised to a high level. If the answer is yes, the flow proceeds to step S4. On the other hand, if the answer is no, the flow returns to step S3, and monitoring of the zero-cross detection signal ZX continues.

If the answer is yes in step S3, the output stage 2 is stopped in step S4. In the following step S5, it is determined whether the feedback voltage detection signal FBDET has been lowered to a low level. If the answer is yes, the flow returns to step S1 and driving of the output stage 2 is resumed. On the other hand, if the answer is no, the flow returns to step S4 and the output stage 2 is maintained in a stopped state.

Figure 4 is a diagram showing light load control waveforms (continuous) in the first embodiment. In this figure, similar to the above-mentioned Figure 2, from the top, the output voltage Vo, the feedback voltage FB, the switch voltage SW, the inductor current IL, the zero-cross detection signal ZX, the feedback voltage detection signal FBDET, the set signal SET, the second ramp voltage VRAMPLLM, the second reset signal XRSTLLM, the first ramp voltage VRAMPPWM, the first reset signal XRSTPWM, the reset signal XRST, and the control state signal PWMCTL are depicted.

In this diagram, as in FIG. 2, the second on-time Ton2 is longer than the first on-time Ton1, resulting in a light load control state (PWMCTL=L, XRSTLLM=XRST). However, in this diagram, as the output current Io increases, the feedback voltage FB does not exceed the upper threshold voltage LLMREFH. Therefore, the feedback voltage detection signal FBDET does not rise to a high level, and the output stage 2 is maintained in a driving state. In other words, the output stage 2 continues to be driven continuously without switching to intermittent driving. This state corresponds to the state in FIG. 3 where a NO decision is made in step S2 and steps S1 and S2 are looped over and over again.

Figure 5 is a diagram showing heavy load control waveforms (continuous) in the first embodiment. In this figure, similar to the above-mentioned Figures 2 and 4, from the top, the output voltage Vo, feedback voltage FB, switch voltage SW, inductor current IL, zero-cross detection signal ZX, feedback voltage detection signal FBDET, set signal SET, second ramp voltage VRAMPLLM, second reset signal XRSTLLM, first ramp voltage VRAMPPWM, first reset signal XRSTPWM, reset signal XRST, and control state signal PWMCTL are depicted.

This diagram explains the conditions for switching from the light load control state (continuous) to the heavy load control state (continuous). As described above, the reference voltage VTONLLM for determining the second on-time Ton2 is given an offset ΔVofs according to the bottom value IL_btm of the inductor current IL.

Specifically, when the bottom value IL_btm of the inductor current IL is a positive value (>0), a negative offset ΔVofs(-) is applied to the reference voltage VTONLLM. On the other hand, when the bottom value IL_btm of the inductor current IL is a negative value (<0), a positive offset ΔVofs(+) is applied to the reference voltage VTONLLM. Note that when the bottom value IL_btm of the inductor current IL is 0, the offset ΔVofs applied to the reference voltage VTONLLM is also 0.

As shown in this figure, when the bottom value IL_btm of the inductor current IL becomes positive as the output current Io increases, the reference voltage VTONLLM is lowered by the negative offset ΔVofs(-). Therefore, the intersection timing of the reference voltage VTONLLM and the second ramp voltage VRAMPLLM, and therefore the falling timing of the second reset signal XRSTLLM, are advanced. As a result, the second on-time Ton2 is shortened.

When the first on-time Ton1 becomes longer than the second on-time Ton2, the first reset signal XRSTPWM is output as the reset signal XRST. Therefore, the on-time Ton of the output transistor M1 is determined by the first on-time Ton1. In addition, the control status signal PWMCTL is raised from low level to high level.

In this way, the control drive circuit 50 switches from a light load control state to a heavy load control state (XRSTPWM=XRST, PWMCTL=H) as the output current Io (and thus the bottom value IL_btm of the inductor current IL) increases.

<Considerations regarding variation in switching current>
However, in the power supply control device 1 of the first embodiment, there are many parameter elements that determine the switching current between the light load control state and the heavy load control state, so the switching current is prone to variation.

The above switching current can be understood as the average value IL_ave (and therefore the output current Io) of the inductor current IL at which the light load control state and the heavy load control state switch, or the bottom value IL_btm.

In the following, as examples of parameter elements, the behavior of the reference voltage VTONLLM, the slope of the second ramp voltage VRAMPLLM, the feedback amount of the inductor current IL, and the switching frequency Fsw when they vary will be considered.

6 and 7 are diagrams showing a light load control waveform (intermittent) and a control switching load waveform under the first condition, respectively. In each diagram, from top to bottom, the output voltage Vo, the feedback voltage FB, the switch voltage SW, the inductor current IL, the zero cross detection signal ZX, the feedback voltage detection signal FBDET, the set signal SET, the second ramp voltage VRAMPLLM, the second reset signal XRSTLLM, the first ramp voltage VRAMPPWM, the first reset signal XRSTPWM, the reset signal XRST, and the control state signal PWMCTL are depicted.

Under the first condition, the reference voltage VTONLLM is lower than the ideal value (= the original target value), the slope of the second ramp voltage VRAMPLLM is greater than the ideal value, or the switching frequency Fsw is lower than the ideal value. On the other hand, the feedback amount of the inductor current IL is the ideal value.

Under this first condition, the switching current between the light load control state and the heavy load control state varies less than the ideal value.

8 and 9 are diagrams showing the light load control waveform (intermittent) and the control switching load waveform under the second condition, respectively. In each diagram, from top to bottom, the output voltage Vo, the feedback voltage FB, the switch voltage SW, the inductor current IL, the zero cross detection signal ZX, the feedback voltage detection signal FBDET, the set signal SET, the second ramp voltage VRAMPLLM, the second reset signal XRSTLLM, the first ramp voltage VRAMPPWM, the first reset signal XRSTPWM, the reset signal XRST, and the control state signal PWMCTL are depicted.

Under the second condition, the reference voltage VTONLLM is higher than the ideal value, the slope of the second ramp voltage VRAMPLLM is smaller than the ideal value, or the switching frequency Fsw is higher than the ideal value. On the other hand, the feedback amount of the inductor current IL is the ideal value.

Under this second condition, the switching current between the light load control state and the heavy load control state varies more than the ideal value.

Figure 10 is a diagram showing a light load control waveform (intermittent) under the third condition. From the top, the diagram shows the output voltage Vo, feedback voltage FB, switch voltage SW, inductor current IL, zero cross detection signal ZX, feedback voltage detection signal FBDET, set signal SET, second ramp voltage VRAMPLLM, second reset signal XRSTLLM, first ramp voltage VRAMPPWM, first reset signal XRSTPWM, reset signal XRST, and control state signal PWMCTL.

Under the third condition, the reference voltage VTONLLM is lower than the ideal value, and the feedback amount of the inductor current IL is greater than the ideal value.

Under this third condition, the bottom value IL_btm of the inductor current IL fluctuates every time the output stage 2 switches. When this happens, the average value IL_ave of the inductor current IL (and therefore the output current Io) approaches a constant value, but the output duty Don becomes unstable.

Figure 11 is a diagram showing a light load control waveform (intermittent) under the fourth condition. From the top, the diagram shows the output voltage Vo, feedback voltage FB, switch voltage SW, inductor current IL, zero cross detection signal ZX, feedback voltage detection signal FBDET, set signal SET, second ramp voltage VRAMPLLM, second reset signal XRSTLLM, first ramp voltage VRAMPPWM, first reset signal XRSTPWM, reset signal XRST, and control state signal PWMCTL.

Under the fourth condition, the reference voltage VTONLLM is lower than the ideal value, and the feedback amount of the inductor current IL is smaller than the ideal value.

Under this fourth condition, the bottom value IL_btm of the inductor current IL decreases every time the output stage 2 switches. When this situation occurs, the average value IL_ave of the inductor current IL (and therefore the output current Io) decreases. As a result, the switching current between the light load control state and the heavy load control state becomes smaller than the ideal value.

In the following, in consideration of the above considerations, a second embodiment is proposed that can reduce the variation in switching current.

Second Embodiment
Fig. 12 is a diagram showing a second embodiment of the switching power supply A. The switching power supply A of this embodiment is based on the above-mentioned first embodiment (Fig. 1), but a change is made to the second on-time setting circuit 20 of the power supply control device 1.

The second on-time setting circuit 20 adjusts the second on-time Ton2 so that the bottom value IL_btm of the inductor current IL in the light load control state becomes 0 according to the detection result of the zero-cross detection circuit 60. By this adjustment process, the switching current between the light load control state and the heavy load control state becomes approximately 1/2 the ripple component of the inductor current IL.

The adjustment process of the second on-time Ton2 is realized by controlling the reference voltage VTONLLM up and down. Specifically, the reference voltage generating circuit 21 lowers the reference voltage VTONLLM when shortening the second on-time Ton2. On the other hand, the reference voltage generating circuit 21 raises the reference voltage VTONLLM when extending the second on-time Ton2.

To achieve the above adjustment process, the zero-cross detection signal ZX, the control state signal PWMCTL, and the upper control signal HGCTL are input to the reference voltage generation circuit 21. The upper control signal HGCTL is an internal signal of the control drive circuit 50. The upper control signal HGCTL has basically the same logical level as the upper gate signal HG.

Figure 13 is a diagram showing an example of the configuration of the reference voltage generation circuit 21. The reference voltage generation circuit 21 of this example configuration includes a first internal voltage generation circuit 211, a first resistor 212 (resistance value: Rx), a current mirror 213, a second resistor 214 (resistance value: Ry), a sample/hold circuit 215, and an adjustment circuit 216.

The first internal voltage generating circuit 211 receives the switch voltage SW as an input and generates a first internal voltage V1 according to the output duty Don of the output stage 2. In accordance with this diagram, the first internal voltage generating circuit 211 includes a voltage dividing/smoothing circuit 211a, an operational amplifier 211b, and a transistor 211c (e.g., an NMOSFET).

The voltage dividing/smoothing circuit 211a divides and smooths the switch voltage SW to generate a reference internal voltage V0. The reference internal voltage V0 increases as the output duty Don increases, and decreases as the output duty Don decreases. The voltage dividing/smoothing circuit 211a may include a resistive voltage dividing ladder and an RC low-pass filter, as shown in this figure.

Operational amplifier 211b controls the gate of transistor 211c so that the reference internal voltage V0 input to the non-inverting input terminal (+) and the first internal voltage V1 input to the inverting input terminal (-) are imaginarily shorted.

The drain of transistor 211c is connected to the input terminal of current mirror 213. The source of transistor 211c is connected to the application terminal of first internal voltage V1. The gate of transistor 211c is connected to the output terminal of operational amplifier 211b.

The first end of the first resistor 212 is connected to the application end of the first internal voltage V1. The second end of the first resistor 212 is connected to the ground end. The first resistor 212 connected in this manner functions as a voltage/current conversion element that converts the first internal voltage V1 applied to the first end into a first internal current I1 (=V1/Rx).

The current mirror 213 includes transistors 213a and 213b (both are PMOSFETs, for example). The sources of the transistors 213a and 213b are both connected to a power supply terminal. The gates of the transistors 213a and 213b are both connected to the drain of the transistor 213a. The drain of the transistor 213a is connected to the drain of the transistor 211c as the input terminal of the current mirror 213. The drain of the transistor 213b is connected to the application terminal of the second internal voltage V2 as the output terminal of the current mirror 213. The current mirror 213 configured in this manner mirrors the first internal current I1 flowing through the input terminal to the output terminal.

The first end of the second resistor 214 is connected to the application end of the second internal voltage V2. The second end of the second resistor 214 is connected to the application end of the switch voltage SW (more precisely, the low-level component of the switch voltage SW). The second resistor 214 connected in this manner functions as a current/voltage conversion element that converts the first internal current I1 flowing through it into the second internal voltage V2 (=I1×Ry+SW). Therefore, the second internal voltage V2 becomes higher as the output duty Don increases, and becomes lower as the output duty Don decreases.

The low-level component of the switch voltage SW varies according to the bottom value IL_btm of the inductor current IL. Therefore, the second internal voltage V2, which includes the low-level component of the switch voltage SW, is given an offset ΔVofs according to the bottom value IL_btm of the inductor current IL.

The sample/hold circuit 215 samples/holds the second internal voltage V2 as a reference voltage VTONLLM. Therefore, the reference voltage VTONLLM becomes higher as the output duty Don increases, and becomes lower as the output duty Don decreases. The reference voltage VTONLLM is also given an offset ΔVofs according to the bottom value IL_btm of the inductor current IL. The sample/hold circuit 215 may perform the sample/hold operation in synchronization with, for example, the set signal SET.

The adjustment circuit 216 adjusts the resistance value Rx of the first resistor 212 according to the detection result of the zero-cross detection circuit 60. In this figure, the adjustment circuit 216 includes logic 216a and an up-down counter 216b.

The logic 216a receives the zero-cross detection signal ZX, the control state signal PWMCTL, and the upper control signal HGCTL, and outputs the up signal UPCODE and the counter clock signal CNTCLK. The up signal UPCODE goes high when the resistance value Rx of the first resistor 212 is increased. On the other hand, the up signal UPCODE goes low when the resistance value Rx of the first resistor 212 is decreased. The operation of the logic 216a will be described in detail later.

Up/down counter 216b receives an up signal UPCODE and a counter clock signal CNTCLK, and outputs an adjustment code VTONCODE. For example, the adjustment code VTONCODE is incremented by one when the up signal UPCODE is at a high level at the rising edge of the counter clock signal CNTCLK. Also, for example, the adjustment code VTONCODE is decremented by one when the up signal UPCODE is at a low level at the rising edge of the counter clock signal CNTCLK.

The resistance value Rx of the first resistor 212 is adjusted according to the adjustment code VTONCODE. For example, the resistance value Rx increases as the adjustment code VTONCODE increases, and decreases as the adjustment code VTONCODE decreases.

Figure 14 is a diagram showing a light load control waveform (intermittent) in the second embodiment. In this figure, from the top, the output voltage Vo, feedback voltage FB, switch voltage SW, inductor current IL, zero cross detection signal ZX, feedback voltage detection signal FBDET, set signal SET, second ramp voltage VRAMPLLM, second reset signal XRSTLLM, first ramp voltage VRAMPPWM, first reset signal XRSTPWM, reset signal XRST, control state signal PWMCTL, adjustment detection signal ILDET, up signal UPCODE, counter clock signal CNTCLK, and adjustment code VTONCODE are depicted.

The adjustment detection signal ILDET is understood to be an internal signal of logic 216a. The adjustment detection signal ILDET becomes high level when the zero-cross detection signal ZX rises to a high level in the automatic adjustment detection section T (details will be described later). On the other hand, the adjustment detection signal ILDET becomes low level if the zero-cross detection signal ZX does not rise to a high level in the automatic adjustment detection section T.

The automatic adjustment detection section T is set at the first on of intermittent drive in the light load control state (PWMCTL=L, XRSTLLM=XRST). In accordance with this diagram, the start point of the automatic adjustment detection section T can be set to the timing when the feedback voltage detection signal FBDET falls to a low level (see times t1 and t4). The end point of the automatic adjustment detection section T can be set to the timing when the first cycle ends after the switching drive of the output stage 2 is started (see times t2 and t5). For example, the end point of the automatic adjustment detection section T can be set to the timing of the second rising edge of the upper control signal HGCTL.

As shown from time t1 to t2, if the zero-cross detection signal ZX does not rise to a high level in the automatic adjustment detection section T, the adjustment detection signal ILDET is maintained at a low level. In the light load control state, when the adjustment detection signal ILDET is at a low level, the mask (or stop) of the counter clock signal CNTCLK is released. In the light load control state, the up signal UPCODE is fixed at a low level.

Therefore, as shown at time t3, when the counter clock signal CNTCLK rises to high level in synchronization with the end timing of intermittent driving, the adjustment code VTONCODE is decremented by one (N → N-1) because the up signal UPCODE is at low level. In other words, the reference voltage VTONLLM is lowered by one step. As a result, the next time intermittent driving is resumed, the intersection timing between the reference voltage VTONLLM and the second ramp voltage VRAMPLLM is advanced. Therefore, the second on-time Ton2 is shortened.

On the other hand, as shown at times t4 to t5, when the zero-crossing detection signal ZX rises to a high level in the automatic adjustment detection section T, the adjustment detection signal ILDET is raised to a high level. As a result, the counter clock signal CNTCLK is masked (or stopped).

Therefore, as shown at time t6, the counter clock signal CNTCLK does not rise to a high level at the end of intermittent driving, and the adjustment code VTONCODE is maintained at its previous value (N→N). In other words, the reference voltage VTONLLM is not lowered. As a result, the next time intermittent driving is resumed, the intersection timing between the reference voltage VTONLLM and the second ramp voltage VRAMPLLM is not advanced. Therefore, the second on-time Ton2 is maintained.

Note that, when we look at the reference voltage VTONLLM, VTONLLM is set to [N] from time t1 to t3. On the other hand, VTONLLM is set to [N-1] from time t3 to t6. [N] and [N-1] can be understood as voltage values corresponding to VTONCODE = N and N-1, respectively.

Furthermore, looking at the offset ΔVofs, ΔVofs is set to 0 before time t2, from time t3 to t5, and from time t6 onwards. On the other hand, from time t2 to t3, a negative offset ΔVofs(-) is applied because the bottom value IL_btm of the inductor current IL is positive. Moreover, from time t5 to t6, a positive offset ΔVofs(+) is applied because the bottom value IL_btm of the inductor current IL is negative.

In this way, in the light load control state, if the zero crossing of the inductor current IL is not detected in the automatic adjustment detection section T, the second on-time Ton2 is shortened. On the other hand, if the zero crossing of the inductor current IL is detected in the automatic adjustment detection section T, the second on-time setting circuit 20 maintains the second on-time Ton2.

Figure 15 is a diagram showing the control switching load waveform in the second embodiment. In this figure, similar to the above-mentioned Figure 14, from the top, the output voltage Vo, feedback voltage FB, switch voltage SW, inductor current IL, zero-cross detection signal ZX, feedback voltage detection signal FBDET, set signal SET, second ramp voltage VRAMPLLM, second reset signal XRSTLLM, first ramp voltage VRAMPPWM, first reset signal XRSTPWM, reset signal XRST, control state signal PWMCTL, adjustment detection signal ILDET, up signal UPCODE, counter clock signal CNTCLK, and adjustment code VTONCODE are depicted.

As shown in this diagram, in the heavy load control state from time t11 to t15 (PWMCTL = H, XRSTPWM = XRST), when the zero-cross detection signal ZX rises to a high level at time t12, the adjustment detection signal ILDET is raised to a high level. Also, at time t13, the up signal UPCODE is raised to a high level. Note that in the heavy load control state, unlike the light load control state described above, the counter clock signal CNTCLK is generated when the adjustment detection signal ILDET is at a high level.

Therefore, when the counter clock signal CNTCLK is raised to a high level at time t14, the adjustment code VTONCODE is incremented by one (N → N + 1) because the up signal UPCODE is at a high level. In other words, the reference voltage VTONLLM is raised by one step. As a result, the timing at which the reference voltage VTONLLM and the second ramp voltage VRAMPLLM intersect is delayed. Therefore, the second on-time Ton2 is extended.

On the other hand, if the zero-cross detection signal ZX does not rise to a high level in a heavy load control state, the counter clock signal CNTCLK is not generated. Therefore, the adjustment code VTONCODE is maintained at its previous value. In other words, the reference voltage VTONLLM is not raised. As a result, the timing of the intersection of the reference voltage VTONLLM and the second ramp voltage VRAMPLLM is not delayed. Therefore, the second on-time Ton2 is maintained.

In this way, in the heavy load control state, if a zero crossing of the inductor current IL is detected, the second on-time Ton2 is extended. On the other hand, if a zero crossing of the inductor current IL is not detected, the second on-time Ton2 is maintained.

According to the series of controls shown in Figures 14 and 15, the reference voltage VTONLLM is automatically adjusted so that the bottom value IL_btm of the inductor current IL becomes 0. Therefore, even if there are many parameter elements that determine the switching current between the light load control state and the heavy load control state, the variation in the switching current can be reduced.

The zero-cross detection circuit 60 (particularly the comparator used therein) may be configured to be able to cancel offset voltages due to manufacturing. An appropriate offset voltage may be applied to the zero-cross detection circuit 60 so that the circuit delays of the zero-cross detection circuit 60 itself and the output stage 2 are offset. The offset voltage of the zero-cross detection circuit 60 may be configured to be intentionally switched so that the switching current between the light load control state and the heavy load control state has hysteresis.

Figure 16 is a diagram showing a modified example of the second on-time setting circuit 20. The second on-time setting circuit 20 of this modified example includes a four-input comparator 23' instead of the two-input comparator 23. In addition, in the second on-time setting circuit 20 of this modified example, the switch voltage SW is not input to the reference voltage generating circuit 21, but is input to a newly provided sample/hold circuit 24. In other words, the second end of the second resistor 214 shown in Figure 13 above may be connected to the ground end instead of the application end of the switch voltage SW.

The comparator 23' compares a first sum signal (=VTONLLM+SWHLD) obtained by adding together the reference voltage VTONLLM and the holding switch voltage SWHLD input to the two non-inverting input terminals (+) with a second sum signal (=VRAMPLLM+GNDHLD) obtained by adding together the second ramp voltage VRAMPLLM and the holding ground voltage GNDHLD input to the two inverting input terminals (-) to generate a second reset signal XRSTLLM.

The sample/hold circuit 24 outputs a held switch voltage SWHLD and a held ground voltage GNDHLD (=ground voltage GND) by sampling and holding the switch voltage SW (=low-level component) when the synchronous rectifier transistor M2 is in the on state. The low-level component of the switch voltage SW includes current feedback information corresponding to the bottom value IL_btm of the inductor current IL.

That is, in the second on-time setting circuit 20 of this modified example, current feedback information is added to the difference information between the reference voltage VTONLLM and the second ramp voltage VRAMPLLM via the four-input comparator 23'. In other words, the second on-time setting circuit 20 of this modified example applies an offset ΔVofs to the input signal (=VTONLLM-VRAMLLM) of the comparator 23' according to the bottom value IL_btm of the inductor current IL.

According to this configuration, the amount of current feedback can be arbitrarily adjusted according to the input gain of the comparator 23'. For example, when the on-resistance value of the synchronous rectifier transistor M2 is small and the current feedback information contained in the low-level component of the switch voltage SW is small, the input gain of the comparator 23' can be increased.

As shown in this figure, the charging current IONLLM of the capacitor 222 generated by the current source 221 may be proportional to the input voltage Vi.

<Additional Notes>
The above disclosure will be summarized below.

The power supply control device according to the present disclosure is configured to control the output stage of a switching power supply that generates an output voltage from an input voltage, and includes a first on-time setting circuit configured to set a first on-time according to the difference between a feedback voltage corresponding to the output voltage and a predetermined reference voltage, a second on-time setting circuit configured to set a second on-time according to the output duty of the output stage, a control drive circuit configured to drive the output stage at a predetermined switching frequency with the longer of the first on-time and the second on-time as the on-time of the output stage, and a zero-cross detection circuit configured to detect zero-crossing of an inductor current flowing through the output stage, and the second on-time setting circuit is configured to adjust the second on-time according to the detection result of the zero-cross detection circuit (first configuration).

In addition, in the power supply control device according to the first configuration, the second on-time setting circuit may be configured (second configuration) to adjust the second on-time so that the bottom value of the inductor current becomes zero.

In the power supply control device according to the second configuration, the control drive circuit may be configured to perform intermittent drive of the output stage (third configuration) so as to stop driving the output stage when a zero crossing of the inductor current is detected after the feedback voltage exceeds the upper threshold voltage, and resume driving the output stage when the feedback voltage falls below the lower threshold voltage.

In the power supply control device according to the third configuration, the second on-time setting circuit may be configured (fourth configuration) to maintain the second on-time if the zero cross is detected in the detection section set when the intermittent drive is initially turned on when the second on-time is longer than the first on-time, and to shorten the second on-time if the zero cross is not detected in the detection section.

In the power supply control device according to the fourth configuration, the second on-time setting circuit may be configured (fifth configuration) to extend the second on-time if the zero cross is detected when the second on-time is shorter than the first on-time, and to maintain the second on-time if the zero cross is not detected.

In the power supply control device according to the fifth configuration, the second on-time setting circuit may include a reference voltage generating circuit configured to generate a reference voltage corresponding to the output duty of the output stage, a ramp voltage generating circuit configured to generate a ramp voltage, and a comparator configured to set the intersection timing of the reference voltage and the ramp voltage as the end timing of the second on-time, and the reference voltage generating circuit may be configured to lower the reference voltage when the second on-time is shortened and to raise the reference voltage when the second on-time is extended (sixth configuration).

In the power supply control device according to the sixth configuration, the reference voltage generation circuit may be configured (seventh configuration) to include a first internal voltage generation circuit configured to generate a first internal voltage according to the output duty of the output stage, a first resistor configured to convert the first internal voltage into a first internal current, a second resistor configured to convert the first internal current into a second internal voltage, a sample/hold circuit configured to sample/hold the second internal voltage as the reference voltage, and an adjustment circuit configured to adjust the resistance value of the first resistor according to the detection result of the zero-cross detection circuit.

In the power supply control device according to the seventh configuration, the reference voltage generating circuit may be configured (eighth configuration) to provide an offset to the second internal voltage depending on the bottom value of the inductor current.

In the power supply control device according to the seventh configuration, the second on-time setting circuit may be configured (ninth configuration) to apply an offset to the input signal of the comparator depending on the bottom value of the inductor current.

For example, the switching power supply according to the present disclosure has a configuration (tenth configuration) including a power supply control device having any one of the first to ninth configurations described above and the output stage controlled by the power supply control device.

This disclosure makes it possible to switch control states with high precision depending on the load.

＜Other＞
In addition to the above-mentioned embodiment, various technical features of the present disclosure can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects. In addition, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope of the claims.

REFERENCE SIGNS LIST 1 Power supply control device 2 Output stage 10 First on-time setting circuit 11 Error voltage generating circuit 12 Ramp voltage generating circuit 121 Current source 122 Capacitor 123 Transistor (NMOSFET)
13 Adder circuit 14 Comparator 20 Second on-time setting circuit 21 Reference voltage generating circuit 211 First internal voltage generating circuit 211a Voltage dividing/smoothing circuit 211b Operational amplifier 211c Transistor (NMOSFET)
212 First resistor 213 Current mirror 213a, 213b Transistor (PMOSFET)
214 Second resistor 215 Sample/hold circuit 216 Adjustment circuit 216a Logic 216b Up/down counter 22 Ramp voltage generating circuit 221 Current source 222 Capacitor 223 Transistor (NMOSFET)
23, 23' Comparator 24 Sample/hold circuit 30 Oscillator 40 OR gate 50 Control drive circuit 60 Zero cross detection circuit 70 Feedback voltage detection circuit 71 Comparator 72 Selector A Switching power supply C1 Capacitor L1 Inductor M1 Output transistor (PMOSFET)
M2 Synchronous rectifier transistor (NMOSFET)
R1, R2 Resistor

Claims (10)

A power supply control device configured to control an output stage of a switching power supply that generates an output voltage from an input voltage,
a first on-time setting circuit configured to set a first on-time in response to a difference between a feedback voltage corresponding to the output voltage and a predetermined reference voltage;
a second on-time setting circuit configured to set a second on-time in response to an output duty of the output stage;
a control drive circuit configured to drive the output stage at a predetermined switching frequency, the control drive circuit setting the longer of the first on-time and the second on-time as an on-time of the output stage;
a zero-crossing detection circuit configured to detect a zero-crossing of an inductor current flowing through the output stage;
Equipped with
The second on-time setting circuit adjusts the second on-time in response to a detection result of the zero-cross detection circuit. The power supply control device according to claim 1, wherein the second on-time setting circuit adjusts the second on-time so that the bottom value of the inductor current becomes zero. The power supply control device according to claim 2, wherein the control drive circuit performs intermittent drive of the output stage such that the drive of the output stage is stopped when a zero cross of the inductor current is detected after the feedback voltage exceeds an upper threshold voltage, and the drive of the output stage is resumed when the feedback voltage falls below a lower threshold voltage. The power supply control device according to claim 3, wherein, when the second on-time is longer than the first on-time, the second on-time setting circuit maintains the second on-time if the zero cross is detected in the detection section set at the first on-time of the intermittent drive, and shortens the second on-time if the zero cross is not detected in the detection section. The power supply control device according to claim 4, wherein the second on-time setting circuit extends the second on-time if the zero crossing is detected when the second on-time is shorter than the first on-time, and maintains the second on-time if the zero crossing is not detected. The second on-time setting circuit includes:
a reference voltage generating circuit configured to generate a reference voltage according to an output duty of the output stage;
a ramp voltage generating circuit configured to generate a ramp voltage;
a comparator configured to set a crossing timing of the reference voltage and the ramp voltage as an end timing of the second on-time;
Including,
6. The power supply control device according to claim 5, wherein the reference voltage generating circuit reduces the reference voltage when the second on-time is shortened, and increases the reference voltage when the second on-time is extended. The reference voltage generating circuit includes:
a first internal voltage generating circuit configured to generate a first internal voltage according to an output duty of the output stage;
a first resistor configured to convert the first internal voltage into a first internal current;
a second resistor configured to convert the first internal current to a second internal voltage;
a sample/hold circuit configured to sample/hold the second internal voltage as the reference voltage;
an adjustment circuit configured to adjust a resistance value of the first resistor in response to a detection result of the zero-crossing detection circuit;
The power control device of claim 6 . The power supply control device according to claim 7, wherein the reference voltage generating circuit applies an offset to the second internal voltage according to the bottom value of the inductor current. The power supply control device according to claim 7, wherein the second on-time setting circuit applies an offset to the input signal of the comparator according to the bottom value of the inductor current. A power supply control device according to any one of claims 1 to 9,
the output stage controlled by the power supply controller;
A switching power supply comprising:

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