JP2025007974A - Sensor element and distance measurement system - Google Patents

Abstract

To achieve higher functionality while maintaining a pixel size.SOLUTION: A sensor element disclosed herein includes: a sensor substrate in which a SPAD is provided for each pixel; a CMOS substrate that is superposed on the sensor substrate and is provided with a transistor for reading a signal; a logic substrate which is superposed on the CMOS substrate and on which a logic circuit is provided; and a through electrode that passes through the CMOS substrate and electrically connects an anode region of the sensor substrate and the CMOS substrate. The present disclosure can be applied to a CMOS image sensor, for example.SELECTED DRAWING: Figure 3

Description

This disclosure relates to a sensor element and a ranging system, and in particular to a sensor element and a ranging system that enable further enhancement of functionality while maintaining pixel size.

A range image sensor that measures distances using the ToF (Time-of-Flight) method is known. Range image sensors use, for example, a pixel array in which pixels using SPADs (Single Photon Avalanche Diodes) are arranged in a matrix. In a SPAD, when a voltage greater than the breakdown voltage is applied and a single photon enters a PN junction region with a high electric field, avalanche amplification occurs. By detecting the timing at which the current flows at this time, it is possible to measure distances with high precision.

Conventionally, distance measurement systems using SPADs have adopted a back-illuminated sensor element in which light is irradiated from the back side of the semiconductor substrate, with a layered structure in which a sensor substrate on which a SPAD is mounted and a logic substrate on which a logic circuit is mounted are bonded together.

Patent Document 1 proposes that in order to reduce the size and improve the functionality of a sensor element with a stacked structure, some of the multiple transistors that output a signal according to the cathode voltage or anode voltage of the SPAD are provided in a well formed in the semiconductor substrate of the sensor board.

JP 2022-148028 A

In recent years, there has been a demand for even higher functionality in logic circuits in stacked sensor elements. However, in a two-layer sensor element such as that disclosed in Patent Document 1, it is not easy to add an SRAM (Static Random Access Memory) for calculations in the logic circuit while maintaining the pixel size.

This disclosure was made in light of these circumstances, and aims to enable even greater functionality while maintaining pixel size.

The sensor element of the present disclosure is a sensor element including a sensor substrate on which a single photon avalanche diode (SPAD) is provided for each pixel, a complementary metal oxide semiconductor (CMOS) substrate laminated on the sensor substrate and provided with transistors for signal readout, a logic substrate laminated on the CMOS substrate and provided with a logic circuit, and a through electrode that penetrates the CMOS substrate and electrically connects the anode region of the sensor substrate to the CMOS substrate.

The distance measurement system disclosed herein includes an illumination device that emits irradiation light and a sensor element that detects reflected light from the irradiation light. The sensor element is a distance measurement system having a sensor substrate on which a single photon avalanche diode (SPAD) is provided for each pixel, a complementary metal oxide semiconductor (CMOS) substrate that is stacked on the sensor substrate and has transistors for reading signals, a logic substrate that is stacked on the CMOS substrate and has a logic circuit, and a through electrode that penetrates the CMOS substrate and electrically connects the anode region of the sensor substrate to the CMOS substrate.

In the present disclosure, a sensor substrate on which a SPAD is provided for each pixel, a CMOS substrate laminated on the sensor substrate and provided with transistors for signal readout, a logic substrate laminated on the CMOS substrate and provided with a logic circuit, and a through electrode penetrating the CMOS substrate and electrically connecting the anode region of the sensor substrate to the CMOS substrate are provided.

1 is a cross-sectional view showing a configuration example of a sensor element to which the technology according to the present disclosure is applied. FIG. 2 is a cross-sectional view showing a configuration example of a CMOS substrate. FIG. 2 is a plan view showing a configuration example of a CMOS substrate. FIG. 2 is a plan view showing a configuration example of a CMOS substrate according to the first embodiment; FIG. 4 is a plan view showing another configuration example of the CMOS substrate according to the first embodiment. FIG. 11 is a cross-sectional view showing a configuration example of a CMOS substrate according to a second embodiment. FIG. 13 is a plan view showing a configuration example of a CMOS substrate according to a second embodiment. FIG. 13 is a plan view showing another configuration example of the CMOS substrate according to the second embodiment. FIG. 13 is a cross-sectional view showing a configuration example of a CMOS substrate according to a third embodiment. FIG. 13 is a plan view showing a configuration example of a CMOS substrate according to a third embodiment. FIG. 1 is a block diagram showing an example of the configuration of a distance measuring system.

Below, we will explain the form for implementing this disclosure (hereinafter, referred to as the embodiment). The explanation will be given in the following order.

1. Prior art and problems thereof 2. Configuration example of a sensor element to which the technology according to the present disclosure is applied 3. First embodiment (configuration in which source region/drain region are used as shield region)
4. Second embodiment (structure in which well region of substrate contact is used as shield region)
5. Third embodiment (air gap as shield region)
6. Example of distance measurement system configuration

1. Conventional technology and its problems
Conventionally, distance measurement systems using SPADs (Single Photon Avalanche Diodes) have adopted a back-illuminated sensor element in which a sensor substrate having a SPAD and a logic substrate having a logic circuit are bonded together, and light is irradiated from the back side of the semiconductor substrate.

Patent Document 1 (JP Patent Publication No. 2022-148028) proposes that in order to achieve miniaturization and high functionality in a sensor element with a stacked structure, some of the multiple transistors for outputting a signal according to the cathode voltage or anode voltage of the SPAD are provided in a well formed in the semiconductor substrate of the sensor substrate.

In recent years, there has been a demand for even higher functionality in logic circuits in stacked sensor elements. However, in a two-layer sensor element such as that disclosed in Patent Document 1, it is not easy to add an SRAM (Static Random Access Memory) for calculations in the logic circuit while maintaining the pixel size.

Therefore, in the technology disclosed herein, a complementary metal oxide semiconductor (CMOS) substrate on which transistors for reading signals are provided is stacked between a sensor substrate on which a SPAD is provided for each pixel and a logic substrate on which a logic circuit is provided, thereby ensuring the area for the logic circuit.

However, in such a three-layered sensor element, a high voltage of -20 to -25 V is applied to the anode electrode that penetrates the CMOS substrate, which raises concerns about the effect on the ON-OFF characteristics of the transistors provided on the CMOS substrate.

In response to this, International Publication No. 2020/262558 (referred to as Publicly Known Example 2) discloses an imaging device in which a shield electrode is provided between a through electrode that electrically connects a floating diffusion of a first substrate and a pixel circuit of a second substrate, and each transistor that constitutes the pixel circuit. The shield electrode is intended to reduce the effect of a bias applied to the through wiring on each transistor that constitutes the pixel circuit.

However, in known example 2, the reduction of pixel size was not taken into consideration, and there were issues in terms of area efficiency.

Therefore, in the technology disclosed herein, in a plan view from the stacking direction, existing components of the CMOS substrate are arranged as a shielding region between the transistor and the through electrode in the CMOS substrate, thereby realizing the maintenance of pixel size without providing a new component such as a shield electrode.

2. Configuration example of sensor element to which the technology according to the present disclosure is applied
The configuration of a sensor element to which the technology according to the present disclosure is applied will be described with reference to FIGS. 1 to 3. FIG.

Figure 1 shows an example of a cross-sectional configuration of a pixel 10 in a sensor element 1 to which the technology disclosed herein is applied.

The sensor element 1 is configured as, for example, a CMOS image sensor. As shown in FIG. 1, the sensor element 1 has a three-layer structure consisting of a sensor substrate 11 on which a SPAD 31 is provided for each pixel 10, a CMOS substrate 12 on which a transistor for reading out a signal is provided and laminated on the sensor substrate 11, and a logic substrate 13 on which a logic circuit is provided and laminated on the CMOS substrate 12. The sensor substrate 11 is configured by laminating an on-chip lens layer 22 on the upper surface (rear surface) of a semiconductor substrate 21. The logic substrate 13 is configured by laminating a wiring layer 24 on the upper surface of a semiconductor substrate 23. The on-chip lens layer 22 is provided with a microlens 25 for each pixel 10.

The pixel 10 is configured such that the well layer 32 of the semiconductor substrate 21 is electrically isolated from the well layers 32 of other adjacent pixels 10 by a pixel isolation portion 33. Although not shown, the pixel 10 is provided with a P-type semiconductor region for accumulating holes, surrounding the side and top surfaces of the well layer 32. An anode region 34 with a higher P-type impurity concentration than the P-type semiconductor region is formed on the underside of the semiconductor substrate 21 corresponding to the region in which the P-type semiconductor region is formed.

In pixel 10, on the underside of semiconductor substrate 21, SPAD 31 is formed by a PN junction region of an N-type multiplication region and a P-type multiplication region. SPAD 31 is a photodiode in which the cathode potential drops due to a current that flows as a result of avalanche amplification of electrons that are generated in response to light incident on pixel 10. In addition, in SPAD 31, a cathode region 35 with a high N-type impurity concentration, which has a higher impurity concentration than the N-type multiplication region, is formed in the N-type multiplication region that forms the PN junction.

Transistors 50 and 60 are provided on the CMOS substrate 12 for reading out a signal according to the cathode voltage of SPAD 31. Transistors 50 and 60 are composed of transistors of different conduction types. One of transistors 50 and 60 may be composed of a PMOS transistor, and the other of transistors 50 and 60 may be composed of an NMOS transistor.

For example, when transistor 50 is a PMOS transistor, gate electrode 53 is provided between source region 51 and drain region 52, which are P-type regions provided for an N-well, with an insulating film such as an oxide film interposed between them. Similarly, when transistor 60 is an NMOS transistor, gate electrode 63 is provided between source region 61 and drain region 62, which are N-type regions provided for a P-well, with an insulating film such as an oxide film interposed between them.

Transistor 50 and transistor 60 are assumed to be configured as planar structure transistors, but are not limited to this and may also be configured as trench structure transistors.

The CMOS substrate 12 is provided with through electrodes 71 and 72 that penetrate the CMOS substrate 12 and electrically connect the sensor substrate 11 and the CMOS substrate 12.

The through electrode 71 is formed as an anode electrode that connects the anode region 34 formed in the sensor substrate 11 and each transistor provided in the CMOS substrate 12 via a SPAD circuit (not shown) formed in the logic substrate 13. The through electrode 72 is formed as a cathode electrode that connects the cathode region 35 formed in the N-type multiplication region of the SPAD 31 and each transistor provided in the CMOS substrate 12 via a SPAD circuit (not shown) formed in the logic substrate 13.

As described above, by stacking the CMOS substrate 12, on which the transistors 50 and 60 for reading signals are provided, between the sensor substrate 11, on which the SPAD 31 is provided for each pixel 10, and the logic substrate 13, on which the logic circuit is provided, it is possible to secure the area for the logic circuit. In other words, while maintaining the pixel size, it is possible to add SRAM and the like for calculations in the logic circuit, thereby enabling the sensor element 1 to achieve even higher functionality.

The detailed configuration of the CMOS substrate 12 will be described with reference to Figure 2.

Figure 2 shows a cross section of a portion of the CMOS substrate 12 where the transistor 50 is provided. Note that the cross-sectional configuration shown in Figure 2 is the cross-sectional configuration shown in Figure 1 flipped upside down.

In the CMOS substrate 12, an element isolation region 81 is formed between the transistor 50 and the through electrode 71. The element isolation region 81 is formed, for example, as an STI (Shallow Trench Isolation) region with a depth of about 250 nm formed of an insulating film such as a silicon oxide film, or a DTI (Deep Trench Isolation) region formed of a silicon oxide film or the like that penetrates from the silicon surface to the bottom surface of the CMOS substrate 12, but may also be formed by ion implantation.

In addition, an element isolation region 82 is formed between the transistors 50 and 60 (not shown) of different conductivity types. The element isolation region 82 is formed, for example, as a DTI region formed of a Si oxide film that penetrates from the Si surface to the bottom surface of the CMOS substrate 12, but may also be formed by ion implantation.

Now, a voltage with an absolute value of 20 V or more is applied to the through electrode 71 connected to the anode region 34. Specifically, a high voltage of -20 to -25 V is applied to the through electrode 71. Therefore, there are concerns about the effect on the ON-OFF characteristics of each transistor provided on the CMOS substrate 12.

Therefore, as shown in FIG. 3, in the CMOS substrate 12, existing components of the CMOS substrate 12 are arranged as a shield region 100 between the transistor 50 and the through electrode 71 when viewed in a plan view from the stacking direction.

The shield region 100 is arranged so as to intersect with all line segments connecting the vertices of the overlap region OL, where the active region in which the source region 51/drain region 52 of the transistor 50 is formed and the gate electrode 53 overlap, and the center of the through electrode 71 (the center of gravity on the two-dimensional figure), in a plan view from the stacking direction. The two-dimensional shape of the overlap region OL, where the active region of the transistor 50 and the gate electrode 53 overlap, is shown as a rectangle in the example of FIG. 3, but in reality it will be a polygonal shape other than a rectangle.

As described above, by arranging the existing components of the CMOS substrate 12 as the shield region 100, it is possible to maintain high reliability of the transistor 50 provided on the CMOS substrate 12, i.e., to reduce the effect on the transistor 50 caused by the application of a high voltage to the through electrode 71. In addition, it is possible to maintain the pixel size without providing a new member such as the shield electrode of the known example 2.

Below, we will explain specific examples of existing components of the CMOS substrate 12 that are arranged as the shield region 100.

3. First embodiment
FIG. 4 is a plan view showing a configuration example of the CMOS substrate 12 according to the first embodiment to which the technology disclosed herein is applied.

The cross-sectional configuration of the CMOS substrate 12 in this embodiment is similar to that shown in FIG. 2, so its description is omitted.

In the example of FIG. 4, in the CMOS substrate 12, the drain region 52 of the active region of the transistor 50 is disposed as a shield region 100 between the transistor 50 and the through electrode 71 in a plan view from the stacking direction.

The drain region 52 is arranged so as to intersect with all the line segments connecting the vertices of the overlapping region where the active region of the transistor 50 and the gate electrode 53 overlap with the center of the through electrode 71 when viewed in a plan view from the stacking direction. This allows the effect of the electric field propagating from the through electrode 71 to be absorbed by the drain region 52.

As described above, by arranging the active region of the transistor 50 between the transistor 50 and the through electrode 71, it is possible to maintain the pixel size while reducing the effect on the transistor 50 of the application of a high voltage to the through electrode 71.

In the example of FIG. 4, the drain region 52 of the active region of the transistor 50 is disposed between the transistor 50 and the through electrode 71, but the source region 51 of the active region of the transistor 50 may be disposed therebetween.

The shape of the active region of the transistor 50 in plan view is not limited to that shown in FIG. 4. That is, for example, the drain region 52 may be arranged so as to intersect with all the line segments connecting the vertices of the overlapping region where the active region of the transistor 50 and the gate electrode 53 overlap with each other in plan view from the stacking direction, and may have any shape depending on the positional relationship between the transistor 50 and the through electrode 71.

For example, as shown in FIG. 5A, if the through electrode 71 is not provided on the longitudinal extension of the active region of the transistor 50, the drain region 52 (or the source region 51) may be formed in an L-shape.

Also, as shown in FIG. B, when two through electrodes 71a and 71b are provided, the drain region 52 (or the source region 51) may be formed in a U-shape depending on their arrangement.

In the example of FIG. 5, the active region of the transistor 50 is also disposed between the transistor 50 and the through electrode 71, so it is possible to maintain the pixel size while reducing the effect on the transistor 50 of the application of a high voltage to the through electrode 71.

4. Second embodiment
FIG. 6 is a cross-sectional view showing an example of the configuration of a CMOS substrate 12 according to a second embodiment to which the technology disclosed herein is applied, and FIG. 7 is a plan view thereof.

In the cross-sectional configuration shown in FIG. 6, in addition to the cross-sectional configuration shown in FIG. 2, a substrate contact 121 and its well region 122 are formed. The well region 122 is an N-type or P-type diffusion layer for the substrate contact, and is fixed to a constant potential by the substrate contact 121.

In the example of FIG. 7, in the CMOS substrate 12, a well region 122 of a substrate contact 121 is disposed as a shield region 100 between the transistor 50 and the through electrode 71 when viewed in a plan view from the stacking direction.

The well region 122 of the substrate contact 121 is arranged so as to intersect with all the line segments connecting the vertices of the overlapping region where the active region of the transistor 50 and the gate electrode 53 overlap with the center of the through electrode 71 when viewed in a plan view from the stacking direction. This allows the effect of the electric field propagating from the through electrode 71 to be absorbed by the well region 122 of the substrate contact 121.

As described above, by arranging the well region 122 of the substrate contact 121 between the transistor 50 and the through electrode 71, it is possible to maintain the pixel size while reducing the effect on the transistor 50 caused by the application of a high voltage to the through electrode 71.

The shape of the well region 122 of the substrate contact 121 in plan view is not limited to that shown in FIG. 7. In other words, the well region 122 of the substrate contact 121 only needs to be arranged so as to intersect with all the line segments connecting the vertices of the overlapping region where the active region of the transistor 50 and the gate electrode 53 overlap with each other and the center of the through electrode 71 in plan view from the stacking direction, and can have any shape depending on the positional relationship between the transistor 50 and the through electrode 71.

For example, as shown in FIG. 8, the well region 122 of the substrate contact 121 may be formed in an L-shape depending on the arrangement of the through electrode 71.

In the example of FIG. 8, the well region 122 of the substrate contact 121 is also disposed between the transistor 50 and the through electrode 71, so that it is possible to maintain the pixel size while reducing the effect on the transistor 50 of the application of a high voltage to the through electrode 71.

5. Third embodiment
FIG. 9 is a cross-sectional view showing an example of the configuration of a CMOS substrate 12 according to a third embodiment to which the technology disclosed herein is applied, and FIG. 10 is a plan view thereof.

In the cross-sectional configuration shown in FIG. 9, an air gap 131 is formed in addition to the cross-sectional configuration shown in FIG. 2. The air gap 131 is formed, for example, by a vacuum cavity.

In the example of FIG. 10, air gaps 131 are arranged as shielding regions 100 between the transistor 50 and each of the two through electrodes 71a and 71b in a plan view from the stacking direction in the CMOS substrate 12.

The air gap 131 is arranged so as to intersect with all the line segments connecting the vertices of the overlapping region where the active region of the transistor 50 and the gate electrode 53 overlap with the center of each of the through electrodes 71a and 71b when viewed in a plan view from the stacking direction. This allows the electric field from each of the through electrodes 71a and 71b to propagate while avoiding the air gap 131, which has a low dielectric constant.

According to the above configuration, by disposing an air gap 131 between the transistor 50 and each of the through electrodes 71a and 71b, it is possible to maintain the pixel size while reducing the effect on the transistor 50 caused by the application of a high voltage to the through electrode 71.

The shape of the air gap 131 in plan view is not limited to that shown in FIG. 10. In other words, the air gap 131 only needs to be arranged so as to intersect with all the line segments connecting the vertices of the overlapping region where the active region of the transistor 50 and the gate electrode 53 overlap with the center of the through electrode 71 (71a, 71b) in plan view from the stacking direction, and can have any shape depending on the positional relationship between the transistor 50 and the through electrode 71.

6. Example of distance measurement system configuration
The sensor element 1 of each of the above-described embodiments can be applied to a ranging system that uses the ToF method to detect the depth distance to a subject for each pixel and captures a distance image, which is an image composed of distance pixel signals based on the detected distance.

Figure 11 is a block diagram showing an example configuration of one embodiment of a distance measurement system 211 to which the technology disclosed herein is applied.

As shown in FIG. 11, the distance measurement system 211 includes an illumination device 221 and an imaging device 222.

The lighting device 221 includes a lighting control unit 231 and a light source 232.

The illumination control unit 231 controls the pattern in which the light source 232 emits light under the control of the control unit 242 of the imaging device 222. Specifically, the illumination control unit 231 controls the pattern in which the light source 232 emits light according to an illumination code included in an illumination signal supplied from the control unit 242. For example, the illumination code is composed of two values, 1 (High) and 0 (Low), and the illumination control unit 231 turns on the light source 232 when the illumination code value is 1 and turns off the light source 232 when the illumination code value is 0.

The light source 232 emits light in a predetermined wavelength range under the control of the illumination control unit 231. The light source 232 is, for example, an infrared laser diode. The type of light source 232 and the wavelength range of the irradiated light can be set arbitrarily depending on the application of the distance measurement system 211, etc.

The imaging device 222 is a device that receives reflected light that is generated when light (illumination light) emitted from the illumination device 221 is reflected by the subject 212, the subject 213, etc. The imaging device 222 includes an imaging unit 241, a control unit 242, a display unit 243, and a storage unit 244.

The imaging unit 241 includes a lens 251, a light receiving element 252, and a signal processing circuit 253.

The lens 251 forms an image of the incident light on the light receiving surface of the light receiving element 252. The configuration of the lens 251 is arbitrary, and for example, the lens 251 can be configured with a group of multiple lenses.

The sensor element 1 to which the technology disclosed herein is applied is applied to the light receiving element 252. Under the control of the control unit 242, the light receiving element 252 receives reflected light from the subject 212, the subject 213, etc., and supplies the resulting pixel signal to the signal processing circuit 253. This pixel signal represents a digital count value that counts the time from when the illumination device 221 emits irradiation light to when the light receiving element 252 receives the light. An emission timing signal that indicates the timing at which the light source 232 emits light is also supplied from the control unit 242 to the light receiving element 252.

The signal processing circuit 253 processes the pixel signal supplied from the light receiving element 252 under the control of the control unit 242. For example, the signal processing circuit 253 detects the distance to the subject for each pixel based on the pixel signal supplied from the light receiving element 252, and generates a distance image showing the distance to the subject for each pixel. Specifically, the signal processing circuit 253 acquires the time (count value) from when the light source 232 emits light to when each pixel of the light receiving element 252 receives the light multiple times (for example, thousands to tens of thousands of times) for each pixel. The signal processing circuit 253 creates a histogram corresponding to the acquired time. Then, the signal processing circuit 253 detects the peak of the histogram to determine the time until the light irradiated from the light source 232 is reflected by the subject 212 or the subject 213 and returns. Furthermore, the signal processing circuit 253 performs a calculation to obtain the distance to the object based on the determined time and the speed of light. The signal processing circuit 253 supplies the generated distance image to the control unit 242.

The control unit 242 is composed of a control circuit or a processor such as an FPGA (Field Programmable Gate Array) or a DSP (Digital Signal Processor). The control unit 242 controls the illumination control unit 231 and the light receiving element 252. Specifically, the control unit 242 supplies an irradiation signal to the illumination control unit 231 and a light emission timing signal to the light receiving element 252. The light source 232 emits irradiation light in response to the irradiation signal. The light emission timing signal may be the irradiation signal supplied to the illumination control unit 231. The control unit 242 also causes the display unit 243 to display the distance image acquired from the imaging unit 241. Furthermore, the control unit 242 causes the storage unit 244 to store the distance image acquired from the imaging unit 241. Furthermore, the control unit 242 outputs the distance image acquired from the imaging unit 241 to the outside.

The display unit 243 is, for example, a panel-type display device such as a liquid crystal display device or an organic EL (Electro Luminescence) display device.

The memory unit 244 can be configured from any storage device or storage medium, and stores distance images, etc.

In the distance measurement system 211 configured in this manner, by applying the sensor element 1 to which the technology disclosed herein is applied, it is possible to achieve, for example, further miniaturization and higher functionality.

In this specification, a system refers to a collection of multiple components (devices, modules (parts), etc.), regardless of whether all the components are in the same housing. Thus, multiple devices housed in separate housings and connected via a network, and a single device in which multiple modules are housed in a single housing, are both systems.

The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

Furthermore, the embodiments to which the technology disclosed herein is applied are not limited to the above-described embodiments, and various modifications are possible without departing from the spirit and scope of the technology disclosed herein.

Furthermore, the present disclosure can have the following configurations.
(1)
A sensor substrate on which a single photon avalanche diode (SPAD) is provided for each pixel;
a complementary metal oxide semiconductor (CMOS) substrate that is laminated on the sensor substrate and has transistors for reading out signals;
a logic substrate laminated on the CMOS substrate and provided with a logic circuit;
a through electrode penetrating the CMOS substrate and electrically connecting the sensor substrate and the CMOS substrate.
(2)
The sensor element according to (1), wherein an existing component of the CMOS substrate is disposed as a shielding region between the transistor and the through electrode in a plan view from a stacking direction in the CMOS substrate.
(3)
The sensor element described in (2), wherein the shielding region is arranged so as to intersect with all line segments connecting the center of the through electrode to each vertex of an overlapping region where the active region and gate electrode of the transistor overlap when viewed in a planar view from the stacking direction.
(4)
The sensor element according to (3), wherein the shield region is a source region or a drain region of the active region of the transistor.
(5)
The sensor element according to claim 3, wherein the shield region is a well region of a substrate contact.
(6)
The sensor element according to claim 3, wherein the shield region is an air gap.
(7)
The sensor element according to any one of (3) to (6), wherein a voltage having an absolute value of 20 V or more is applied to the through electrode.
(8)
a first conductive type transistor and a second conductive type transistor are provided on the CMOS substrate;
The sensor element according to any one of (3) to (7), wherein an element isolation region is formed between the first conductive type transistor and the second conductive type transistor.
(9)
The sensor element according to (8), wherein the element isolation region is formed by a deep trench isolation (DTI) region penetrating the CMOS substrate from a surface to a bottom surface.
(10)
The sensor element according to (9), wherein, in the CMOS substrate, an STI (Shallow Trench Isolation) region having a depth of about 250 nm or the DTI region is further formed between the transistor and the through electrode.
(11)
An illumination device that emits irradiation light;
a sensor element for detecting reflected light of the irradiated light,
The sensor element includes:
A sensor substrate on which a single photon avalanche diode (SPAD) is provided for each pixel;
a complementary metal oxide semiconductor (CMOS) substrate that is laminated on the sensor substrate and has transistors for reading out signals;
a logic substrate laminated on the CMOS substrate and provided with a logic circuit;
a through electrode penetrating the CMOS substrate and electrically connecting the sensor substrate and the CMOS substrate.

1 sensor element, 10 pixel, 11 sensor substrate, 12 CMOS substrate, 13 logic substrate, 31 SPAD, 34 anode region, 35 cathode region, 50 transistor, 51 source region, 52 drain region, 53 gate electrode, 60 transistor, 61 source region, 62 drain region, 63 gate electrode, 71, 72 through electrode, 81, 82 element isolation region, 100 shield region, 121 substrate contact, 122 well region, 131 air gap

Claims (11)

A sensor substrate on which a single photon avalanche diode (SPAD) is provided for each pixel;
a complementary metal oxide semiconductor (CMOS) substrate that is laminated on the sensor substrate and has transistors for reading out signals;
a logic substrate laminated on the CMOS substrate and provided with a logic circuit;
a through electrode penetrating the CMOS substrate and electrically connecting the anode region of the sensor substrate to the CMOS substrate. The sensor element according to claim 1 , wherein an existing component of the CMOS substrate is disposed as a shielding region between the transistor and the through electrode in a plan view from a stacking direction in the CMOS substrate. The sensor element according to claim 2 , wherein the shielding region is arranged so as to intersect with all line segments connecting the centers of the through electrodes to the vertices of overlapping regions where the active regions and gate electrodes of the transistors overlap when viewed in a planar view from the stacking direction. The sensor element according to claim 3 , wherein the shield region is a source region or a drain region of the active area of the transistor. The sensor element according to claim 3 , wherein the shield region is a well region of a substrate contact. The sensor element according to claim 3 , wherein the shielding region is an air gap. The sensor element according to claim 3 , wherein a voltage having an absolute value of 20 V or more is applied to the through electrode. a first conductive type transistor and a second conductive type transistor are provided on the CMOS substrate;
The sensor element according to claim 3 , further comprising an element isolation region formed between the first conductive type transistor and the second conductive type transistor. The sensor element according to claim 8 , wherein the element isolation region is formed by a DTI (Deep Trench Isolation) region penetrating the CMOS substrate from a surface to a bottom surface. The sensor element according to claim 9 , wherein in the CMOS substrate, a shallow trench isolation (STI) region or the DTI region having a depth of about 250 nm is further formed between the transistor and the through electrode. An illumination device that emits irradiation light;
a sensor element for detecting reflected light of the irradiated light,
The sensor element includes:
A sensor substrate on which a single photon avalanche diode (SPAD) is provided for each pixel;
a complementary metal oxide semiconductor (CMOS) substrate that is laminated on the sensor substrate and has transistors for reading out signals;
a logic substrate laminated on the CMOS substrate and provided with a logic circuit;
a through electrode penetrating the CMOS substrate and electrically connecting an anode region of the sensor substrate to the CMOS substrate.

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