JP2025004609A - Comparison Circuit - Google Patents

Abstract

A small-scale comparison circuit with high detection accuracy is provided.
[Solution] The comparison circuit 1 includes a first transistor M1 of a depletion type, a second transistor M2 having an input signal VMON or its divided voltage signal VA applied to a control electrode, a first resistor R1 connected between the gate and source of the first transistor M1, and a second resistor R2 connected to a first main electrode of the second transistor M2 and through which a current I having the same value as the current I flowing through the first resistor R1 flows. The comparison circuit 1 outputs a node signal VB appearing at a second main electrode of the second transistor M2 or a signal VC corresponding to the node signal VB as an output signal OUT.
[Selected figure] Figure 3

Description

This disclosure relates to a comparison circuit.

Conventionally, comparison circuits that compare a monitored signal with a reference signal have been widely used.

An example of related prior art is Patent Document 1 proposed by the applicant of the present application.

JP 2021-040257 A

[overview]
However, there is room for further consideration regarding the topology of the comparison circuit.

For example, the comparison circuit according to the present disclosure includes a first depletion-type transistor, a second transistor configured to have an input signal or a divided voltage signal thereof applied to its control electrode, a first resistor configured to be connected between the gate and source of the first transistor, and a second resistor connected to a first main electrode of the second transistor and configured to pass a current equal to the current flowing through the first resistor, and outputs a node signal appearing at the second main electrode of the second transistor or a signal corresponding thereto as an output signal.

Additional features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto.

FIG. 1 is a diagram showing a comparative example of a comparison circuit. FIG. 2 is a diagram showing input/output behavior in the comparative example. FIG. 3 is a diagram showing a first embodiment of a comparison circuit. FIG. 4 is a diagram showing input/output behavior in the first embodiment. FIG. 5 is a diagram showing temperature characteristics of a detection voltage in the first embodiment. FIG. 6 is a diagram showing a second embodiment of the comparator circuit. FIG. 7 is a diagram showing input/output behavior in the second embodiment. FIG. 8 is a diagram showing a third embodiment of the comparator circuit. FIG. 9 is a diagram showing a fourth embodiment of the comparator circuit. FIG. 10 is a diagram showing a fifth embodiment of the comparison circuit.

Detailed Description
Comparative Example
1 is a diagram showing a comparative example of a comparison circuit (an example of a circuit configuration to be compared with the embodiments described later). A comparison circuit 100 of this comparative example receives an input signal VMON (corresponding to a monitored voltage) and outputs an output signal OUT.

With reference to this diagram, the comparison circuit 100 includes a transistor 110 (in this diagram, an enhancement type NMOSFET [N-channel type metal oxide semiconductor field effect transistor]), a reference voltage generation circuit 120, a divided voltage generation circuit 130, a comparator 140, and a resistor 150.

The transistor 110 is connected between the application terminal of the output signal OUT and the ground terminal (corresponding to the reference potential terminal). The transistor 110 is switched between an on state and an off state according to the drive signal SG output from the comparator 140.

The reference voltage generating circuit 120 generates a predetermined reference voltage VREF from the power supply voltage VCC. Note that a bandgap power supply that has little temperature and power supply dependency is generally used as the reference voltage generating circuit 120.

The divided voltage generation circuit 130 includes resistors 131 and 132 connected in series between the application terminal of the input signal VMON and the ground terminal, and generates a divided voltage signal VDIV (= divided voltage of the voltage to be monitored) according to the input signal VMON.

Comparator 140 compares the reference voltage VREF with the voltage division signal VDIV to generate a drive signal SG for transistor 110.

Resistor 150 is connected between the application end of the power supply voltage VCC (corresponding to the power supply potential end) and the application end of the output signal OUT.

Figure 2 is a diagram showing the input/output behavior of the comparison circuit 100 in the comparative example. The horizontal axis of this figure represents the input signal VMON. The vertical axis of this figure represents the output signal OUT.

As shown in this figure, the comparison circuit 100 of this comparative example can switch the logic level of the output signal OUT according to the comparison result between the input signal VMON and a predetermined threshold voltage Vth. The threshold voltage Vth is expressed as VREF x (R131 + R132) / R132, where R131 and R132 are the resistance values of resistors 131 and 132, respectively.

However, in the comparison circuit 100, the circuit scale of the reference voltage generation circuit 120 and the comparator 140 tends to be large. In addition, as the circuit scale increases, the factors that cause element variation also increase. As a result, there is a risk that the characteristics (detection accuracy, etc.) of the comparison circuit 100 will deteriorate.

In the following, various embodiments that adopt new topologies are proposed in light of the above considerations.

First Embodiment
3 is a diagram showing a first embodiment of a comparison circuit. Similar to the comparative example (FIG. 1) described above, the comparison circuit 1 of this embodiment receives an input signal VMON (=voltage to be monitored) and outputs an output signal OUT.

With reference to this diagram, the comparison circuit 1 includes a transistor M0 (e.g., a PMOSFET [P-channel type MOSFET]), a transistor M1 (e.g., a depletion type NMOSFET), a transistor M2 (e.g., an enhancement type NMOSFET), and resistors R0 to R4.

Note that the depletion type refers to a type in which a drain current flows even when the gate-source voltage is 0V. On the other hand, the enhancement type refers to a type in which no drain current flows when the gate-source voltage is 0V.

The source and backgate of transistor M0 and the drain of transistor M1 are all connected to the application terminal of power supply voltage VCC. The source and backgate of transistor M1 are all connected to the first terminal of resistor R1. The gates of transistors M0 and M1, the drain of transistor M2, and the second terminal of resistor R1 are all connected to the application terminal of node signal VB. The source and backgate of transistor M2 are all connected to the first terminal of resistor R2. The gate of transistor M2 is connected to the application terminal of node signal VA. The drain of transistor M0 and the first terminal of resistor R0 are all connected to the application terminal of node signal VC (and thus output signal OUT). The second terminals of resistors R0 and R2 are all connected to the ground terminal. The node signal VC is a signal of a logical level corresponding to node signal VB (details will be described later).

Transistor M0 functions as an output transistor that switches the logic level of the output signal OUT in response to a node signal VB that appears at the drain of transistor M2. Although not shown separately, transistor M0 may be replaced with a pnp transistor.

The gate and base of a transistor can be interpreted as corresponding to the control electrode of the transistor. The source and emitter of a transistor can be interpreted as corresponding to the first main electrode of the transistor. The drain and collector of a transistor can be interpreted as corresponding to the second main electrode of the transistor.

The first end of resistor R3 is connected to the application terminal of the input signal VMON. The second end of resistor R3 and the first end of resistor R4 are both connected to the application terminal of the node signal VA. The second end of resistor R4 is connected to the ground terminal.

The resistors R3 and R4 connected in this way function as a resistive voltage divider DIV that divides the input signal VMON to generate a node signal VA (corresponding to a voltage-divided signal). However, the resistors R3 and R4 (i.e., the resistive voltage divider) may be omitted. In that case, the gate of the transistor M2 may be directly connected to the application terminal of the input signal VMON.

Figure 4 is a diagram showing the input/output behavior of the comparison circuit 1 in the first embodiment. Note that the horizontal axis of this figure represents the input signal VMON. The vertical axis of this figure represents the output signal OUT.

When the input signal VMON is lower than the detection voltage VDET, the node signal VB applied to the gate of the transistor M0 is pulled up via the transistor M1 and the resistor R1. Therefore, the transistor M0 is turned off, and the node signal VC is pulled down via the resistor R0. As a result, the output signal OUT becomes low level. The impedance of the pull-up path formed by the transistor M1 and the resistor R1 is determined by Vgs1/R1.

On the other hand, when the input signal VMON rises, the node signal VA applied to the gate of transistor M2 also rises. Therefore, the impedance of transistor M2 falls. Then, when the input signal VMON becomes higher than the detection voltage VDET, the impedance of transistor M2 falls below the impedance of the pull-up path formed by transistor M1 and resistor R1. As a result, the node signal VB applied to the gate of transistor M0 falls. Therefore, transistor M0 is turned on, and node signal VC is pulled up via transistor M0. As a result, the output signal OUT becomes high level.

In this way, the comparison circuit 1 of this embodiment can switch the logic level of the output signal OUT depending on the comparison result between the input signal VMON and the predetermined detection voltage VDET.

Furthermore, the comparison circuit 1 does not require the previously mentioned reference voltage generation circuit 120 and comparator 140. In this way, if the output signal OUT is generated using only the minimum necessary elements, the circuit scale of the comparison circuit 1 is reduced. Furthermore, as the circuit scale is reduced, the causes of element variation are also reduced. Therefore, the characteristics (detection accuracy, etc.) of the comparison circuit 1 can be improved.

When the input signal VMON becomes higher than the detection voltage VDET, a current I flows through resistor R2 that is equal to the current I (= Vgs1/R1) flowing through resistor R1. Therefore, a voltage V (= Vgs1 × (R2/R1)) corresponding to the current I is generated across resistor R2.

At this time, the node signal VA applied to transistor M2 is the voltage value (= Vgs2 + Vgs1 × (R2/R1)) obtained by adding the voltage V between both ends of resistor R2 and the gate-source voltage Vgs2 of transistor M2.

Therefore, the detection voltage VDET is expressed as {Vgs2+Vgs1×(R2/R1)}×(R3+R4)/R4. In other words, the absolute value of the detection voltage VDET can be adjusted by the resistance ratio of resistors R3 and R4.

Figure 5 is a diagram showing the temperature characteristics of the detection voltage VDET in the first embodiment. As shown in the upper left of this figure, the gate-source voltage Vgs2 of the enhancement type transistor M2 has a negative temperature characteristic. In other words, the gate-source voltage Vgs2 decreases as the temperature T increases.

On the other hand, as shown in the lower left of the figure (dash line), the gate-source voltage Vgs1 of the depletion-type transistor M1 has a positive temperature characteristic. In other words, the higher the temperature T, the higher the gate-source voltage Vgs1. Therefore, as shown in the lower left of the figure (solid line), the voltage V (= Vgs1 × (R2/R1)) across resistor R2 also has a positive temperature characteristic. In other words, the higher the temperature T, the higher the voltage V across both ends.

Therefore, by appropriately adjusting the element size of each of the transistors M1 and M2 and the resistance value of each of the resistors R1 and R2, the temperature characteristics of the detection voltage VDET can be made closer to flat compared to a configuration that does not have resistors R1 and R2 (dashed line).

In one example of the adjustment process, in a first step, the element sizes (and thus the element size ratio) of the transistors M1 and M2 may be determined so that the quadratic temperature characteristics of the gate-source voltages Vgs1 and Vgs2, respectively, are offset. For example, when the detection voltage VDET is expressed as a quadratic function f(T)= ^ax2 +bx+c of temperature T, the element sizes of the transistors M1 and M2 may be adjusted so that the quadratic coefficient a in the quadratic function f(T) becomes 0.

In this state, if the gate-source voltage Vgs2 of transistor M2 and the voltage V across resistor R2 are simply added together, the first-order temperature characteristics of the gate-source voltages Vgs1 and Vgs2 may remain.

Therefore, in the subsequent second step, the resistance values (and thus the resistance ratio) of resistors R1 and R2 may be adjusted. For example, the resistance values of resistors R1 and R2 may be adjusted so that the linear coefficient b in the quadratic function f(T) becomes 0.

More specifically, for example, if the detection voltage VDET still has a negative temperature characteristic, the resistance values of resistors R1 and R2 may be adjusted so that R2>R1. With such adjustment, the temperature characteristic (positive) of the gate-source voltage Vgs1 becomes dominant over the temperature characteristic (negative) of the gate-source voltage Vgs2. Therefore, the temperature characteristic of the detection voltage VDET is made closer to flat.

Note that when the resistance values of resistors R1 and R2 are adjusted, the secondary temperature characteristics that were offset in the first step may shift. Therefore, in the third step, the element sizes of transistors M1 and M2 may be fine-tuned.

By performing the above series of adjustment processes, a highly accurate detection voltage VDET with a nearly flat temperature characteristic can be set, as shown on the right side of the figure. This improves the detection accuracy of the comparison circuit 1.

The resistors R1 and R2 may be elements having the same temperature characteristics. For example, the resistors R1 and R2 may both be polysilicon resistors having negative temperature characteristics. Also, for example, the resistors R1 and R2 may both be diffused resistors having positive temperature characteristics.

Second Embodiment
6 is a diagram showing a second embodiment of the comparator circuit 1. The comparator circuit 1 of this embodiment is based on the first embodiment (FIG. 3) described above, and further includes a transistor M3 (e.g., an enhancement type NMOSFET), a resistor R5, and an inverter INV.

The second end of resistor R4 is not directly connected to the ground terminal, but is connected to the first end of resistor R5 and the drain of transistor M3. The second end of resistor R5 and the source and backgate of transistor M3 are all connected to the ground terminal.

Transistor M3 and resistor R5 connected in this manner can be understood as components of a resistive voltage divider DIV.

The application terminal of the node signal VC is not directly connected to the application terminal of the output signal OUT, but is connected to the input terminal of the inverter INV. The output terminal of the inverter INV is connected to the application terminal of the node signal VD (and thus the output signal OUT) and the gate of the transistor M3. In other words, the drain of the transistor M0 is connected to the application terminal of the output signal OUT via the inverter INV.

The inverter INV inverts the logic level of the node signal VC to generate the node signal VD. Therefore, the node signal VD is at a low level when the node signal VC is at a high level, and is at a high level when the node signal VC is at a low level.

When the node signal VD is at a high level, the transistor M3 is turned on. At this time, both ends of the resistor R5 are shorted via the transistor M3. Therefore, the voltage division ratio of the resistive voltage divider DIV is R4/(R3+R4).

On the other hand, when the node signal VD is at a low level, the transistor M3 is turned off. At this time, both ends of the resistor R5 are open. Therefore, the voltage division ratio of the resistor divider DIV is (R4+R5)/(R3+R4+R5).

In this way, the resistive voltage divider DIV switches the voltage division ratio depending on the logic level of the node signal VD (and thus the output signal OUT).

Figure 7 is a diagram showing the input/output behavior in the second embodiment. Note that the horizontal axis of this figure represents the input signal VMON. The vertical axis of this figure represents the output signal OUT.

When the input signal VMON becomes higher than the detection voltage VDET (= {Vgs2 + Vgs1 x (R2/R1)} x (R3 + R4)/R4), the output signal OUT falls from high to low. At this time, the transistor M3 is turned off. Therefore, the voltage division ratio of the resistive divider DIV switches to (R4 + R5)/(R3 + R4 + R5). In other words, the comparison target of the input signal VMON is lowered to the detection voltage VDETL (= {Vgs2 + Vgs1 x (R2/R1)} x (R3 + R4 + R5)/(R4 + R5)).

On the other hand, when the input signal VMON becomes lower than the detection voltage VDETL, the output signal OUT falls from low to high. At this time, the transistor M3 is turned on. Therefore, the voltage division ratio of the resistive voltage divider DIV switches to R4/(R3+R4). In other words, the comparison target of the input signal VMON is raised to the detection voltage VDET.

In this way, hysteresis may be added to the detection voltage VDET that is compared with the input signal VMON.

Third Embodiment
8 is a diagram showing a third embodiment of the comparison circuit. The comparison circuit 1 of this embodiment is based on the first embodiment (FIG. 2) described above, but includes a transistor M11 (e.g., a depletion-type NMOSFET), a transistor M12 (e.g., an enhancement-type NMOSFET), transistors M13 and M14 (e.g., PMOSFETs), and resistors R11 and R12 instead of the transistors M1 and M2 and the resistors R1 and R2.

The gate-source voltages Vgs11 and Vgs12 of transistors M11 and M12, respectively, have different temperature characteristics. For example, the gate-source voltage Vgs11 of transistor M11, which is a depletion type, has a positive temperature characteristic. On the other hand, the gate-source voltage Vgs12 of transistor M12, which is an enhancement type, has a negative temperature characteristic. In this respect, it is similar to the transistors M1 and M2 mentioned above.

In addition, resistors R11 and R12 may be elements having the same temperature characteristics. For example, resistors R11 and R12 may both be polysilicon resistors having negative temperature characteristics. In addition, resistors R11 and R12 may both be diffused resistors having positive temperature characteristics. In this respect, it is the same as resistors R1 and R2 mentioned above.

The drain of transistor M11 is connected to the drain of transistor M13 (= the input terminal of the current mirror CM). The source and back gate of transistor M11 are connected to the first terminal of resistor R11. The gate of transistor M11 and the second terminal of resistor R11 are both connected to the ground terminal (= the reference potential terminal).

The sources and back gates of the transistors M13 and M14 are connected to the application terminal of the power supply voltage VCC. The gates of the transistors M13 and M14 are connected to the drain of the transistor M13. The drain of the transistor M14 (= the output terminal of the current mirror CM) and the drain of the transistor M12 are both connected to the application terminal of the node signal VB (= the gate of the transistor M0). The source and back gate of the transistor M12 are connected to the first terminal of the resistor R12. The second terminal of the resistor R12 is connected to the ground terminal. The gate of the transistor M12 is connected to the application terminal of the node signal VA (= the connection node between the resistors R3 and R4).

Transistors M13 and M14 connected in this way form a current mirror CM. The current mirror CM mirrors the drain current of transistor M13 as the drain current of transistor M14.

When the input signal VMON is lower than the detection voltage VDET, the node signal VB applied to the gate of the transistor M0 is pulled up via the current mirror CM. Therefore, the transistor M0 is turned off, and the node signal VC is pulled down via the resistor R0. As a result, the output signal OUT becomes low level. The impedance of the pull-up path by the current mirror CM is determined by Vgs11/R11.

On the other hand, when the input signal VMON rises, the node signal VA applied to the gate of transistor M12 also rises. Therefore, the impedance of transistor M12 falls. Then, when the input signal VMON becomes higher than the detection voltage VDET, the impedance of transistor M12 falls below the impedance of the pull-up path by the current mirror CM. Therefore, the node signal VB applied to the gate of transistor M0 falls. Therefore, since transistor M0 is turned on, the node signal VC is pulled up via transistor M0. As a result, the output signal OUT becomes high level.

In this way, even with a circuit configuration in which the current I flowing through resistor R11 is supplied to resistor R12 via the current mirror CM, the same effects as those of the first embodiment (Figure 3) can be obtained.

When the input signal VMON becomes higher than the detection voltage VDET, a current I flows through resistor R12, which is equal to the current I (=Vgs11/R11) flowing through resistor R11. Therefore, a voltage V (=Vgs11×(R12/R11)) corresponding to the current I is generated across resistor R12.

At this time, the node signal VA applied to transistor M12 is the voltage value (= Vgs12 + Vgs11 × (R12/R11)) obtained by adding the voltage V across resistor R12 and the gate-source voltage Vgs12 of transistor M12.

Therefore, the detection voltage VDET is expressed as {Vgs12+Vgs11×(R12/R11)}×(R13+R14)/R14. Therefore, by appropriately adjusting the element sizes of the transistors M11 and M12 and the resistance values of the resistors R11 and R12, the temperature characteristics of the detection voltage VDET can be made closer to flat. In addition, the absolute value of the detection voltage VDET can be adjusted by the resistance ratio of the resistors R13 and R14.

The current mirror CM is not limited to PMOSFETs, and may be formed by bipolar pnp transistors.

Fourth Embodiment
9 is a diagram showing a fourth embodiment of the comparator circuit, which is based on the third embodiment (FIG. 8) and further includes the transistor M3, resistor R5, and inverter INV.

In this way, while the circuit configuration is based on supplying the current I flowing through resistor R11 to resistor R12 via the current mirror CM, hysteresis may be added to the detection voltage VDET that is compared with the input signal VMON, following the second embodiment (Figure 6) described above.

Fifth Embodiment
10 is a diagram showing a comparison circuit according to a fifth embodiment of the present invention. The comparison circuit 1 according to the present embodiment is based on the first embodiment (FIG. 3) described above, but includes a transistor M2′ (e.g., a P+ gate depletion type NMOSFET) instead of the transistor M2.

The aforementioned transistor M1 is a typical depletion type (N+ gate) with n-type impurities injected into the gate. The on-threshold voltage of transistor M1 is a negative voltage (approximately -0.5V). On the other hand, transistor M2' is a depletion type (P+ gate) with p-type impurities injected into the gate. The on-threshold voltage of transistor M2' can be designed to be a positive voltage (approximately +0.6V). Therefore, transistor M2' can replace enhancement type transistor M2.

Transistors M1 and M2' share a common device structure (particularly the portion below the gate). Therefore, in the comparison circuit 1 of this embodiment, the detection voltage VDET is less susceptible to the effects of manufacturing variations compared to the first embodiment (FIG. 3).

The comparison circuit 1 of this embodiment is based on the first embodiment (Figure 3) described above, but may also be based on the second embodiment (Figure 6), the third embodiment (Figure 8), or the fourth embodiment (Figure 9).

In addition, transistors M2 and M12 may each be replaced with a bipolar npn transistor.

<Combination of the embodiments>
The circuit configurations of the first to fifth embodiments described above may be arbitrarily combined within a range where no contradiction occurs.

<Additional Notes>
The following provides a general description of the various embodiments described above.

For example, the comparison circuit according to the present disclosure includes a first transistor of a depletion type, a second transistor configured to have an input signal or a divided voltage signal thereof applied to its control electrode, a first resistor configured to be connected between the gate and source of the first transistor, and a second resistor connected to a first main electrode of the second transistor and configured to pass a current equal to the current flowing through the first resistor, and is configured to output a node signal appearing at the second main electrode of the second transistor or a signal corresponding thereto as an output signal (first configuration).

In the comparison circuit according to the first configuration, the second transistor may be an enhancement type, a depletion type in which an impurity of a conductivity type different from that of the first transistor is injected into the gate, or a bipolar type transistor (second configuration).

In the comparison circuit having the first or second configuration, the first resistor and the second resistor may be configured to have the same temperature characteristics (third configuration).

The comparison circuit according to any one of the first to third configurations may be further configured (fourth configuration) to include a resistive voltage divider configured to divide the input signal to generate the divided voltage signal.

In the comparison circuit of the fourth configuration, the resistive voltage divider may be configured to switch the voltage division ratio according to the logic level of the output signal (fifth configuration).

The comparison circuit according to any one of the first to fifth configurations may be further configured (sixth configuration) to include an output transistor configured to switch the logic level of the output signal in response to the node signal.

In the comparison circuit according to the sixth configuration, the drain of the first transistor is connected to a power supply potential terminal, the source of the first transistor is connected to a first terminal of the first resistor, the first main electrode of the second transistor is connected to a first terminal of the second resistor, the second terminal of the second resistor is connected to a reference potential terminal, the gate of the first transistor, the second terminal of the first resistor, and the second main electrode of the second transistor are connected to a control electrode of the output transistor, the first main electrode of the output transistor is connected to the power supply potential terminal, and the second main electrode of the output transistor is connected to an application terminal of the output signal directly or via an inverter (seventh configuration).

In addition, in the comparison circuit according to the sixth configuration, the drain of the first transistor is connected to the input terminal of the current mirror, the source of the first transistor is connected to the first terminal of the first resistor, the first main electrode of the second transistor is connected to the first terminal of the second resistor, the gate of the first transistor and the second terminals of the first resistor and the second resistor are connected to a reference potential terminal, the output terminal of the current mirror and the second main electrode of the second transistor are connected to the control electrode of the output transistor, the first main electrode of the output transistor is connected to a power supply potential terminal, and the second main electrode of the output transistor is connected to an application terminal of the output signal directly or via an inverter (eighth configuration).

In the comparison circuit according to any one of the sixth to eighth configurations, the output transistor may be configured to be a P-channel type or a PNP type (ninth configuration).

In the comparison circuit according to any one of the first to ninth configurations, the detection voltage at which the logic level of the output signal switches may be expressed as a quadratic function of temperature, the element sizes of the first transistor and the second transistor may be adjusted so that the quadratic coefficient of the quadratic function is zero, and the resistance values of the first resistor and the second resistor may be adjusted so that the linear coefficient of the quadratic function is zero (tenth configuration).

According to the present disclosure, for example, a small-scale comparison circuit with high detection accuracy can be provided.

＜Other＞
In addition, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation, in addition to the above-mentioned embodiment. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects. In addition, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

1 Comparison circuit 100 Comparison circuit 110 Transistor (enhancement type NMOSFET)
120 Reference voltage generating circuit 130 Divided voltage generating circuit 131, 132 Resistor 140 Comparator 150 Resistor CM Current mirror DIV Resistive voltage divider INV Inverter M0 Transistor (PMOSFET)
M1 transistor (depletion type NMOSFET)
M2 Transistor (enhancement type NMOSFET)
M2' transistor (depletion type NMOSFET, P+ gate)
M3 Transistor (enhancement type NMOSFET)
M11 Transistor (Depletion-type NMOSFET)
M12 Transistor (enhancement type NMOSFET)
M13 Transistor (PMOSFET)
M14 Transistor (PMOSFET)
R0, R1, R2, R3, R4, R5 Resistor R11, R12, R13, R14 Resistor

Claims (10)

a first transistor of the depletion type;
a second transistor configured so that an input signal or a divided voltage signal thereof is applied to a control electrode thereof;
a first resistor configured to be connected between the gate and source of the first transistor;
a second resistor connected to a first main electrode of the second transistor so as to pass a current having a value equal to that of the current passing through the first resistor;
Equipped with
a comparison circuit that outputs, as an output signal, a node signal appearing at the second main electrode of the second transistor or a signal corresponding thereto; The comparison circuit according to claim 1, wherein the second transistor is an enhancement type transistor, a depletion type transistor having a gate doped with an impurity of a conductivity type different from that of the first transistor, or a bipolar type transistor. The comparison circuit of claim 1, wherein the first resistor and the second resistor have the same temperature characteristics. The comparison circuit of claim 1, further comprising a resistive divider configured to divide the input signal to generate the divided signal. The comparison circuit according to claim 4, wherein the resistive voltage divider switches a voltage division ratio according to the logic level of the output signal. The comparison circuit of claim 1, further comprising an output transistor configured to switch the logic level of the output signal in response to the node signal. The drain of the first transistor is connected to a power supply potential terminal,
a source of the first transistor is connected to a first end of the first resistor;
a first main electrode of the second transistor is connected to a first end of the second resistor;
a second end of the second resistor is connected to a reference potential end;
a gate of the first transistor, a second end of the first resistor, and a second main electrode of the second transistor are connected to a control electrode of the output transistor;
a first main electrode of the output transistor is connected to the power supply potential terminal;
7. The comparison circuit according to claim 6, wherein the second main electrode of the output transistor is connected directly or via an inverter to an application terminal of the output signal. The drain of the first transistor is connected to an input terminal of a current mirror;
a source of the first transistor is connected to a first end of the first resistor;
a first main electrode of the second transistor is connected to a first end of the second resistor;
a gate of the first transistor and a second terminal of each of the first resistor and the second resistor are connected to a reference potential terminal;
an output terminal of the current mirror and a second main electrode of the second transistor are connected to a control electrode of the output transistor;
a first main electrode of the output transistor is connected to a power supply potential terminal;
7. The comparison circuit according to claim 6, wherein the second main electrode of the output transistor is connected directly or via an inverter to an application terminal of the output signal. The comparison circuit according to claim 6, wherein the output transistor is a P-channel type or a PNP type. a detection voltage at which a logic level of the output signal switches is expressed as a quadratic function of temperature;
the first transistor and the second transistor have respective element sizes adjusted so that a quadratic coefficient in the quadratic function becomes 0;
10. The comparison circuit according to claim 1, wherein the first resistor and the second resistor have respective resistance values adjusted so that a linear coefficient in the quadratic function becomes zero.

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