JP2024167877A - Wafers and semiconductor devices - Google Patents

Abstract

To provide a wafer and a semiconductor device capable of improving characteristics.SOLUTION: According to one embodiment, a wafer includes a silicon substrate, a first layer, and a plurality of structures. The first layer includes aluminum and nitrogen. The plurality of structures are provided between a part of the silicon substrate and a part of the first layer in a first direction from the silicon substrate to the first layer. The plurality of structures include a first element that includes at least one selected from the group consisting of Ni, Cu, Cr, Mn, Fe and Co and silicon. Another part of the first layer is in contact with another part of the silicon substrate.SELECTED DRAWING: Figure 1

Description

Embodiments of the present invention relate to wafers and semiconductor devices.

For example, semiconductor devices are formed using wafers containing nitrides. It is desirable to improve the characteristics of the wafers and semiconductor devices.

JP 2003-224072 A

Embodiments of the present invention provide wafers and semiconductor devices that can improve characteristics.

According to an embodiment of the present invention, a wafer includes a silicon substrate, a first layer, and a plurality of structures. The first layer includes aluminum and nitrogen. The plurality of structures are provided between a portion of the silicon substrate and a portion of the first layer in a first direction from the silicon substrate to the first layer. The plurality of structures include silicon and a first element including at least one selected from the group consisting of Ni, Cu, Cr, Mn, Fe, and Co. Another portion of the first layer contacts another portion of the silicon substrate.

FIG. 1 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. FIG. 2 is an electron microscope image illustrating the wafer according to the first embodiment. FIG. 3 is a microscope image illustrating the wafer according to the first embodiment. 4(a) to 4(c) are microscope images illustrating the wafer according to the first embodiment. FIG. 5 is an image showing positions on a wafer according to the first embodiment. FIG. 6 is a graph illustrating element concentrations in the wafer according to the first embodiment. FIG. 7 is a graph illustrating element concentrations in the wafer according to the first embodiment. FIG. 8 is a graph illustrating element concentrations in the wafer according to the first embodiment. FIG. 9 is a graph illustrating element concentrations in the wafer according to the first embodiment. FIG. 10 is a graph illustrating element concentrations in the wafer according to the first embodiment. FIG. 11 is an element profile illustrating the wafer according to the first embodiment. FIG. 12 is an element profile illustrating the wafer according to the first embodiment. FIG. 13 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. FIG. 14 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing.
In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals and detailed descriptions thereof will be omitted as appropriate.

First Embodiment
FIG. 1 is a schematic cross-sectional view illustrating a wafer according to the first embodiment.
1, a wafer 110 according to the embodiment includes a silicon substrate 15, a first layer 17, and a plurality of structures 16. The first layer 17 includes aluminum and nitrogen. The first layer 17 is, for example, an AlN layer.

The first direction D1 from the silicon substrate 15 to the first layer 17 is defined as the Z-axis direction. One direction perpendicular to the Z-axis direction is defined as the X-axis direction. The direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction.

The first layer 17 is a layer parallel to the XY plane. The silicon substrate 15 is aligned along the XY plane.

The multiple structures 16 are provided in the first direction D1 between a portion of the silicon substrate 15 and a portion of the first layer 17. For example, another portion of the first layer 17 contacts another portion of the silicon substrate 15.

For example, the silicon substrate 15 includes a first silicon region 15a, a second silicon region 15b, and a third silicon region 15c. In the first direction D1, the multiple structures 16 are provided between the first silicon region 15a and the first layer 17. In a direction intersecting the first direction D1, one of the multiple structures 16 is between the second silicon region 15b and the third silicon region 15c. The direction intersecting the first direction D1 is any direction along the XY plane. For example, the multiple structures 16 are island-shaped. The multiple structures 16 are discontinuous with each other.

The plurality of structures 16 includes a first element including at least one selected from the group consisting of Ni, Cu, Cr, Mn, Fe, and Co, and silicon. The first element is, for example, a transition element. For example, the plurality of structures 16 includes a compound including Ni and silicon. The plurality of structures 16 includes, for example, a crystal.

A number of such structures 16 are distributed between the silicon substrate 15 and the first layer 17 (AlN layer). This relieves stress in the wafer 110, suppressing, for example, cracks.

For example, a reference example can be considered in which a continuous layer containing Ni or the like is provided between the silicon substrate 15 and the first layer 17. In this case, since the layer containing Ni or the like is provided continuously between the silicon substrate 15 and the first layer 17, the crystallinity is reduced due to the mismatch of the lattice constants.

In contrast, in the embodiment, multiple discontinuous structures 16 are provided. This alleviates the mismatch in lattice constants. This results in multiple structures 16 with high crystallinity. By forming the first layer 17 on the multiple highly crystalline structures 16 and the silicon substrate 15, high crystallinity is obtained in the first layer 17 and the nitride layer formed thereon. According to the embodiment, high crystallinity is obtained while suppressing cracks. According to the embodiment, a wafer capable of improving characteristics can be provided.

As described above, for example, the plurality of structures 16 includes a compound containing Ni and silicon. The thermal expansion coefficient of the silicon substrate 15 is about 3.6×10 ⁻⁶ /K. The thermal expansion coefficient of the first layer 17 (AlN) is about 4.2×10 ⁻⁶ /K. The thermal expansion coefficient of NiSi ₂ is about 14.4×10 ⁻⁶ /K. Thus, the thermal expansion coefficient of NiSi ₂ is large. This can reduce the tensile stress that occurs when, for example, various layers are formed on the wafer 110 at high temperature and then the temperature is lowered to room temperature.

The lattice constant of the silicon substrate 15 is 0.543 nm. The lattice constant of the first layer 17 (AlN) is 0.311 nm. The lattice constant of NiSi ₂ is 0.540 nm. The lattice constant of NiSi ₂ is equal to the lattice constant of the silicon substrate 15.

In one example, the multiple structures 16 are obtained by heat-treating the silicon substrate 15 in an environment containing a first element (e.g., Ni). For example, a small amount of the first element is attached to the surface of the silicon substrate 15 by the heat treatment. The first element may be incorporated into the silicon substrate 15 by the heat treatment. In this case, if a large amount of the first element is attached to the surface of the silicon substrate 15, a continuous film is formed, and the multiple discontinuous structures 16 are not obtained. The wafer 110 is obtained by forming a first layer 17 on the silicon substrate 15 on which the multiple structures 16 are provided. The first layer 17 can be formed by a method such as MOCVD (Metal Organic Chemical Vapor Deposition).

By providing multiple discontinuous structures 16, the crystallinity of the multiple structures 16 can be improved. On the other hand, if a continuous film is provided, the crystallinity deteriorates. If the first layer 17 (AlN) is formed on a deteriorated continuous film, the crystallinity of the first layer 17 (AlN) deteriorates. By forming the first layer 17 (AlN) on multiple discontinuous structures 16, it is easy to obtain a high-quality first layer 17 (AlN).

In an embodiment, the plurality of structures 16 may include, for example, a compound of Cu and silicon. In this case, high crystallinity is obtained while cracks are suppressed. In addition, the plurality of structures 16 may include, for example, a compound of at least one selected from the group consisting of Ni, Cu, Cr, Mn, Fe, and Co, and silicon.

FIG. 2 is an electron microscope image illustrating the wafer according to the first embodiment.
Fig. 2 is a High Angle Annular Dark-Field Scanning Transmission Electron Microscopy (HAADF-STEM) image of a cross section of the wafer 110. Fig. 2 illustrates one of the multiple structures 16. The thickness of the first layer 17 along the first direction D1 is defined as a first layer thickness t17. The thickness of one of the multiple structures 16 along the first direction D1 is defined as a structure thickness t16. The structure thickness t16 is thinner than the first layer thickness t17.

The structure thickness t16 is, for example, 5 nm or more and 30 nm or less. A thin structure thickness t16 makes it easier to obtain high crystallinity in the multiple structures 16. If the structure thickness t16 is excessively thick, the crystallinity may be low. If the structure thickness t16 is excessively thin, the stress relaxation effect is reduced, and the crack suppression effect is reduced.

As shown in FIG. 2, the length of one of the multiple structures 16 in a direction perpendicular to the first direction D1 is defined as the structure length 16L. In an embodiment, the structure length 16L is, for example, 200 nm or more and 5000 nm or less. If the structure length 16L is excessively long, for example, the crystallinity may be reduced. If the structure length 16L is excessively short, the crack suppression effect may be reduced.

2, the wafer 110 may further include a nitride layer 10L. The first layer 17 is provided between the silicon substrate 15 and the nitride layer 10L. The nitride layer 10L includes at least one selected from the group consisting of Al and Ga, and nitrogen. The nitride layer 10L may include, for example, an AlGaN layer 13, a stacked structure 14, and a first nitride region 11. In the embodiment, by providing a plurality of structures 16, high crystallinity is obtained in the nitride layer 10L. An example of the nitride layer 10L will be described later.

FIG. 3 is a microscope image illustrating the wafer according to the first embodiment.
Figure 3 is an optical microscope image of wafer 110. Figure 3 illustrates silicon substrate 15 and structures 16 before first layer 17 is formed.

The bright dots illustrated in FIG. 3 correspond to the structures 16. The dark areas in the image in FIG. 3 correspond to areas where the structures 16 are not present. The dark areas correspond, for example, to the surface of the silicon substrate 15. The dark areas correspond, for example, to the nitride layer 10L where the structures 16 are not present. As shown in FIG. 3, the structures 16 are island-like (dot-like).

For example, the density of the multiple structures 16 in the XY plane (plane perpendicular to the first direction D1) is, for example, 2×10 ³ /cm ² or more and 2×10 ⁵ /cm ² or less. If the density is excessively high, for example, parts of the multiple structures 16 tend to be continuous with each other. Crystallinity may decrease. If the density is excessively low, for example, the effect of stress relaxation decreases, and the effect of suppressing cracks decreases.

4(a) to 4(c) are microscope images illustrating the wafer according to the first embodiment.
These figures are HAADF-STEM images of a cross section of the wafer 110. Fig. 4(a) is an HAADF-STEM image of a portion including one of the multiple structures 16. Fig. 4(b) is an enlarged image of region Q1 in Fig. 4(a). Fig. 4(c) is an enlarged image of region Q2 in Fig. 4(a).

As shown in FIG. 4(b), one of the multiple structures 16 is provided between the first silicon region 15a and the first layer 17. The second silicon region 15b includes a substrate surface 15f facing the first layer 17. One of the multiple structures 16 includes a structure surface 16f facing the first layer 17. The position of the substrate surface 15f in the first direction D1 coincides with the position of the structure surface 16f in the first direction D1. The top surface of the first silicon region 15a is aligned with the top surface of one of the multiple structures 16.

As shown in FIG. 4(b), one of the multiple structures 16 includes a structure side surface 16s that faces the second silicon region 15b. The structure side surface 16s is inclined with respect to the first direction D1. For example, the structure side surface 16s is aligned along a crystal plane of the silicon substrate 15. In one example, the structure side surface 16s is aligned along the (111) plane of the silicon substrate 15. In the multiple structures 16 having high crystallinity, an inclined structure side surface 16s aligned along a crystal plane of the silicon substrate 15 is obtained.

As shown in Figures 4(b) and 4(c), crystal lattices are observed in multiple structures 16.

As shown in FIG. 4(b), an intermediate region 16M may be provided between the multiple structures 16 and the first layer 17. The intermediate region 16M is, for example, a transition region. The intermediate region 16M will be described later.

An example of the analysis results of elements in the wafer 110 will now be described.
FIG. 5 is an image showing positions on a wafer according to the first embodiment.
6 to 10 are graphs illustrating element concentrations in the wafer according to the first embodiment.
In Fig. 5, positions in the wafer 110 are shown in the same image as the HAADF-STEM image in Fig. 4(a). Fig. 6 corresponds to the analysis results at the first position P1 shown in Fig. 5. Fig. 7 corresponds to the analysis results at the second position P2 shown in Fig. 5. Fig. 8 corresponds to the analysis results at the third position P3 shown in Fig. 5. Fig. 9 corresponds to the analysis results at the fourth position P4 shown in Fig. 5. Fig. 10 corresponds to the analysis results at the fifth position P5 shown in Fig. 5.

The first position P1 corresponds to the first silicon region 15a. The second position P2 corresponds to one of the multiple structures 16. The third position P3 corresponds to the first layer 17. In the Z-axis direction, the second position P2 is between the first position P1 and the third position P3. The fourth position P4 corresponds to the second silicon region 15b. The fifth position P5 corresponds to the third silicon region 15c. Figures 6 to 10 are the results of analysis by TEM-EDX. In this example, the first element is Ni.

As shown in FIG. 7, the first element (Ni) is detected at the second position P2. In this example, the atomic concentration of Ni is 25.8 atm%. On the other hand, as shown in FIG. 6 and FIG. 8, the first element (Ni) is not detected at the first position P1 and the third position P3. As shown in FIG. 9 and FIG. 10, the first element (Ni) is not detected at the fourth position P4 and the fifth position P5 either. A plurality of structures 16 that are discontinuous with each other are formed.

FIG. 11 is an element profile illustrating the wafer according to the first embodiment.
11 illustrates the results of a three-dimensional atom probe analysis of a cross section of one of the structures 16 of the wafer 110. The cross section is parallel to a first direction D1. The horizontal axis of FIG. 11 is the position pZ in the Z-axis direction. The vertical axis is the concentration C1 (atomic %) of the detected element.

As shown in FIG. 11, silicon is detected in the silicon substrate 15. Al and N are detected in the first layer 17. Ni (first element) and silicon are detected in the structure 16.

As shown in FIG. 11, the wafer 110 may include an intermediate region 16M (see FIG. 4(b)). The intermediate region 16M is provided between the multiple structures 16 and a portion of the first layer 17. As shown in FIG. 11, the intermediate region 16M includes Al, N, and Si. The intermediate region 16M is, for example, a transition region.

The intermediate region 16M does not contain the first element (e.g., Ni). Alternatively, the concentration of the first element in the intermediate region 16M is lower than the concentration of the first element in the multiple structures 16. As described below, carbon or the like may be detected in the intermediate region 16M.

FIG. 12 is an element profile illustrating the wafer according to the first embodiment.
12 illustrates the results of analyzing a cross section of one of the structures 16 of the wafer 110 with a three-dimensional atom probe. The cross section is parallel to the first direction D1. The horizontal axis of FIG. 12 is the position pZ in the Z-axis direction. The left vertical axis is the concentration C1 (atomic %) of carbon, silicon, and Al. The right vertical axis is the concentration C(b) (atomic %) of boron. The silicon and Al profiles in FIG. 12 are the same as the silicon and Al profiles illustrated in FIG. 11.

As shown in FIG. 12, the intermediate region 16M may contain carbon. Meanwhile, the first layer 17 does not contain carbon. Alternatively, the carbon concentration in the first layer 17 is lower than the carbon concentration in the intermediate region 16M. The multiple structures 16 do not contain carbon. Alternatively, the carbon concentration in the multiple structures 16 is lower than the carbon concentration in the intermediate region 16M.

By providing the intermediate region 16M containing carbon, better characteristics can be obtained. For example, carbon is present locally in the intermediate region 16M. For example, the adverse effects of carbon in the first layer 17 are suppressed. The concentration of B may be locally high in the intermediate region 16M.

Second Embodiment
The second embodiment relates to a semiconductor device.
FIG. 13 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment.
13 , a semiconductor device 120 according to the embodiment includes the wafer 110 according to the first embodiment, a first electrode 51, a second electrode 52, and a third electrode 53. The semiconductor device 120 may include an insulating member 61.

As already described, the wafer 110 includes a silicon substrate 15, a first layer 17, and a plurality of structures 16. In this example, the wafer 110 includes a nitride layer 10L. The nitride layer 10L includes an AlGaN layer 13, a stacked structure 14, and a first nitride region 11, etc.

The laminated structure 14 includes a plurality of first films 14a and a plurality of second films 14b. One of the plurality of first films 14a is provided between one of the plurality of second films 14b and another one of the plurality of second films 14b. One of the plurality of second films 14b is provided between one of the plurality of first films 14a and another one of the plurality of first films 14a.

An AlGaN layer 13 is provided between the first layer 17 and the first nitride region 11. A stacked structure 14 is provided between the AlGaN layer 13 and the first nitride region 11.

The first nitride region 11 contains, for example, Al _x1 Ga _1-x1 N (0≦x1<1), where the composition ratio x1 is, for example, not less than 0 and not more than 0.15. The first nitride region 11 is, for example, a GaN layer.

In this example, the nitride layer 10L includes a second nitride region 12. The second nitride region 12 includes, for example, Al _x2 Ga _1-x2 N (0<x2≦1, x1<x2). The composition ratio x2 is, for example, higher than 0.15 and equal to or lower than 0.3. The second nitride region 12 is, for example, an AlGaN layer.

The first nitride region 11 is provided between the first layer 17 and the second nitride region 12. The direction from the first electrode 51 to the second electrode 52 is along a second direction D2 that intersects with the first direction D1. The second direction D2 is, for example, the X-axis direction. The position of the third electrode 53 in the second direction D2 is between the position of the first electrode 51 in the second direction D2 and the position of the second electrode 52 in the second direction D2.

The first nitride region 11 includes a first partial region 11a, a second partial region 11b, a third partial region 11c, a fourth partial region 11d, and a fifth partial region 11e. The direction from the first partial region 11a to the first electrode 51 is along the first direction D1. The direction from the second partial region 11b to the second electrode 52 is along the first direction D1. The third partial region 11c is between the first partial region 11a and the second partial region 11b in the second direction D2. The direction from the third partial region 11c to the third electrode 53 is along the first direction D1.

The position of the fourth partial region 11d in the second direction D2 is between the position of the first partial region 11a in the second direction D2 and the position of the third partial region 11c in the second direction D2. The position of the fifth partial region 11e in the second direction D2 is between the position of the third partial region 11c in the second direction D2 and the position of the second partial region 11b in the second direction D2.

The second nitride region 12 includes a sixth sub-region 12f and a seventh sub-region 12g. The direction from the fourth sub-region 11d to the sixth sub-region 12f is along the first direction D1. The direction from the fifth sub-region 11e to the seventh sub-region 12g is along the first direction D1.

For example, the current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential based on the potential of the first electrode 51. The first electrode 51 functions, for example, as a source electrode. The second electrode 52 functions, for example, as a drain electrode. The third electrode 53 functions, for example, as a gate electrode. The semiconductor device 120 is, for example, a transistor.

The first nitride region 11 includes a portion corresponding to the second nitride region 12. A carrier region is formed in this portion. The carrier region is, for example, a two-dimensional electron gas. The semiconductor device 120 is, for example, a HEMT (High Electron Mobility Transistor).

As shown in FIG. 13, at least a portion 61p of the insulating member 61 is provided between the nitride layer 10L and the third electrode 53. The insulating member 61 is provided as necessary and may be omitted.

In the semiconductor device 120, at least a portion of the third electrode 53 is provided between the sixth partial region 12f and the seventh partial region 12g in the second direction D2. At least a portion of the third electrode 53 may be provided between the fourth partial region 11d and the fifth partial region 11e in the second direction D2. In the semiconductor device 120, for example, normally-off characteristics are obtained.

FIG. 14 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment.
14, a semiconductor device 121 according to the embodiment also includes a wafer 110, a first electrode 51, a second electrode 52, and a third electrode 53. In the semiconductor device 121, a second nitride region 12 is provided between the third partial region 11c and the third electrode 53 in the first direction D1. In the semiconductor device 121, a normally-on operation is obtained.

In the semiconductor devices 120 and 121 according to the embodiment, for example, low on-resistance is easily obtained based on high crystallinity. Cracks are suppressed.

In an embodiment, information regarding shape, etc., is obtained, for example, by observation using an electron microscope. Information regarding composition and element concentration may be obtained, for example, by EDX (Energy Dispersive X-ray Spectroscopy) or SIMS (Secondary Ion Mass Spectrometry).

The embodiment may include the following configurations (e.g., technical solutions).
(Configuration 1)
A silicon substrate;
a first layer comprising aluminum and nitrogen;
a plurality of structures provided between a portion of the silicon substrate and a portion of the first layer in a first direction from the silicon substrate to the first layer;
Equipped with
The plurality of structures include a first element including at least one selected from the group consisting of Ni, Cu, Cr, Mn, Fe, and Co, and silicon;
Another portion of the first layer contacts another portion of the silicon substrate.

(Configuration 2)
the silicon substrate includes a first silicon region, a second silicon region, and a third silicon region;
In the first direction, the plurality of structures are provided between the first silicon region and the first layer,
2. The wafer of claim 1, wherein in a direction intersecting the first direction, one of the plurality of structures is between the second silicon region and the third silicon region.

(Configuration 3)
the second silicon region includes a substrate surface facing the first layer;
the one of the plurality of structures includes a structure surface facing the first layer;
3. The wafer of claim 2, wherein the position of the substrate surface in the first direction coincides with the position of the structure surface in the first direction.

(Configuration 4)
4. The wafer of claim 2 or 3, wherein a structure thickness of the one of the plurality of structures along the first direction is thinner than a first layer thickness of the first layer along the first direction.

(Configuration 5)
5. The wafer of claim 4, wherein the structure thickness is 5 nm or more and 30 nm or less.

(Configuration 6)
6. The wafer according to any one of configurations 2 to 5, wherein the length of one of the plurality of structures in a direction perpendicular to the first direction is 200 nm or more and 5000 nm or less.

(Configuration 7)
7. The wafer according to any one of configurations 2 to 6, wherein a density of the plurality of structures in a plane perpendicular to the first direction is 2×10 ³ /cm ² or more and 2×10 ⁵ /cm ² or less.

(Configuration 8)
the one of the plurality of structures includes a structure side facing the second silicon region;
8. A wafer according to any one of configurations 2 to 7, wherein the structure side surface is inclined with respect to the first direction.

(Configuration 9)
the one of the plurality of structures includes a structure side facing the second silicon region;
8. The wafer according to any one of configurations 2 to 7, wherein the structure side faces are aligned along a crystal plane of the silicon substrate.

(Configuration 10)
10. The wafer of claim 9, wherein the structure side is along a (111) plane of the silicon substrate.

(Configuration 11)
11. The wafer of any one of configurations 1 to 10, wherein the plurality of structures includes crystals.

(Configuration 12)
12. The wafer of any one of configurations 1 to 11, wherein the plurality of structures are island-shaped.

(Configuration 13)
13. The wafer of any one of configurations 1 to 12, wherein the plurality of structures includes a compound including Ni and silicon.

(Configuration 14)
an intermediate region provided between the plurality of structures and the portion of the first layer;
the intermediate region comprises Al, N and Si;
14. The wafer of any one of configurations 1 to 13, wherein the intermediate region does not contain the first element, or the concentration of the first element in the intermediate region is lower than the concentration of the first element in the plurality of structures.

(Configuration 15)
the intermediate region comprises carbon;
15. The wafer of claim 14, wherein the first layer is carbon-free or the concentration of carbon in the first layer is lower than the concentration of carbon in the intermediate region.

(Configuration 16)
the intermediate region comprises carbon;
15. The wafer of claim 14, wherein the plurality of structures are carbon-free or the concentration of carbon in the plurality of structures is lower than the concentration of carbon in the intermediate region.

(Configuration 17)
Further comprising a nitride layer;
the first layer is disposed between the silicon substrate and the nitride layer;
17. The wafer of any one of configurations 1 to 16, wherein the nitride layer contains at least one selected from the group consisting of Al and Ga, and nitrogen.

(Configuration 18)
18. A wafer according to claim 17,
A first electrode;
A second electrode;
A third electrode;
Equipped with
The nitride layer is
a first nitride region including Al _x1 Ga _1-x1 N (0≦x1<1);
a second nitride region comprising Al _x2 Ga _1-x2 N (0<x2≦1, x1<x2);
Including,
the first nitride region is provided between the first layer and the second nitride region;
a direction from the first electrode to the second electrode is along a second direction intersecting the first direction;
a position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction,
the first nitride region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region;
A direction from the first partial region to the first electrode is along the first direction,
a direction from the second partial region to the second electrode is along the first direction;
the third partial region is between the first partial region and the second partial region in the second direction, and a direction from the third partial region to the third electrode is along the first direction;
a position of the fourth partial region in the second direction is between the position of the first partial region in the second direction and the position of the third partial region in the second direction,
a position of the fifth partial region in the second direction is between a position of the third partial region in the second direction and the position of the second partial region in the second direction;
the second nitride region includes a sixth sub-region and a seventh sub-region,
a direction from the fourth partial region to the sixth partial region is along the first direction;
A semiconductor device, wherein a direction from the fifth partial region to the seventh partial region is along the first direction.

(Configuration 19)
Further comprising an insulating member;
19. The semiconductor device of configuration 18, wherein at least a portion of the insulating member is provided between the nitride layer and the third electrode.

(Configuration 20)
20. The semiconductor device of structure 18 or 19, wherein at least a portion of the third electrode is between the sixth partial region and the seventh partial region in the second direction.

In the wafer 110, the tensile stress occurring when the temperature is lowered from a high temperature to room temperature can be reduced. The lattice constant of the (111) plane of the silicon substrate 15 may be 0.384 nm. The lattice constant of the a-axis of the first layer 17 (AlN) may be 0.311 nm. The lattice constant of the (111) plane of NiSi ₂ may be 0.382 nm. The lattice constant of NiSi ₂ is equal to the lattice constant of the silicon substrate 15. The values of the lattice constants are values at room temperature. The multiple structures 16 may include, for example, a compound of Mn and silicon.

The plurality of first films 14a include, for example, Al _z1 Ga _1-z1 N (0<z1≦1). The composition ratio z1 is, for example, 0.75 or more and 1 or less. In one example, the plurality of first films 14a are AlN layers. The plurality of second films 14b include, for example, Al _z2 Ga _1-21 N (0≦z2<1, z2<z1). The composition ratio z2 is, for example, 0.05 or more and 0.3 or less. In one example, the plurality of second films 14b are, for example, Al _0.13 Ga _0.87 N layers.

According to the embodiment, it is possible to provide a wafer and a semiconductor device that can improve characteristics.

In this specification, "electrically connected" includes a state in which multiple conductors are physically in contact with each other and current flows between the multiple conductors. "Electrically connected" includes a state in which a conductor is inserted between multiple conductors and current flows between the multiple conductors.

Above, the embodiments of the present invention have been described with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of each element included in the wafer, such as the substrate, layers, and structures, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting from the known range.

In addition, any combination of two or more elements of each specific example, within the scope of technical feasibility, is also included in the scope of the present invention as long as it includes the gist of the present invention.

In addition, all wafers and semiconductor devices that can be implemented by a person skilled in the art through appropriate design modifications based on the wafers and semiconductor devices described above as embodiments of the present invention also fall within the scope of the present invention, so long as they include the gist of the present invention.

In addition, within the scope of the concept of this invention, a person skilled in the art may conceive of various modifications and alterations, and these modifications and alterations are also considered to fall within the scope of this invention.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims.

10L: nitride layer, 11, 12: first and second nitride regions, 11a to 11e: first to fifth partial regions, 12f, 12g: sixth and seventh partial regions, 13: AlGaN layer, 14: stacked structure, 14a, 14b: first and second films, 15: silicon substrate, 15a to 15c: first to third silicon regions, 15f: substrate surface, 16: structure, 16L: structure length, 16M: intermediate region, 16f: structure surface, 16s: structure side surface, 17: first layer, 51 to 53: first to third electrodes, 61: insulating member, 61p: part, 110: wafer, 120, 121: semiconductor device, C(B), C1: concentration, D1, D2: first and second directions, P1 to P5: 1st to 5th positions, Q1, Q2: region, pZ: position, t16: structure thickness, t17: first layer thickness

Claims (20)

A silicon substrate;
a first layer comprising aluminum and nitrogen;
a plurality of structures provided between a portion of the silicon substrate and a portion of the first layer in a first direction from the silicon substrate to the first layer;
Equipped with
The plurality of structures include a first element including at least one selected from the group consisting of Ni, Cu, Cr, Mn, Fe, and Co, and silicon;
Another portion of the first layer contacts another portion of the silicon substrate. the silicon substrate includes a first silicon region, a second silicon region, and a third silicon region;
In the first direction, the plurality of structures are provided between the first silicon region and the first layer,
The wafer of claim 1 , wherein in a direction intersecting the first direction, one of the plurality of structures is between the second silicon region and the third silicon region. the second silicon region includes a substrate surface facing the first layer;
the one of the plurality of structures includes a structure surface facing the first layer;
The wafer according to claim 2 , wherein a position of the substrate surface in the first direction coincides with a position of the structure surface in the first direction. The wafer of claim 2, wherein the structure thickness of one of the plurality of structures along the first direction is thinner than the first layer thickness of the first layer along the first direction. The wafer according to claim 4, wherein the structure thickness is 5 nm or more and 30 nm or less. The wafer according to claim 2, wherein the length of one of the structures in a direction perpendicular to the first direction is 200 nm or more and 5000 nm or less. The wafer according to claim 2 , wherein a density of the plurality of structures in a plane perpendicular to the first direction is not less than 2×10 ³ /cm ² and not more than 2×10 ⁵ /cm ² . the one of the plurality of structures includes a structure side facing the second silicon region;
8. The wafer according to claim 2, wherein the side surface of the structure is inclined with respect to the first direction. the one of the plurality of structures includes a structure side facing the second silicon region;
8. The wafer according to claim 2, wherein the side surface of the structure is aligned along a crystal plane of the silicon substrate. The wafer according to claim 9, wherein the side surface of the structure is aligned along the (111) surface of the silicon substrate. The wafer of claim 1, wherein the plurality of structures includes crystals. The wafer of claim 1, wherein the plurality of structures are island-shaped. The wafer of claim 1, wherein the plurality of structures includes a compound containing Ni and silicon. an intermediate region provided between the plurality of structures and the portion of the first layer;
the intermediate region comprises Al, N and Si;
The wafer according to claim 1 , wherein the intermediate region does not contain the first element, or the concentration of the first element in the intermediate region is lower than the concentration of the first element in the plurality of structures. the intermediate region comprises carbon;
15. The wafer of claim 14, wherein the first layer is carbon-free or the concentration of carbon in the first layer is lower than the concentration of carbon in the intermediate region. the intermediate region comprises carbon;
The wafer of claim 14 , wherein the plurality of structures does not contain carbon, or the concentration of carbon in the plurality of structures is lower than the concentration of carbon in the intermediate region. Further comprising a nitride layer;
the first layer is disposed between the silicon substrate and the nitride layer;
The wafer of claim 1 , wherein the nitride layer comprises at least one selected from the group consisting of Al and Ga, and nitrogen. A wafer according to claim 17;
A first electrode;
A second electrode;
A third electrode;
Equipped with
The nitride layer is
a first nitride region including Al _x1 Ga _1-x1 N (0≦x1<1);
a second nitride region comprising Al _x2 Ga _1-x2 N (0<x2≦1, x1<x2);
Including,
the first nitride region is provided between the first layer and the second nitride region;
a direction from the first electrode to the second electrode is along a second direction intersecting the first direction;
a position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction,
the first nitride region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region;
A direction from the first partial region to the first electrode is along the first direction,
a direction from the second partial region to the second electrode is along the first direction;
the third partial region is between the first partial region and the second partial region in the second direction, and a direction from the third partial region to the third electrode is along the first direction;
a position of the fourth partial region in the second direction is between the position of the first partial region in the second direction and the position of the third partial region in the second direction,
a position of the fifth partial region in the second direction is between a position of the third partial region in the second direction and the position of the second partial region in the second direction;
the second nitride region includes a sixth sub-region and a seventh sub-region,
a direction from the fourth partial region to the sixth partial region is along the first direction;
A semiconductor device, wherein a direction from the fifth partial region to the seventh partial region is along the first direction. Further comprising an insulating member;
The semiconductor device according to claim 18 , wherein at least a portion of the insulating member is provided between the nitride layer and the third electrode. The semiconductor device according to claim 18, wherein at least a portion of the third electrode is between the sixth partial region and the seventh partial region in the second direction.

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