JP2024158715A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

To provide a semiconductor device with a small occupancy area.SOLUTION: A semiconductor device includes a transistor, a first insulation layer, a second insulation layer and a material layer. A source electrode and a drain electrode of the transistor are provided in contact with the upper surface of the first insulation layer. The second insulation layer is provided over the source electrode, the drain electrode, and the first insulation layer. The first insulation layer and the second insulation layer have recesses in the regions overlapping the source electrode and the drain electrode. The source electrode and the drain electrode have exposed regions within the recesses. A semiconductor layer of the transistor has a region that comes into contact with the side surface of the second insulation layer, the side surface of the source electrode and the side surface of the drain electrode within the recesses. The material layer is provided on the bottom surface of the recess. The gate insulation layer of the transistor is provided in contact with the side surface of the semiconductor layer and the upper surface of the material layer. The gate electrode of the transistor is provided on the gate insulation layer so as to have a region overlapping the recess. The semiconductor layer and the material layer are made of the same material and are electrically insulated from each other.SELECTED DRAWING: Figure 1

Description

One aspect of the present invention relates to a semiconductor device and a manufacturing method thereof. One aspect of the present invention relates to a transistor and a manufacturing method thereof. One aspect of the present invention relates to a display device having a semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), electronic devices having them, driving methods thereof, or manufacturing methods thereof.

In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

Semiconductor devices having transistors are widely used in electronic devices. In recent years, the uses of display devices have become more diverse, and display devices are used in, for example, mobile information terminals, television devices (also called television receivers), digital signage, and public information displays (PIDs). Examples of display devices include display devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs), display devices having liquid crystal elements, and electronic paper that displays using an electrophoretic method.

In display devices, by reducing the area occupied by transistors, the pixel size can be reduced and the resolution can be increased. In addition, by reducing the area occupied by transistors, the aperture ratio can be increased. For this reason, there is a demand for miniaturized transistors.

Devices requiring high-definition display devices, such as those for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), are being actively developed.

Patent document 1 discloses a high-definition display device that uses organic EL elements.

International Publication No. 2016/038508

One aspect of the present invention has an object to provide a transistor with a fine size. Or, an object to provide a transistor with a long channel length. Or, an object to provide a transistor with a long channel length and a transistor with a short channel length. Or, an object to provide a transistor with good electrical characteristics. Or, an object to provide a semiconductor device with a small occupancy area. Or, an object to provide a semiconductor device or display device with low power consumption. Or, an object to provide a highly reliable transistor, semiconductor device, or display device. Or, an object to provide a display device that can be easily made high-definition. Or, an object to provide a method for manufacturing a transistor or semiconductor device with high yield. Or, an object to provide a method for manufacturing a semiconductor device or display device with high productivity. Or, an object to provide a novel transistor, semiconductor device, or display device, or a manufacturing method thereof.

The description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

One aspect of the present invention includes a transistor, a first insulating layer, a second insulating layer, and a material layer, the source electrode and drain electrode of the transistor being provided in contact with an upper surface of the first insulating layer, the second insulating layer being provided on the source electrode, the drain electrode, and the first insulating layer, and having an opening in a region overlapping with the source electrode and the drain electrode in a planar view, the first insulating layer having a recess in a region overlapping with the opening in a planar view, the source electrode and the drain electrode having an exposed region in a region overlapping with the recess in a planar view, and the sidewall of the recess is an end of the source electrode in a region overlapping with the source electrode and the drain electrode in a planar view. and the drain electrode, and in a region that does not overlap with the source electrode and drain electrode in a plan view, the semiconductor layer of the transistor has a region that contacts the side of the second insulating layer in the opening, the side of the source electrode, and the side of the drain electrode, the material layer is provided on the bottom surface of the recess, the gate insulating layer of the transistor is provided in contact with the semiconductor layer and the material layer, and the gate electrode of the transistor is provided on the gate insulating layer so as to have a region that overlaps with the recess in a plan view, the semiconductor layer and the material layer are made of the same material and are provided separately from each other.

In the above, it is also preferable that the semiconductor layer contains a metal oxide.

In the above, the second insulating layer has a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer, and the third insulating layer and the fifth insulating layer are one or more of silicon nitride, silicon nitride oxide, or aluminum oxide, and the fourth insulating layer is preferably one or more of silicon oxide or silicon oxynitride.

In the above, it is also preferable that the side surface of the source electrode and the side surface of the drain electrode protrude beyond the side surface of the second insulating layer within the opening.

In the above, it is also preferable that the side surfaces of the source electrode and the drain electrode roughly coincide with the side surfaces of the second insulating layer within the opening.

In the above, it is also preferable that the side surface of the recess in the second insulating layer is perpendicular or approximately perpendicular to the upper surface of the first insulating layer.

In the above, it is also preferable that the side surface of the second insulating layer within the opening has a tapered shape relative to the upper surface of the first insulating layer.

In the above, the second insulating layer has a third insulating layer, a fourth insulating layer on the third insulating layer, a fifth insulating layer on the fourth insulating layer, a sixth insulating layer on the fifth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, and the third insulating layer, the fifth insulating layer, the sixth insulating layer, and the eighth insulating layer are one or more of silicon nitride, silicon nitride oxide, or aluminum oxide, and the fourth insulating layer and the seventh insulating layer are one or more of silicon oxide or silicon oxide nitride, and it is preferable that there is a conductive layer between the fifth insulating layer and the sixth insulating layer.

Another aspect of the present invention is to form a first insulating layer, form a first conductive layer and a second conductive layer on the first insulating layer, form a second insulating layer on the first insulating layer, the first conductive layer, and the second conductive layer, process the first insulating layer and the second insulating layer to form recesses in the first insulating layer and the second insulating layer so as to have areas overlapping with the first conductive layer and the second conductive layer in a planar view, form a metal oxide film on the first insulating layer and the second insulating layer so as to cover the recesses, and apply a photoresist on the metal oxide film so as to fill the recesses. This is a method for manufacturing a semiconductor device, which includes applying a photoresist, irradiating the photoresist with light, removing the irradiated portions of the photoresist to form a resist mask, removing the exposed portions of the metal oxide film, forming a semiconductor layer in contact with the side surfaces of the second insulating layer, the side surfaces of the first conductive layer, and the side surfaces of the second conductive layer in the recess, removing the resist mask remaining in the recess, forming a third insulating layer on the semiconductor layer so as to cover the recess, and forming a third conductive layer on the third insulating layer so as to have an area that overlaps with the recess in a plan view.

According to one embodiment of the present invention, a transistor having a fine size can be provided. Or, a transistor having a long channel length can be provided. Or, a transistor having a long channel length and a transistor having a short channel length can be provided. Or, a transistor having good electrical characteristics can be provided. Or, a semiconductor device having a small occupancy area can be provided. Or, a semiconductor device or display device having low power consumption can be provided. Or, a highly reliable transistor, semiconductor device, or display device can be provided. Or, a display device that can be easily made high-definition can be provided. Or, a method for manufacturing a transistor or semiconductor device with high yield can be provided. Or, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Or, a novel transistor, semiconductor device, display device, or a manufacturing method thereof can be provided.

The description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have to have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

1A is a schematic perspective view of a transistor, and FIG 1B is a schematic plan view of the transistor. 2A and 2B are cross-sectional views of a transistor. 3A to 3C are schematic plan views of a transistor. 4A and 4B are schematic plan views of a transistor. 5A is a schematic plan view of a transistor, and FIG 5B is a cross-sectional view of the transistor. 6A to 6C are schematic plan views of a transistor. Fig. 7A is a plan view showing an example of a semiconductor device, and Fig. 7B and Fig. 7C are cross-sectional views showing the example of the semiconductor device. 8A is a plan view showing an example of a semiconductor device, and FIG 8B is a cross-sectional view showing the example of the semiconductor device. 9A is a plan view showing an example of a semiconductor device, and FIG 9B is a cross-sectional view showing the example of the semiconductor device. 10A and 10B are cross-sectional views showing an example of a semiconductor device. 11A and 11B are cross-sectional views showing an example of a semiconductor device. 12A and 12B are cross-sectional views showing an example of a semiconductor device. 13A to 13C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. 14A to 14C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. 15A to 15C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. 16A to 16C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. 17A to 17C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. 18A to 18C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. 19A to 19C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. 20A to 20C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. 21A to 21C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. Fig. 22A is a perspective view showing an example of a display device, and Fig. 22B is a block diagram showing an example of the display device. 23A is a circuit diagram of a latch circuit, and FIG 23B is a circuit diagram of an inverter circuit. 24A and 24B are circuit diagrams of a pixel circuit, and Fig. 24C is a cross-sectional view showing an example of a pixel circuit. FIG. 25 is a schematic cross-sectional view showing a configuration example of a display device. 26A and 26B are diagrams illustrating an example of the configuration of an electronic device. 27A and 27B are diagrams illustrating an example of the configuration of an electronic device. 28A and 28B are diagrams illustrating a configuration example of a display device. FIG. 29 is a diagram illustrating an example of the configuration of a display device. 30A to 30C are perspective views of a display module. 31A and 31B are diagrams illustrating a configuration example of a display device. 32A to 32D are diagrams illustrating examples of the structure of a display device. 33A to 33D are diagrams illustrating examples of the structure of a display device. 34A and 34B are diagrams illustrating a configuration example of a display device. 35A to 35D are diagrams illustrating examples of the configuration of a display device. 36A to 36C are diagrams illustrating examples of the structure of a display device. 37A to 37F are diagrams showing examples of electronic devices. 38A to 38G are diagrams showing examples of electronic devices. Fig. 39A is a diagram illustrating a sub-display portion, and Figs. 39B1 to 39B7 are diagrams illustrating examples of pixel configurations. 40A to 40G are diagrams illustrating examples of pixel configurations. 41A to 41D are diagrams illustrating configuration examples of a light-emitting device. Fig. 42(A) is an optical microscope photograph according to this example, and Fig. 42(B) and Fig. 42(C) are cross-sectional STEM images according to this example. 43(A) and 43(B) are cross-sectional STEM images according to this example.

The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will easily understand that the form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations will be omitted. Also, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

In this specification, etc., when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m,n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m,n]" is added to the reference numeral in the drawings, etc., when it is not necessary to distinguish between them in this specification, etc., the identification symbol may not be added.

For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. For this reason, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). In addition, an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.

Note that the words "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conduction. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

The functions of "source" and "drain" may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Note that the source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, depending on the situation.

The terms "gate" and "backgate" can be used interchangeably. For this reason, in this specification and the like, the terms "gate" and "backgate" can be used interchangeably. Note that the names of the gate and backgate of a transistor can be appropriately changed depending on the situation, such as gate electrode and backgate electrode.

In this specification, "electrically connected" includes a connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, capacitive elements, and other elements with various functions.

In this specification and the like, the term "electrically insulated" means that the magnitude of the current flowing between the two objects to be measured is 1×10 ⁻²⁴ A or less.

In this specification and the like, unless otherwise specified, the off-state current refers to leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off state refers to a state in which the voltage _Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage _Vth (higher than _Vth for a p-channel transistor).

In this specification, "top surface shapes roughly match" means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, in which case it may also be said that "top surface shapes roughly match." Furthermore, when the top surface shapes match or roughly match, it can also be said that the ends are aligned or roughly aligned.

In this specification, a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, it refers to a shape having an area in which the angle (also called the taper angle) between the inclined side and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.

In this specification, etc., a device manufactured using a metal mask or FMM (fine metal mask, high-definition metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device manufactured without using a metal mask or FMM may be referred to as a device with an MML (metal maskless) structure. Note that since a device with an MML structure can be manufactured without using a metal mask, it is possible to exceed the upper limit of the definition caused by the alignment accuracy of the metal mask. Furthermore, a device with an MML structure can eliminate the need for equipment related to the manufacturing of the metal mask and the cleaning process of the metal mask. Furthermore, a device with an MML structure is suitable for mass production because it is possible to keep manufacturing costs low.

In this specification, a structure in which different light-emitting layers are created for light-emitting devices (also called light-emitting elements) with different emission wavelengths may be referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting device, increasing the freedom of material and configuration selection and making it easier to improve brightness and reliability.

In this specification and the like, holes or electrons may be referred to as "carriers". Specifically, the hole injection layer or electron injection layer may be referred to as the "carrier injection layer", the hole transport layer or electron transport layer may be referred to as the "carrier transport layer", and the hole block layer or electron block layer may be referred to as the "carrier block layer". Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other due to their cross-sectional shapes or characteristics. Also, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

In this specification, the light-emitting device has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, the layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). In this specification, the light-receiving element (also called a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

In this specification, the sacrificial layer (which may also be referred to as a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that make up the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

In this specification, "approximately the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as the surface of a substrate) are approximately the same in a cross-sectional view. In addition, in this specification, "approximately the same" includes both a perfect match and an approximate match.

In this specification, step discontinuity refers to a phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step, etc.).

In this specification, perpendicular means that two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, this also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, roughly perpendicular means that two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

(Embodiment 1)
In this embodiment, a structure example of a semiconductor device of one embodiment of the present invention will be described.

A semiconductor device according to one embodiment of the present invention includes a transistor, a first insulating layer, a second insulating layer, and a material layer. The transistor is provided on the first insulating layer. The source electrode and drain electrode of the transistor are provided in contact with the upper surface of the first insulating layer. The second insulating layer is provided on the source electrode and drain electrode of the transistor and on the first insulating layer.

The second insulating layer has an opening in a region overlapping the transistor. In the opening, at least a portion of the source electrode and drain electrode of the transistor are exposed. In addition, the first insulating layer has a recess in a region overlapping the opening. In the recess, at least a portion of the source electrode and drain electrode of the transistor (more specifically, a portion of the bottom surface) is exposed.

A semiconductor layer of the transistor is provided in contact with the side surface of the opening in the second insulating layer. The semiconductor layer has an area in contact with the source electrode and drain electrode of the transistor within the opening.

A material layer is provided on the bottom surface of the recess in the first insulating layer. The material layer is made of the same material as the semiconductor layer of the transistor. Therefore, the semiconductor layer of the transistor may be called the "first semiconductor layer" and the material layer may be called the "second semiconductor layer." The semiconductor layer and the material layer are provided separately from each other. In other words, the semiconductor layer and the material layer are electrically insulated. The semiconductor layer (first semiconductor layer) is a layer that corresponds to a part of the transistor, while the material layer (second semiconductor layer) is a layer that does not correspond to a part of the transistor.

Therefore, in a semiconductor device according to one embodiment of the present invention, a region of the semiconductor layer that is in contact with the opening of the second insulating layer and is located between the source electrode and the drain electrode can function as a channel formation region of the transistor. In this case, the distance between the source electrode and the drain electrode along this region corresponds to the channel length of the transistor, and the depth (height) of this region corresponds to the channel width of the transistor. Therefore, by adjusting the film thickness of the second insulating layer, the size of the channel width of the transistor changes, and therefore the size of the on-current of the transistor can be adjusted.

For example, the thinner the second insulating layer, the smaller the channel width of the transistor, and the smaller the ratio of the channel width to the channel length of the transistor can be. This allows the on-current of the transistor to be reduced. Conversely, the thicker the second insulating layer, the larger the channel width of the transistor, and the larger the ratio of the channel width to the channel length of the transistor can be. This allows the on-current of the transistor to be increased.

As described above, in a semiconductor device according to one embodiment of the present invention, in a plan view, a part of the source electrode and the drain electrode of the transistor are exposed in the recess of the first insulating layer and in the opening of the second insulating layer. Therefore, when the film that becomes the semiconductor layer is formed in the opening and in the recess, the film that becomes the semiconductor layer is stepped at the ends of the exposed source electrode and the drain electrode. As a result, the semiconductor layer that contacts the side of the opening and the material layer that contacts the bottom of the recess can be formed simultaneously and in a self-aligned manner. Therefore, after the film that becomes the semiconductor layer is formed, a separate process of processing the film into a semiconductor layer is not required, and the overall number of steps in the manufacture of the semiconductor device can be reduced.

In addition, when multiple semiconductor devices are manufactured within a substrate plane, the angle between the side of the opening in the second insulating layer and the substrate surface may vary for each semiconductor device. For example, the angle may be approximately 90 degrees in one semiconductor device within the substrate plane, whereas the angle may be a taper angle in another semiconductor device. In such a case, after a process for forming a semiconductor layer in contact with the side of the opening in the second insulating layer (for example, an anisotropic etching process performed after forming a film that becomes the semiconductor layer), a problem may occur in which the semiconductor layer cannot be formed well depending on the semiconductor device. On the other hand, with the configuration of the semiconductor device according to one embodiment of the present invention, even if the angle varies between semiconductor devices, the semiconductor layer of each semiconductor device can be formed with high precision. Therefore, a method for manufacturing a semiconductor device with a high yield can be provided.

A gate insulating layer of the transistor is provided in the opening of the second insulating layer and in the recess of the first insulating layer, in contact with the side surface of the semiconductor layer of the transistor and the top surface of the material layer.

A gate electrode of the transistor is provided in contact with the upper surface of the gate insulating layer so as to have a region that overlaps with the opening of the second insulating layer in a plan view. The gate electrode is provided in the opening so as to have a region that faces the semiconductor layer through the gate insulating layer.

Below, a configuration example of a semiconductor device according to one embodiment of the present invention (mainly a configuration example of a transistor included in the semiconductor device) will be described with reference to the drawings.

<Configuration Example 1>
FIG 1A shows a schematic perspective view of a transistor 20 included in a semiconductor device of one embodiment of the present invention. FIG 1B shows a schematic plan view (also referred to as a schematic top view) of the transistor 20. FIG 2A shows a schematic cross-sectional view taken along dashed line A-B in FIG 1A. FIG 2B shows a schematic cross-sectional view taken along dashed line C-D in FIG 1A. Note that some components (such as a conductive layer 23, an insulating layer 22, and a material layer 21m) are omitted in FIGS. 1A and 1B. FIG 1A shows the conductive layer 24a and the conductive layer 24b through an insulating layer 32.

The transistor 20 is provided on the insulating layer 31. The transistor 20 has a semiconductor layer 21, an insulating layer 22, a conductive layer 23, a conductive layer 24a, and a conductive layer 24b.

In the transistor 20, the semiconductor layer 21 functions as a semiconductor layer having a channel formation region. The insulating layer 22 functions as a gate insulating layer (first gate insulating layer). The conductive layer 23 functions as a gate electrode (first gate electrode). The conductive layer 24a functions as one of the source electrode and the drain electrode. The conductive layer 24b functions as the other of the source electrode and the drain electrode.

Conductive layer 24a and conductive layer 24b are provided on insulating layer 31. Furthermore, insulating layer 32 is provided on insulating layer 31. In insulating layer 31 and insulating layer 32, recess 30 is provided so as to have an area overlapping at least a part of conductive layer 24a and conductive layer 24b in a plan view. In other words, a part of conductive layer 24a and a part of conductive layer 24b are provided so as to protrude from the side wall of recess 30 (which may refer to the side surface of recess 30 or the side surface of insulating layer 32 in recess 30). Recess 30 penetrates insulating layer 32 and has a bottom surface in the film of insulating layer 31. In other words, the bottom surface of recess 30 is located lower (substrate surface side) than the lower surfaces of conductive layer 24a and conductive layer 24b. The opening formed in insulating layer 32 and the recess on insulating layer 31 formed at a position overlapping the opening can be collectively referred to as recess 30.

As shown in FIG. 1(A) and FIG. 1(B), the semiconductor layer 21 is provided along the periphery of the recess 30 (which may also be referred to as the side surface of the recess 30). Here, in the region overlapping with the conductive layer 24a and the conductive layer 24b in a planar view, as shown in FIG. 2(A), the semiconductor layer 21 has a region in contact with the side surface of the insulating layer 32 in the recess 30, the upper surface and the side surface of the conductive layer 24a in the recess 30, and the upper surface and the side surface of the conductive layer 24b in the recess 30. Also, in the region not overlapping with the conductive layer 24a and the conductive layer 24b in a planar view, as shown in FIG. 2(B), the semiconductor layer 21 has a region in contact with the side surface of the insulating layer 32 in the recess 30.

A material layer 21m is provided on the bottom surface of the recess 30. The material layer 21m is a layer made of the same material as the semiconductor layer 21. In the semiconductor device of one embodiment of the present invention, as shown in FIG. 2A, the ends of the conductive layer 24a and the conductive layer 24b protrude in the recess 30. That is, the ends of the conductive layer 24a and the conductive layer 24b are located closer to the inside of the recess 30 than the sidewall of the opening formed in the insulating layer 32 and the sidewall of the recess formed in the insulating layer 31. Therefore, when the film that becomes the semiconductor layer 21 and the material layer 21m is formed in the recess 30, the film is cut at the exposed ends of the conductive layer 24a and the conductive layer 24b. As a result, the semiconductor layer 21 in contact with the side of the insulating layer 32 in the recess 30, and the top and side surfaces of the conductive layers 24a and 24b in the recess 30, and the material layer 21m in contact with the bottom surface of the recess 30 are each formed separately.

As shown in FIG. 2B, in the region of the recess 30 that does not overlap with the conductive layer 24a and the conductive layer 24b, the sidewall of the recess formed in the insulating layer 31 is positioned outward from the sidewall of the opening formed in the insulating layer 32. Therefore, when the film that becomes the semiconductor layer 21 and the material layer 21m is formed in the recess 30 in this region, the film is cut at the bottom end of the opening formed in the insulating layer 32. As a result, the semiconductor layer 21 that contacts the side surface of the insulating layer 32 in the recess 30 and the material layer 21m that contacts the bottom surface of the recess 30 are formed separately.

In other words, in one aspect of the present invention, two island-shaped layers (semiconductor layer 21 and material layer 21m) can be simultaneously formed in a self-aligned manner by performing only one film formation process.

The insulating layer 22 is provided in the recess 30 in contact with the upper surfaces of the semiconductor layer 21 and the material layer 21m. The recess 30 has a cavity 27 that is filled with the conductive layer 24a or the conductive layer 24b and the insulating layer 22 in the cross section in the YZ plane (FIG. 2(A)), and is filled with the insulating layer 22 in the cross section in the XZ plane (FIG. 2(B)).

However, the configuration of the semiconductor device according to one embodiment of the present invention is not limited to this. The semiconductor device according to one embodiment of the present invention may be configured such that the recess 30 does not have a cavity 27. That is, in the cross section in the YZ plane, the lower surface of the insulating layer 22 contacts the upper surface of the insulating layer 31 in the recess 30 and the lower surfaces of the conductive layers 24a and 24b in the recess 30, and in the cross section in the XZ plane, the lower surface of the insulating layer 31 in the recess 30 and the lower surface of the insulating layer 32 in the recess 30.

As shown in FIG. 2(A) and FIG. 2(B), the insulating layer 22 is provided in the recess 30 so as to fill the gap between the semiconductor layer 21 and the material layer 21m, which is disconnected from the recess 30. This is preferable because it prevents electrical conduction between the semiconductor layer 21 and the material layer 21m and prevents the material layer 21m from becoming a current path between the source electrode and the drain electrode. However, the above is not limited as long as the electrical insulation between the semiconductor layer 21 and the material layer 21m can be maintained. For example, the insulating layer 22 may have a region disconnected from the recess 30 and divided into a portion covering the semiconductor layer 21 and a portion covering the material layer 21m.

The conductive layer 23 is provided on the insulating layer 22 so as to have an area that overlaps with the recess 30 in a plan view. The conductive layer 23 is also provided in the recess 30 so as to have an area that faces the semiconductor layer 21 through the insulating layer 22.

2(A) and 2(B), the conductive layer 23 is configured to completely cover the upper surface of the insulating layer 22 within the recess 30, but this is not limited thereto. For example, the conductive layer 23 may have a step within the recess 30, and may have an area divided into a portion that covers the semiconductor layer 21 and a portion that covers the material layer 21m.

In addition, as long as electrical insulation between the semiconductor layer 21 and the material layer 21m can be maintained, both the insulating layer 22 and the conductive layer 23 may have a stepped area within the recess 30, with each area divided into a portion covering the semiconductor layer 21 and a portion covering the material layer 21m.

In addition, if the insulating layer 22 is disconnected within the recess 30, the semiconductor layer 21 and the conductive layer 23 may come into contact with each other at the disconnected portion. In this case, the transistor 20 will not be able to perform normal transistor operation. Therefore, even if the insulating layer 22 is disconnected, the semiconductor layer 21 and the conductive layer 23 are required to at least maintain a state in which they do not contact each other (preferably, are electrically insulated).

Here, the channel length of the transistor 20 corresponds to the distance between the conductive layer 24a and the conductive layer 24b in the circumferential direction of the semiconductor layer 21 provided on the side wall of the recess 30. Here, as shown in FIG. 1B, since the ring-shaped semiconductor layer 21 is provided over the entire side wall of the recess 30, there are two paths connecting the conductive layer 24a and the conductive layer 24b in the semiconductor layer 21, and the length of one of them can be the channel length L1 and the length of the other can be the channel length L2. By arranging the conductive layer 24a and the conductive layer 24b symmetrically with respect to the center of the recess 30 in a plan view, the channel length L1 and the channel length L2 can be made equal. For example, as shown in FIG. 1B, the upper surface shape of the recess 30 is made approximately circular (also called a square shape with rounded corners), and the conductive layer 24a and the conductive layer 24b are provided at both ends, so that the channel length L1 and the channel length L2 can be made equal relatively easily.

Meanwhile, the channel width W (the width of the region that can function as the channel width) of the transistor 20 corresponds to the width (length) of the semiconductor layer 21 along the depth direction of the recess 30 in the region that overlaps with the conductive layers 24a and 24b in a plan view. Also, as shown in FIG. 1B, when the channel length L1 and the channel length L2 are equal or approximately equal, both paths function as channel formation regions, so that the effective channel width of the transistor 20 may be twice the channel width W.

Because the channel width W can be controlled by the thickness of the insulating layer 32 (and the thickness of the conductive layers 24a and 24b), a transistor with an extremely short channel width can be realized. For example, it is possible to realize a transistor with an extremely small channel width that could not be realized with a mass-production exposure tool. In addition, it is also possible to realize a transistor with a channel width of less than 10 nm without using the extremely expensive exposure tool used in cutting-edge LSI technology.

By adopting such a configuration, the channel width W of the transistor can be precisely controlled by the thickness of the insulating layer 32, so that the variation in the channel width W can be made extremely small. Furthermore, a transistor with an extremely small channel width W can be realized.

Here, the ratio of channel width W to channel length L (W/L ratio) may be used as an index of transistor characteristics. In planar transistors, the minimum values of channel length and channel width depend on the exposure limit of an exposure device, so if the W/L ratio is to be reduced, L must be increased, resulting in a problem of an increased area occupied by the transistor. However, in one embodiment of the present invention, the channel width W can be made smaller than the exposure limit of the exposure device, making it possible to realize a transistor with an extremely small W/L ratio without increasing the area occupied by the transistor.

Here, the top surface shape of the recess 30 (also referred to as the contour shape, planar shape, or shape in plan view) is a square shape with rounded corners, but the present invention is not limited to this. For example, the top surface shape of the recess 30 may be circular as shown in FIG. 3(A), or may be rectangular with rounded corners as shown in FIG. 3(B). By making the top surface shape rectangular as shown in FIG. 3(B), the channel length L can be extended. In this case, it is preferable to arrange the conductive layer 24a and the conductive layer 24b symmetrically with respect to the center of the recess 30 in plan view. In contrast, by making the top surface shape of the recess 30 circular or approximately circular as shown in FIG. 1(B) or FIG. 3(A), the area occupied by the transistor can be reduced. In addition, since the shape of the recess 30 is simple, the variation in shape can be reduced, and the variation in the electrical characteristics of the transistor can be suppressed.

The top surface shape of the recess 30 is not limited to the above and can be various shapes. For example, it can be an ellipse, a rectangle, etc. It can also be a regular polygon such as an equilateral triangle, a square, a regular pentagon, or a polygon other than a regular polygon. If it is a concave polygon with at least one interior angle exceeding 180 degrees, such as a star-shaped polygon, the channel length L can be increased. Other shapes include an ellipse, a polygon with rounded corners, and a closed curve that combines straight lines and curves. For example, the more complex the top surface shape of the recess 30 is, the greater the channel length L can be.

In the above, the configuration in which the ring-shaped semiconductor layer 21 is provided over the entire side wall of the recess 30 has been shown, but the present invention is not limited to this. For example, as shown in FIG. 3(C), the semiconductor layer 21 formed along the side wall of the recess 30 may have a shape in which a part has been removed. For example, in FIG. 3(B), the top surface shape of the semiconductor layer 21 has a closed curved shape, whereas in FIG. 3(C), the top surface shape of the semiconductor layer 21 has an open curved shape. As shown in FIG. 3(C), by providing a conductive layer 24a and a conductive layer 24b near the end of the semiconductor layer 21, the entire semiconductor layer 21 can be made into one channel formation region. Therefore, the channel length of the channel formation region in the semiconductor layer 21 shown in FIG. 3(C) can be made longer than the channel length of each of the two channel formation regions in the semiconductor layer 21 shown in FIG. 3(B).

Also, FIG. 4(A) shows an example in which conductive layer 24a and conductive layer 24b are provided adjacent to each other. With this configuration, semiconductor layer 21 can be provided on most of the sidewall of recess 30. Therefore, the channel length L of the transistor can be made close to the perimeter of recess 30, and a transistor with a long channel length L can be realized. For example, it is desirable for the channel length L to be 70% or more, preferably 80% or more, and more preferably 90% or more of the perimeter of recess 30.

In the above, a configuration in which one transistor is disposed in one recess 30 has been shown, but the present invention is not limited to this. For example, as shown in FIG. 4B, a configuration in which two transistors are disposed in one recess 30 may be used. Here, the semiconductor layer 21a and the semiconductor layer 21b are provided along the sidewall of the recess 30 without contacting each other. As a result, the transistor 20a having the semiconductor layer 21a and the transistor 20b having the semiconductor layer 21b are provided so as to share one recess 30. The transistors 20a and 20b have the same channel width W. The transistors 20a and 20b may have different channel lengths L. Although an example in which two transistors are provided in one recess 30 has been shown here, three or more transistors may be provided.

<Configuration Example 2>
5A and 5B show configuration examples different from Configuration Example 1. Fig. 5A is a schematic plan view of a transistor 20A. Fig. 5B is a schematic cross-sectional view taken along dashed line A-B shown in Fig. 5A. Note that some components (such as the conductive layer 23, the insulating layer 22, and the material layer 21m) are omitted in Fig. 5A.

As shown in FIG. 5A, the transistor 20A is different from the transistor 20 shown in the configuration example 1 mainly in that the recess 30 has a top surface shape that has an extension portion and a bend portion. Here, the top surface shape of the recess 30 formed by combining the extension portion and the bend portion can be called a serpentine shape, a roundabout shape, a meandering shape, or a meandering shape.

As shown in FIG. 5(A), the recess 30 has extensions 26a, 26b, 26c, bends 28a, and 28b. The top surface shape of the recess 30 can be considered as a shape in which the extensions 26a and 26b are connected via bend 28a, and the extensions 26b and 26c are connected via bend 28b.

As shown in Figures 5(A) and 5(B), the semiconductor layer 21 is provided along the side surface of the insulating layer 32 in the recess 30. Furthermore, the semiconductor layer 21 has a region in contact with the conductive layer 24a and a region in contact with the conductive layer 24b. Furthermore, within the recess 30, the semiconductor layer 21 is provided facing the conductive layer 23 via the insulating layer 22.

5(A) and the like show an example in which the semiconductor layer 21 contacts the conductive layer 24a at the extension portion 26a and contacts the conductive layer 24b at the extension portion 26c. The semiconductor layer 21 may be configured to contact the conductive layer 24a or the conductive layer 24b at the bent portion. For example, the semiconductor layer 21 may be configured to contact the conductive layer 24a at the bent portion 28a and contact the conductive layer 24b at the bent portion 28b.

By connecting two extensions with one bend, a folded structure can be formed in the recess 30. By forming one or more such folded shapes, the perimeter of the recess 30 can be made much larger than the distance between the conductive layer 24a and the conductive layer 24b. Therefore, the channel length L can be increased without increasing the area occupied by the transistor. By increasing the channel length L, a transistor with high saturation properties can be obtained. Also, a transistor with an extremely small ratio of the channel width W to the channel length L (W/L ratio) can be realized.

In this specification, the term "high saturation" may be used to describe a transistor's drain current (Id)-drain voltage (Vd) characteristics in which the change in current in the saturation region is small.

Figure 6(A) shows an example of a configuration in which the semiconductor layer 21 is not provided on a portion of the side wall of the recess 30. Figure 6(A) is a schematic plan view of this example.

Figure 6 (A) shows a configuration example in which conductive layer 24a and conductive layer 24b are provided adjacent to each other, and further, semiconductor layer 21 is not provided on the side wall of recess 30 between conductive layer 24a and conductive layer 24b. With such a configuration, the channel length L of the transistor can be made closer to the perimeter of recess 30, and the channel length L can be made longer.

6(A) and other figures show a configuration in which the recess 30 has the extensions 26a, 26b, 26c, the bends 28a, and 28b, but the present invention is not limited to this. The recess 30 may have multiple extensions and at least one bend. Here, it is preferable that the number of bends is one less than the number of extensions. For example, as shown in FIG. 6(B), the recess 30 may have two extensions and one bend. Also, for example, the recess 30 may have four or more extensions and three or more bends. Note that the upper surface of the recess 30 may be rolled as shown in FIG. 6(C).

6A and the like show an example in which the semiconductor layer 21 contacts the conductive layer 24a and the conductive layer 24b in the extension portion 26a, but one embodiment of the present invention is not limited to this. The semiconductor layer 21 may be configured to contact the conductive layer 24a and the conductive layer 24b in the bent portion. Alternatively, the semiconductor layer 21 may be configured to contact one of the conductive layer 24a and the conductive layer 24b in the bent portion and to contact the other of the conductive layer 24a and the conductive layer 24b in the extension portion.

The configuration of the semiconductor layer 21 shown here can also be applied to other configuration examples.

In FIG. 5(A) and other figures, the corners of the bent portion of the recess 30 are shown as rounded, but this is not a limitation of one embodiment of the present invention, and the corners of the bent portion may be angular. In this case, the top surface shape of the recess 30 may be called a zigzag shape.

The configuration of the recess 30 shown here can also be applied to other configuration examples.

This embodiment and the corresponding drawings, etc. can be implemented by appropriately combining at least a part of them with other embodiments or examples described in this specification. In addition, the multiple configurations shown in this embodiment and the corresponding drawings, etc. can be appropriately combined with each other.

(Embodiment 2)
In this embodiment, a more detailed structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

The contents described above regarding the semiconductor device having the transistor 20 can also be applied to the semiconductor device described later. The contents described regarding the semiconductor device described later can also be applied to the semiconductor device having the transistor 20 described above.

Figure 7(A) shows a plan view (also referred to as a top view) of a semiconductor device 10 according to one embodiment of the present invention. Figure 7(B) shows a cross-sectional view taken along dashed line A1-A2 in Figure 7(A). Figure 7(C) shows a cross-sectional view taken along dashed line B1-B2 in Figure 7(A). Here, dashed line B1-B2 is orthogonal to dashed line A1-A2. Note that some of the components of the semiconductor device 10 (such as an insulating layer) are omitted in Figure 7(A). As with Figure 7(A), some of the components are omitted from the plan views of the semiconductor device in the following drawings.

The semiconductor device 10 includes a transistor 100, a transistor 200, an insulating layer 110, and an insulating layer 102. An insulating layer serving as a base film or a substrate may be provided below the insulating layer 102.

The transistors 100 and 200 have different structures. In addition, the transistors 100 and 200 can be formed by sharing some of the steps. When the semiconductor device 10 is applied to a display device, it is preferable to use the transistor 100 as a pixel selection transistor and the transistor 200 as a driving transistor. More specifically, since it is preferable that the driving transistor has high saturation, the transistor 200 having a long channel length can be preferably used. In this way, the semiconductor device of one embodiment of the present invention has an excellent effect that transistors having different channel lengths can be freely designed on the same substrate by changing the thickness of the insulating layer and pattern formation.

The configuration of transistor 200 will be described. Here, an example is shown in which the configuration of transistor 20 described above is applied to transistor 200.

The transistor 200 includes a conductive layer 204, a conductive layer 212a, a conductive layer 212b, an insulating layer 106, and a semiconductor layer 208. In the transistor 200, the conductive layer 204 functions as a gate electrode, and a part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 212a functions as one of the source electrode and the drain electrode, and the conductive layer 212b functions as the other of the source electrode and the drain electrode. Each layer constituting the transistor 200 may have a single-layer structure or a stacked structure. The conductive layer 204, the conductive layer 212a, the conductive layer 212b, the insulating layer 106, and the semiconductor layer 208 can refer to the above-mentioned descriptions of the conductive layer 23, the conductive layer 24a, the conductive layer 24b, the insulating layer 22, and the semiconductor layer 21, respectively.

The insulating layer 110 and the insulating layer 102 have a recess 145. For the insulating layer 110, the insulating layer 102, and the recess 145, the above-mentioned descriptions of the insulating layer 32, the insulating layer 31, and the recess 30 can be referred to, respectively.

The conductive layer 212a and the conductive layer 212b are provided on the insulating layer 102. Here, the recess 145 can be said to be a combination of an opening (opening 145a) provided in the insulating layer 110 so as to overlap a part of the conductive layer 212a and the conductive layer 212b in a plan view, and a recess (recess 145b) of the insulating layer 102 provided in the area overlapping with the opening. Therefore, it can be said that the vicinity of the side end of the conductive layer 212a and the vicinity of the side end of the conductive layer 212b protrude from the side wall of the recess 145 (which may refer to the side surface of the recess 145, or the side surface of the insulating layer 110 in the recess 145).

The conductive layer 212a and the conductive layer 212b can be formed using the same material. In addition, the conductive layer 212a and the conductive layer 212b can be formed in the same process. For example, a film that will become the conductive layer 212a and the conductive layer 212b can be formed by forming the film and processing the film.

As shown in Figures 7(A) and 7(B), in the region where the semiconductor layer 208 overlaps with the conductive layer 212a and the conductive layer 212b in a plan view, the semiconductor layer 208 is provided in contact with the side of the insulating layer 110 in the recess 145, a part of the upper surface and the side of the conductive layer 212a, and a part of the upper surface and the side of the conductive layer 212b. Also, as shown in Figures 7(A) and 7(C), in the region where the semiconductor layer 208 does not overlap with the conductive layer 212a and the conductive layer 212b in a plan view, the semiconductor layer 208 is provided in contact with the side of the insulating layer 110 in the recess 145.

As shown in FIG. 7B and FIG. 7C, a material layer 208m is provided on the bottom surface of the recess 145. For the material layer 208m, the description of the material layer 21m described above can be referred to. The material layer 208m is a layer made of the same material as the semiconductor layer 208. The semiconductor layer 208 and the material layer 208m are formed simultaneously and separately when the films to become the semiconductor layer 208 and the material layer 208m are formed in the recess 145 by causing a step in the film at the exposed ends of the conductive layer 212a and the conductive layer 212b.

In this way, in one embodiment of the present invention, a semiconductor layer can be formed in a self-aligned manner simply by depositing a film that will become the semiconductor layer. Therefore, the total number of steps in manufacturing a semiconductor device can be reduced.

The region of the semiconductor layer 208 in contact with the conductive layer 212a functions as one of the source region and the drain region, and the region of the semiconductor layer 208 in contact with the conductive layer 212b functions as the other of the source region and the drain region. In the semiconductor layer 208, a channel formation region is provided between the source region and the drain region.

The insulating layer 106 is provided so as to cover the recess 145. Here, the semiconductor layer 208 and the material layer 208m provided inside the recess 145 are also covered by the insulating layer 106. The insulating layer 106 is provided on the semiconductor layer 208, the material layer 208m, the conductive layer 212a, the conductive layer 212b, and the insulating layer 110. The insulating layer 106 has an area in contact with the side of the semiconductor layer 208 in the recess 145, the upper surface of the material layer 208m in the recess 145, the upper surface and side of the conductive layer 212a in the recess 145, the upper surface and side of the conductive layer 212b in the recess 145, and the side of the insulating layer 110 in the recess 145. The insulating layer 106 has a shape that conforms to the shapes of the side surface of the semiconductor layer 208 in the recess 145, the top surface of the material layer 208m in the recess 145, the top surface and side surface of the conductive layer 212a in the recess 145, the top surface and side surface of the conductive layer 212b in the recess 145, and the side surface of the insulating layer 110 in the recess 145. At least a portion of the insulating layer 106 is provided between the semiconductor layer 208 and the conductive layer 204. That is, the insulating layer 106 functions as a gate insulating layer.

When viewed in cross section perpendicular to the substrate surface, the recess 145 has a cavity 227 filled with the conductive layer 212a or the conductive layer 212b and the insulating layer 106. Note that the recess 145 may not have the cavity 227. For the cavity 227, the description of the cavity 27 described above can be referred to.

The conductive layer 204 is provided on the insulating layer 106, overlapping the recess 145, and has a region in contact with the upper surface of the insulating layer 106. The conductive layer 204 has a region facing the semiconductor layer 208 via the insulating layer 106. The conductive layer 204 has a shape that follows the shape of the upper surface of the insulating layer 106.

In the transistor 200, the side of the region of the semiconductor layer 208 located between the conductive layers 212a and 212b becomes the source-drain current path (the channel formation region of the semiconductor layer 208). Therefore, in the transistor 200, the current path between the source and drain can be in a plane perpendicular or approximately perpendicular (vertical or approximately vertical) to the substrate surface. At the same time, it can also be said that the source-drain current flows in a parallel or approximately parallel (horizontal or approximately horizontal) direction to the substrate surface in the transistor 200. In this way, the transistor 200 can be called a VLFET (Vertical Lateral Field Effect Transistor) because both the vertical and horizontal directions contribute to the source-drain current path.

Next, the configuration of transistor 100 will be described.

The transistor 100 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. In the transistor 100, the conductive layer 104 functions as a gate electrode, and a part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other of the source electrode and the drain electrode. Each layer constituting the transistor 100 may have a single-layer structure or a stacked structure.

A conductive layer 112a is provided on the insulating layer 102, and an insulating layer 110 is provided on the conductive layer 112a. The insulating layer 110 is provided so as to cover the upper surface and side surface of the conductive layer 112a. The insulating layer 110 has an opening 141 that reaches the conductive layer 112a in a region overlapping with the conductive layer 112a. It can also be said that the conductive layer 112a is exposed in the opening 141. The conductive layer 112a can be made of the same material as the conductive layer 212a and the conductive layer 212b. In addition, the conductive layer 112a can be formed in the same process as the conductive layer 212a and the conductive layer 212b. For example, a film that becomes the conductive layer 112a, the conductive layer 212a, and the conductive layer 212b is formed, and the conductive layer 112a, the conductive layer 212a, and the conductive layer 212b can be formed by processing the film.

The conductive layer 112b is provided so as to be embedded in the insulating layer 110 in a region overlapping with the conductive layer 112a. The height of the upper surface of the conductive layer 112b is roughly the same as the height of the upper surface of the insulating layer 110. The conductive layer 112b also has an opening 143 in the region overlapping with the conductive layer 112a. The opening 143 is provided in a region overlapping with the opening 141.

The semiconductor layer 108 is provided so as to cover the opening 141 and the opening 143. The same material as the semiconductor layer 208 can be used for the semiconductor layer 108. The semiconductor layer 108 can be formed in the same process as the semiconductor layer 208. For example, the semiconductor layer 108 and the semiconductor layer 208 can be formed by forming a film that will become the semiconductor layer 108 and the semiconductor layer 208 and processing the film.

The semiconductor layer 108 has an area in contact with the side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the upper surface of the conductive layer 112a. The semiconductor layer 108 is electrically connected to the conductive layer 112a through the openings 141 and 143. The semiconductor layer 108 has a shape that follows the shapes of the side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the upper surface of the conductive layer 112a.

The region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source region and the drain region, and the region in contact with the conductive layer 112b functions as the other of the source region and the drain region. In the semiconductor layer 108, a channel formation region is provided between the source region and the drain region.

The insulating layer 106 is provided so as to cover the opening 141 and the opening 143. The insulating layer 106 is provided on the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110. The insulating layer 106 has an area that contacts the side surface of the semiconductor layer 108, the upper surface and side surface of the conductive layer 112b, and the upper surface of the insulating layer 110. The insulating layer 106 has a shape that follows the shapes of the side surface of the semiconductor layer 108, the upper surface and side surface of the conductive layer 112b, and the upper surface of the insulating layer 110.

The conductive layer 104 is provided on the insulating layer 106 and has a region in contact with the upper surface of the insulating layer 106. The conductive layer 104 has a region that overlaps with the semiconductor layer 108 through the insulating layer 106. The conductive layer 104 has a shape that matches the shape of the upper surface of the insulating layer 106. The conductive layer 104 can be formed using the same material as the conductive layer 204. In addition, the conductive layer 104 can be formed in the same process as the conductive layer 204. For example, the conductive layer 104 and the conductive layer 204 can be formed by forming a film that will become the conductive layer 104 and the conductive layer 204 and processing the film.

The transistor 100 is a so-called top-gate type transistor having a gate electrode above the semiconductor layer 108. Furthermore, since the lower surface of the semiconductor layer 108 (the sidewall and bottom surface of the opening 141, and the surface facing the sidewall of the opening 143) contacts the conductive layer 112a and the conductive layer 112b that function as a source electrode and a drain electrode, the transistor 100 can be called a TGBC (Top Gate Bottom Contact) type transistor. In addition, the source electrode and the drain electrode of the transistor 100 are located at different heights with respect to the substrate surface, and the drain current flows vertically or approximately vertically with respect to the substrate surface. It can also be said that the drain current flows vertically or approximately vertically in the transistor 100. Therefore, the transistor 100 can be called a vertical channel type transistor or a VFET (Vertical Field Effect Transistor).

The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor having a channel length smaller than the limit resolution of an exposure device used to manufacture the transistor can be manufactured with high precision. In addition, the characteristic variation between the multiple transistors 100 can be reduced. Therefore, the operation of a semiconductor device including the transistor 100 can be stabilized and the reliability can be improved. Furthermore, when the characteristic variation between the multiple transistors 100 is reduced, the degree of freedom in circuit design is increased, and the operating voltage of the semiconductor device including the transistor 100 can be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

In addition, since the transistor 100 can have a source electrode, a layer having a channel formation region, and a drain electrode stacked, the area occupied can be significantly reduced compared to a so-called planar type transistor in which a layer having a channel formation region is arranged in a planar shape.

The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each function as wiring, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit having the transistor 100 and wiring, the area occupied by the transistor 100 and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and the semiconductor device can be miniaturized.

The conductive layer 112a and the conductive layer 112b functioning as the source electrode and the drain electrode of the transistor 100 are provided on different surfaces. Specifically, the conductive layer 112a is provided on the insulating layer 102, the conductive layer 112b is provided on the insulating layer 110, and the insulating layer 110 is sandwiched between the conductive layer 112a and the conductive layer 112b. On the other hand, the conductive layer 212a and the conductive layer 212b functioning as the source electrode and the drain electrode of the transistor 200 are provided on the same surface. Specifically, the conductive layer 212a and the conductive layer 212b are provided on the insulating layer 102. It can also be said that one of the source electrode or the drain electrode of the transistor 100 is provided on the same surface as the source electrode and the drain electrode of the transistor 200, and the other of the source electrode or the drain electrode of the transistor 100 is provided on a surface different from the source electrode and the drain electrode of the transistor 200.

In this way, a semiconductor device according to one aspect of the present invention can have a configuration that combines not only a VLFET (e.g., the aforementioned transistor 20 and transistor 200, etc.), but also a VLFET and a transistor having a structure different from that of a VLFET (e.g., a VFET such as transistor 100, etc.). This makes it possible to realize a high-performance semiconductor device that takes advantage of the characteristics of each transistor.

For example, a high-performance semiconductor device 10 can be realized by applying a VFET with a short channel length such as transistor 100 to a transistor that requires a large on-current, and applying a VLFET with a long channel length such as transistor 200 to a transistor that requires high saturation. As described below, transistors 100 and 200 can be formed on the same substrate with some of the processes in common. Therefore, even if the semiconductor device 10 has a configuration that includes transistors with different structures (VLFETs and VFETs), the number of processes required for fabrication does not increase significantly compared to a semiconductor device that has only VLFETs.

Note that the semiconductor device according to one embodiment of the present invention is not limited to the above, and may be composed of only VLFETs, as in the semiconductor device having the transistor 20 described above. For example, if the semiconductor device 10 does not include the transistor 100 (VFET) and includes only a plurality of transistors 200 (VLFETs), the semiconductor device 10 can be realized having a plurality of transistors 200 with different on-currents by making the top surface shape of the recess 145 different for each transistor 200. For specific examples of the top surface shape of the recess 145, the description of the top surface shape of the recess 30 in the transistor 20 described in the previous embodiment can be referenced.

For example, when a semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained. Furthermore, when a semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

An insulating layer 195 is provided to cover the transistors 100 and 200. The insulating layer 195 functions as a protective layer for the transistors 100 and 200.

Next, the detailed configuration of transistor 100 and transistor 200 will be described.

It is preferable that the semiconductor layer 108 and the semiconductor layer 208 each have a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties.

The band gap of the metal oxide used in the semiconductor layer 108 and the semiconductor layer 208 is preferably 2.0 eV or more, and more preferably 2.5 eV or more.

Transistors using an oxide semiconductor (hereinafter referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. In addition, OS transistors have an extremely small off-state current and can retain charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of OS transistors can reduce the power consumption of a semiconductor device.

The crystallinity of the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.

The semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: oxide semiconductor). Note that these semiconductor materials may contain impurities as dopants.

For example, silicon can be used for the semiconductor layer 108 and the semiconductor layer 208. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using amorphous silicon in the channel formation region can be formed on a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon in the channel formation region has high field effect mobility and can operate at high speed. In addition, a transistor using microcrystalline silicon in the channel formation region has higher field effect mobility and can operate at high speed than a transistor using amorphous silicon.

The insulating layer 110 preferably has one or more inorganic insulating films. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. An oxynitride refers to a material whose composition contains more nitrogen than oxygen.

In the transistor 200, the region of the semiconductor layer 208 in contact with the insulating layer 110 functions as a channel formation region. In the transistor 100, the region of the semiconductor layer 108 in contact with the insulating layer 110 functions as a channel formation region. When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110 and the interface characteristics between the semiconductor layer 208 and the insulating layer 110, it is preferable that at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 and at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 208 contain oxygen. Specifically, it is preferable that the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 and the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 208 contain oxygen. One or more of oxide and oxynitride can be preferably used in the region of the insulating layer 110 that contacts the channel formation region of the semiconductor layer 108 and the region of the insulating layer 110 that contacts the channel formation region of the semiconductor layer 208.

It is preferable that the insulating layer 110 has a laminated structure. FIG. 7(B) and other figures show an example in which the insulating layer 110 has an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b.

Enlarged views of the transistor 200 shown in FIG. 7(A) and FIG. 7(B) are shown in FIG. 8(A) and FIG. 8(B). Enlarged views of the transistor 100 shown in FIG. 7(A) and FIG. 7(B) are shown in FIG. 9(A) and FIG. 9(B).

The insulating layer 110b preferably contains oxygen, and preferably uses one or more of the oxides and oxynitrides described above. Specifically, one or both of silicon oxide and silicon oxynitride can be preferably used for the insulating layer 110b. As a result, at least the region of the semiconductor layer 208 that is in contact with the insulating layer 110b and the region of the semiconductor layer 108 that is in contact with the insulating layer 110b can each function as a channel formation region.

It is more preferable to use a film that releases oxygen by heating for the insulating layer 110b. When the insulating layer 110b releases oxygen due to heat applied during the manufacturing process of the transistor 200 and the transistor 100, oxygen can be supplied to the semiconductor layer 208 and the semiconductor layer 108. When oxygen is supplied from the insulating layer 110b to the semiconductor layer 208 and the semiconductor layer 108, particularly to the channel formation region, oxygen vacancies (V _O ) in the channel formation region can be repaired and the oxygen vacancies (V _O ) in the channel formation region can be reduced. Therefore, the transistor 200 and the transistor 100 can have good electrical characteristics and high reliability.

For example, oxygen can be supplied to the insulating layer 110b by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer 110b by forming an oxide film in an oxygen-containing atmosphere on the upper surface of the insulating layer 110b by a sputtering method. The oxide film may then be removed. Note that in the third embodiment described later, an example in which oxygen is supplied to the insulating layer 110b by forming a metal oxide layer 137 is shown.

The insulating layer 110b is preferably formed by a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method. In particular, by forming the insulating layer 110b by a method that does not use hydrogen gas as a deposition gas, a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the channel formation region can be suppressed, and the electrical characteristics of the transistor 200 and the transistor 100 can be stabilized.

It is preferable that the substance diffuses easily in the insulating layer 110b. It can also be said that it is preferable that the diffusion coefficient of the substance in the insulating layer 110b is large. In particular, it is preferable that oxygen diffuses easily in the insulating layer 110b. In other words, it is preferable that the diffusion coefficient of oxygen in the insulating layer 110b is large. The oxygen contained in the insulating layer 110b diffuses in the insulating layer 110b and is supplied to the semiconductor layer 108 through the interface between the insulating layer 110b and the semiconductor layer 108, and is supplied to the semiconductor layer 208 through the interface between the insulating layer 110b and the semiconductor layer 208.

Here, by using a material with high conductivity for the semiconductor layer 108 and the semiconductor layer 208, the transistor 100 and the transistor 200 can have a large on-state current. However, when a material with high conductivity is used, oxygen vacancies (V _O ) are easily formed in the channel formation region of the transistor, and when the oxygen vacancies (V _O ) in the channel formation region increase, the threshold voltage of the transistor shifts, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may become large. For example, in an n-channel transistor, the cutoff current may become large due to the shift of the threshold voltage to the negative side. By providing the insulating layer 110b, oxygen is supplied to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b and the region of the semiconductor layer 208 that is in contact with the insulating layer 110b, that is, the channel formation region of the transistor 100 and the transistor 200, and the oxygen vacancies (V _O ) in the channel formation region can be reduced. As a result, the shift of the threshold voltage is suppressed, and a transistor that has both a small cutoff current and a large on-state current can be obtained. Therefore, a semiconductor device that achieves both low power consumption and high performance can be obtained.

In the transistor 100, the region in contact with the conductive layer 112a of the semiconductor layer 108 functions as one of the source region and the drain region, and the region in contact with the conductive layer 112b of the semiconductor layer 108 functions as the other of the source region and the drain region. The source region and the drain region are regions with lower electrical resistance than the channel formation region. The source region and the drain region can also be said to be regions with a higher carrier concentration and a higher oxygen defect density than the channel formation region.

The insulating layer 110a is provided on the insulating layer 102 so as to cover the conductive layer 112a, the conductive layer 212a, and the conductive layer 212b. The insulating layer 110a has an area in contact with the upper surface and side surface of the conductive layer 112a, the upper surface and side surface of the conductive layer 212a, the upper surface and side surface of the conductive layer 212b, and the upper surface of the insulating layer 102. The insulating layer 110b is provided on the insulating layer 110a. The insulating layer 110c is provided on the insulating layer 110b so as to cover the lower surface (the surface on the insulating layer 102 side) of the conductive layer 112b and the side surface of the conductive layer 112b opposite to the opening 143. The height of the upper surface of the conductive layer 112b and the height of the upper surface of the insulating layer 110c are approximately the same. It is preferable that the insulating layer 110a and the insulating layer 110c each release a small amount of impurities (e.g., hydrogen and water) from themselves and are difficult for impurities to penetrate. This makes it possible to prevent impurities contained in the insulating layers 110a and 110c from diffusing into the channel formation region. Therefore, it is possible to realize the transistors 100 and 200 that exhibit good electrical characteristics and are highly reliable.

It is preferable to use a film that is difficult for oxygen to permeate for each of the insulating layers 110a and 110c. This can suppress the oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a, the conductive layer 212a, and the conductive layer 212b through the insulating layer 110a. Similarly, it can suppress the oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112b through the insulating layer 110c. This can suppress the electrical resistance of the conductive layer 112a, the conductive layer 212a, the conductive layer 212b, and the conductive layer 112b from increasing. In addition, since the oxygen contained in the insulating layer 110b is suppressed from diffusing to the insulating layer 110a side and the insulating layer 110c side, the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the transistor 100 and the transistor 200 is increased, and oxygen vacancies (V _O ) in the channel formation region and defects in which hydrogen has entered the oxygen vacancies (hereinafter, sometimes referred to as V _O H) can be reduced.

By using a film through which oxygen does not easily diffuse for each of the insulating layers 110a and 110c, oxygen can be effectively supplied from the insulating layer 110b to the channel formation regions of the transistors 100 and 200. Note that a configuration in which one or both of the insulating layers 110a and 110c are not provided may also be used.

The insulating layer 110a and the insulating layer 110c each preferably contain nitrogen, and preferably use one or more of the above-mentioned nitrides and nitride oxides. For example, silicon nitride or silicon nitride oxide may be preferably used for the insulating layer 110a and the insulating layer 110c, respectively. Alternatively, one or both of the insulating layer 110a and the insulating layer 110c may use one or more of an oxide and an oxynitride. For example, aluminum oxide may be preferably used for the insulating layer 110a and the insulating layer 110c, respectively. Note that the insulating layer 110a may use the same material as the insulating layer 110c, or a different material may be used.

In this specification, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

The thickness T110a of the insulating layer 110a can be, for example, 3 nm or more and less than 1 μm, 5 nm or more and less than 500 nm, 10 nm or more and less than 400 nm, 20 nm or more and less than 300 nm, 50 nm or more and less than 200 nm, or 70 nm or more and less than 150 nm, or 70 nm or more and less than 120 nm. As shown in FIG. 8B, the thickness T110a can be the shortest distance between the surface to be formed of the insulating layer 110a (here, the upper surface of the conductive layer 212a or the upper surface of the conductive layer 212b) and the lower surface of the insulating layer 110b in the cross-sectional view of the transistor 200. Also, as shown in FIG. 9B, the thickness T110a can be the shortest distance between the surface to be formed of the insulating layer 110a (here, the upper surface of the conductive layer 112a) and the lower surface of the insulating layer 110b in the cross-sectional view of the transistor 100.

When the thickness T110a of the insulating layer 110a is large, the amount of impurities released from the insulating layer 110a increases, and the amount of impurities diffusing to the channel formation regions of the transistors 200 and 100 may increase. On the other hand, when the thickness T110a is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 212a side, the conductive layer 212b side, and the conductive layer 112a side through the insulating layer 110a, and the amount of oxygen supplied to the channel formation regions of the transistors 200 and 100 may decrease. By setting the thickness T110a to the above-mentioned range, oxygen vacancies (V _O ) and V _O H in the channel formation regions of the transistors 200 and 100 can be reduced. In addition, the conductive layer 212a, the conductive layer 212b, or the conductive layer 112a is oxidized by the oxygen contained in the insulating layer 110b, and the electrical resistance of the conductive layer 212a, the conductive layer 212b, or the conductive layer 112a can be prevented from increasing.

The thickness T110c of the insulating layer 110c can be, for example, 3 nm to 1 μm, 5 nm to 500 nm, 10 nm to 300 nm, 15 nm to 200 nm, 20 nm to 150 nm, 20 nm to 120 nm, or 20 nm to 100 nm. As shown in FIG. 8B, the thickness T110c can be the shortest distance between the surface on which the insulating layer 110c is formed (here, the upper surface of the insulating layer 110b) and the lower surface of the insulating layer 106 in the cross-sectional view of the transistor 200. Also, as shown in FIG. 9B, the thickness T110c can be the shortest distance between the surface on which the insulating layer 110c is formed (here, the upper surface of the insulating layer 110b) and the lower surface of the insulating layer 106 in the cross-sectional view of the transistor 100.

When the thickness T110c of the insulating layer 110c is large, the amount of impurities released from the insulating layer 110c increases, and the amount of impurities diffusing into the channel formation regions of the transistors 200 and 100 may increase. On the other hand, when the thickness T110c is small, oxygen contained in the insulating layer 110b may diffuse to the insulating layer 106 side and the conductive layer 112b side through the insulating layer 110c, and the amount of oxygen supplied to the channel formation regions of the transistors 200 and 100 may decrease. By setting the thickness T110c to the above-mentioned range, oxygen vacancies (V _O ) and V _O H in the channel formation regions of the transistors 200 and 100 can be reduced. In addition, the conductive layer 112b is oxidized by the oxygen contained in the insulating layer 110b, and the electrical resistance of the conductive layer 112b can be prevented from increasing.

In the transistor 100, at least one of the region of the semiconductor layer 108 in contact with the insulating layer 110a and the region of the semiconductor layer 108 in contact with the insulating layer 110c may be a region having a lower electrical resistance (hereinafter also referred to as a low-resistance region) than the channel formation region. The region can be said to be a region having a higher carrier concentration or a higher oxygen defect density than the channel formation region. By using a material that releases impurities (e.g., water or hydrogen) in the insulating layer 110a, the region in contact with the insulating layer 110a can be a low-resistance region. The semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112a (either the source region or the drain region) and the channel formation region. Similarly, by using a material that releases impurities in the insulating layer 110c, the region in contact with the insulating layer 110c can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region. The low-resistance region can function as a buffer region for relaxing the drain electric field. Note that these low-resistance regions may function as the source region or the drain region.

By providing a low resistance region between the drain region and the channel formation region, a high electric field is unlikely to occur near the drain region, the generation of hot carriers is suppressed, and the deterioration of the transistor can be suppressed. For example, when the conductive layer 112a functions as a drain electrode and the conductive layer 112b functions as a source electrode, by making the region of the semiconductor layer 108 in contact with the insulating layer 110a into a low resistance region, a high electric field is unlikely to occur near the drain region, the generation of hot carriers is suppressed, and the deterioration of the transistor can be suppressed. When the conductive layer 112a functions as a source electrode and the conductive layer 112b functions as a drain electrode, by making the region of the semiconductor layer 108 in contact with the insulating layer 110c into a low resistance region, a high electric field is unlikely to occur near the drain region, the generation of hot carriers is suppressed, and the deterioration of the transistor can be suppressed.

Similarly, in the transistor 200, the region of the semiconductor layer 208 in contact with the insulating layer 110a may be a low-resistance region compared to the channel formation region. This region can also be said to be a region with a high carrier concentration or a high oxygen defect density compared to the channel formation region. By using a material that releases impurities (e.g., water or hydrogen) in the insulating layer 110a, the region in contact with the insulating layer 110a can be a low-resistance region. The semiconductor layer 208 can be configured to have a low-resistance region between the region in contact with the conductive layer 212a (one of the source region or drain region) and the channel formation region. In addition, the semiconductor layer 208 can be configured to have a low-resistance region between the region in contact with the conductive layer 212b (the other of the source region or drain region) and the channel formation region. The low-resistance region can function as a buffer region for relaxing the drain electric field. Note that the low-resistance region may function as a source region or drain region.

As mentioned above, if the amount of impurities released from the insulating layers 110a and 110c is too large, the impurities may diffuse into the channel formation regions of the transistors 200 and 100. Therefore, even if a material that releases impurities is used for the insulating layers 110a and 110c, it is preferable that the amount of released impurities is small.

It is preferable that the insulating layer 110 has at least the insulating layer 110b. For example, the insulating layer 110 may have a structure that does not have either or both of the insulating layer 110a and the insulating layer 110c. The insulating layer 110 may have a stacked structure of two layers, four or more layers, or a single layer structure.

The upper surface shapes of the recess 145, the opening 141, and the opening 143 are not limited, and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or other polygonal shape, or a shape with rounded corners of these polygons. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 7(A) and the like, the upper surface shapes of the openings 141 and 143 are preferably circular. By making the upper surface shape of the openings circular, the processing accuracy when forming the openings can be improved, and openings of fine size can be formed. In this specification and the like, a circle is not limited to a perfect circle.

In addition, in FIG. 7(A) and other figures, the top surface shape of the recess 145 is circular, but the present invention is not limited to this, and as described above, various shapes are possible.

In this specification, the top surface shape of the recess 145 refers to the shape of the top surface end of the insulating layer 110 on the recess 145 side. The top surface shape of the opening 141 refers to the shape of the top surface end of the insulating layer 110 on the opening 141 side. Additionally, the top surface shape of the opening 143 refers to the shape of the bottom surface end of the conductive layer 112b on the opening 143 side.

As shown in FIG. 7(A) and the like, the top surface shape of opening 141 and the top surface shape of opening 143 can be made to match or approximately match each other. In this case, as shown in FIG. 7(B) and the like, it is preferable that the bottom surface end of conductive layer 112b on the opening 143 side matches or approximately matches the top surface end of insulating layer 110 on the opening 141 side. The bottom surface of conductive layer 112b refers to the surface on the insulating layer 102 side. The top surface of insulating layer 110 refers to the surface on the bottom surface side of conductive layer 112b. In this case, opening 141 and opening 143 can be viewed together as one opening.

The top surface shape of opening 141 and the top surface shape of opening 143 do not have to match each other. Furthermore, when the top surface shapes of openings 141 and 143 are circular, openings 141 and 143 may or may not be concentric.

The channel length and channel width of transistor 100 are explained using Figures 9(A) and 9(B).

9B, the channel length L100 of the transistor 100 is indicated by a double-headed dashed arrow. The channel length L100 of the transistor 100 corresponds to the length of the side of the insulating layer 110b on the opening 141 side in a cross-sectional view. In other words, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ110 between the side of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the limit resolution of the exposure device, and a transistor of a fine size can be realized. Specifically, a transistor with an extremely small channel length that could not be realized with a conventional exposure device for mass production of flat panel displays (for example, a minimum line width of about 2 μm or 1.5 μm) can be realized. In addition, a transistor with a channel length of less than 10 nm can be realized without using an extremely expensive exposure device used in cutting-edge LSI technology.

The channel length L100 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm. For example, the channel length L100 can be 100 nm or more and less than 1 μm.

By reducing the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, the semiconductor device can be miniaturized. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-definition display device, even if the number of wirings is increased, the signal delay in each wiring can be reduced and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

The channel length L100 can be controlled by adjusting the thickness T110b and angle θ110 of the insulating layer 110b. Note that in FIG. 9(B), the thickness T110b of the insulating layer 110b is indicated by a dashed double-headed arrow.

The thickness T110b of the insulating layer 110b can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm.

9B and the like show an example in which the side of the insulating layer 110 on the opening 141 side is vertical, but the side of the insulating layer 110 on the opening 141 side can also be tapered, as in the transistor 100A shown in FIG. 12A. When the side of the insulating layer 110 on the opening 141 side is tapered, the angle θ110 is preferably 90 degrees or less. By reducing the angle θ110, the coverage of the layer (e.g., the semiconductor layer 108) formed on the insulating layer 110 can be improved. In addition, the smaller the angle θ110, the larger the channel length L100 can be, and the larger the angle θ110, the smaller the channel length L100 can be.

The angle θ110 can be, for example, 30 degrees or more and 90 degrees or less, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 80 degrees or less, 50 degrees or more and 80 degrees or less, 55 degrees or more and 80 degrees or less, 60 degrees or more and 80 degrees or less, 65 degrees or more and 80 degrees or less, or 70 degrees or more and 80 degrees or less.

9B and other figures show a configuration in which the shape of the side of the insulating layer 110 on the opening 141 side is straight in cross section, but one embodiment of the present invention is not limited to this. In cross section, the shape of the side of the insulating layer 110 on the opening 141 side may be curved, and the shape of the side may have both straight and curved regions.

Here, it is preferable that the conductive layer 112b is not provided inside the opening 141. Specifically, it is preferable that the conductive layer 112b does not have a region that contacts the side of the insulating layer 110 on the opening 141 side. If the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 becomes shorter than the length of the side of the insulating layer 110b, which may make it difficult to control the channel length L100. Therefore, it is preferable that the top shape of the opening 143 coincides with the top shape of the opening 141, or that the opening 143 encompasses the opening 141 in a planar view.

In Figures 9(A) and 9(B), the width D141 of the opening 141 is indicated by a double-headed arrow with a two-dot chain line. Figure 9(A) shows an example in which the top surface shape of the opening 141 is circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 is the length of the circumference of the circle. In other words, the channel width W100 is π x D141. In this way, when the top surface shape of the opening 141 is circular, a transistor with a smaller channel width W100 can be realized compared to other shapes.

The width D141 of the opening 141 may vary in the depth direction. For example, the width D141 of the opening 141 may be the average value of the diameter at the highest point of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these three diameters. Alternatively, the diameter of the opening 141 may be any of the diameters at the highest point of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these three diameters.

When the opening 141 is formed using a photolithography method, the width D141 of the opening 141 is equal to or greater than the limit resolution of the exposure device. The width D141 can be, for example, 200 nm or more and less than 5 μm, 300 nm or more and less than 4.5 μm, 400 nm or more and less than 4 μm, 500 nm or more and less than 3.5 μm, 500 nm or more and less than 3 μm, 500 nm or more and less than 2.5 μm, 500 nm or more and less than 2 μm, 500 nm or more and less than 1.5 μm, or 500 nm or more and less than 1 μm.

When the channel length L100 of the transistor 100 is reduced, it is preferable that the insulating layer 110a and the insulating layer 110c are made of a material that releases less hydrogen from itself. When the insulating layer 110a and the insulating layer 110c are made of a material that releases even a small amount of hydrogen, it is preferable that the thicknesses of these layers are thin. For example, when the channel length L100 is 100 nm or less, the thickness T110a of the insulating layer 110a and the thickness T110c of the insulating layer 110c are preferably 1 nm or more and 50 nm or less, 3 nm or more and 40 nm or less, 5 nm or more and 30 nm or less, 5 nm or more and 20 nm or less, 5 nm or more and 15 nm or less, or 5 nm or more and 10 nm or less. This makes it possible to reduce the amount of impurities that diffuse into the channel formation region, and even when the channel length L100 is short, the transistor exhibits good electrical characteristics and is highly reliable.

Note that, although the configuration in which the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region has been described as an example here, one embodiment of the present invention is not limited to this. The region of the semiconductor layer 108 in contact with the insulating layer 110a may also function as a channel formation region. Similarly, the region in contact with the insulating layer 110c may also function as a channel formation region.

7B and the like show an example in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the openings 141 and 143 in the transistor 100, but one embodiment of the present invention is not limited to this. A step may be formed between the insulating layer 110 and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 may be provided along the step.

In addition, in FIG. 9B and other figures, the transistor 100 has only one gate electrode, but the present invention is not limited to this. For example, the transistor 100 may have a back gate electrode (which may also be called a second gate electrode) as in the transistor 100B shown in FIG. 12B.

Transistor 100B differs from transistor 100 mainly in that it has conductive layer 116 on conductive layer 112a and that insulating layer 110 has a six-layer structure.

The insulating layer 110 includes an insulating layer 110a on the conductive layer 112a, an insulating layer 110b1 on the insulating layer 110a, an insulating layer 110d1 on the insulating layer 110b1, an insulating layer 110d2 on the insulating layer 110d1 and the conductive layer 116, an insulating layer 110b2 on the insulating layer 110d2, and an insulating layer 110c on the insulating layer 110b2.

The conductive layer 116 functions as a back gate electrode of the transistor 100B. The conductive layer 116 is preferably located on the insulating layer 110b1. The conductive layers 112a and 112b are electrically insulated from the conductive layer 116 by the insulating layers 110d2, 110b2, and 110c. An opening is preferably provided in the conductive layer 116, and an opening 141 is preferably provided inside the opening. A part of the insulating layer 110 functions as a back gate insulating layer of the transistor 100B.

Therefore, in the transistor 100B, the semiconductor layer 108 also has a region that faces the conductive layer 104 via the insulating layer 106, and a region that faces the conductive layer 116 via a part of the insulating layer 110 (particularly, the insulating layer 110b2 and the insulating layer 110d2). In other words, at least a part of the semiconductor layer 108 is sandwiched between the conductive layer 104 and the conductive layer 116 in the opening 141. In the opening 141, the insulating layer 106 is provided between at least a part of the semiconductor layer 108 and the conductive layer 104. In addition, a part of the insulating layer 110 (particularly, the insulating layer 110b2 and the insulating layer 110d2) is provided between at least a part of the semiconductor layer 108 and the conductive layer 116.

The conductive layer 116 may be electrically connected to the conductive layer 112a or the conductive layer 112b. For example, the conductive layer 112a and the conductive layer 116 may be in contact with each other through openings provided in the insulating layer 110a, the insulating layer 110b1, and the insulating layer 110d1.

The conductive layer 116 may have a single layer structure or a stacked structure of two or more layers. The conductive layer 116 may be made of the same material as the conductive layer 112a, the conductive layer 112b, and the conductive layer 104.

The insulating layer 110d2 covers the upper and side surfaces of the conductive layer 116. The insulating layer 110d2 is provided so as to cover a portion of the opening of the conductive layer 116. It is preferable that the insulating layer 110d2 contacts the insulating layer 110d1 through the opening.

It is preferable to apply the same configuration as the insulating layer 110a and the insulating layer 110c to the insulating layer 110d1 and the insulating layer 110d2. Specifically, it is preferable to use a film into which oxygen is unlikely to diffuse for the insulating layer 110d1 and the insulating layer 110d2. It is also preferable to use a film into which hydrogen is unlikely to diffuse for the insulating layer 110d1 and the insulating layer 110d2. By providing such insulating layer 110d1 and insulating layer 110d2, it is possible to suppress oxidation of the conductive layer 116. It is also possible to suppress diffusion of hydrogen contained in the conductive layer 116 into the semiconductor layer 108.

Note that, although FIG. 12(B) shows an example in which the thickness of insulating layer 110d1 is uniform regardless of location, the present invention is not limited to this. For example, insulating layer 110d1 may have different thicknesses in areas that overlap with conductive layer 116 and areas that do not overlap. For example, when processing the film that will become conductive layer 116, parts of insulating layer 110d1 that do not overlap with conductive layer 116 may be removed, resulting in a thinner thickness.

It is preferable that the insulating layer 110b2 covers the upper and side surfaces of the conductive layer 116 via the insulating layer 110d2. It is preferable that the insulating layer 110b2 is provided so as to cover a portion of the opening of the conductive layer 116 via the insulating layer 110d2.

The insulating layer 110b1 and the insulating layer 110b2 can each have a configuration similar to that applicable to the insulating layer 110b. Specifically, it is preferable to use a layer containing oxygen for the insulating layer 110b1 and the insulating layer 110b2, and it is preferable to have a region with a higher oxygen content than at least one of the insulating layers 110a, 110c, 110d1, and 110d2.

By adopting such a structure, the structure of the insulating layer 110 can be made symmetrical above and below the conductive layer 116. In addition, oxygen can be supplied to the semiconductor layer 108 from the two insulating layers, the insulating layer 110b1 and the insulating layer 110b2, thereby improving the characteristics of the transistor.

However, the present invention is not limited to the above, and for example, it is also possible to configure the device without providing insulating layer 110b1. It is also possible to configure the device without providing insulating layer 110d1 and insulating layer 110d2.

In the transistor 100B, the semiconductor layer 108 has a region facing the conductive layer 104 through the insulating layer 106 and a region facing the conductive layer 116 through a part of the insulating layer 110 (particularly, the insulating layer 110b2 and the insulating layer 110d2). In other words, at least a part of the semiconductor layer 108 is sandwiched between the conductive layer 104 and the conductive layer 116 in the opening 141. In the opening 141, the insulating layer 106 is provided between at least a part of the semiconductor layer 108 and the conductive layer 104. In addition, a part of the insulating layer 110 (particularly, the insulating layer 110b2 and the insulating layer 110d2) is provided between at least a part of the semiconductor layer 108 and the conductive layer 116. Here, the part of the insulating layer 110 functions as a back gate insulating layer (which can also be called a second gate insulating layer) of the transistor 100B.

Because the transistor 100B has a back gate electrode, the potential of the back gate side (also called the back channel) of the semiconductor layer 108 can be fixed. Therefore, the saturation of the Id-Vd characteristics of the transistor 100B can be further improved.

In addition, since the transistor 100B has a back gate electrode, the potential of the back channel of the semiconductor layer 108 can be fixed, and the shift in the threshold voltage can be suppressed. This makes it possible to realize a transistor with normally-off characteristics.

Transistor 100B has a region in which conductive layer 116, insulating layer 110, semiconductor layer 108, insulating layer 106, and conductive layer 104 overlap in this order in one direction without any other layers in between. By widening this region, the electric field from the gate electrode (first gate electrode) and the electric field from the back gate electrode (second gate electrode) can be applied to the semiconductor layer 108 more effectively.

In addition, in a cross-sectional view, the shortest distance between the conductive layer 116 and the semiconductor layer 108 (i.e., the thickness of the backgate insulating layer) may differ on the left and right sides of the opening in the insulating layer 110.

Next, the channel length and channel width of transistor 200 will be explained using Figures 8(A) and 8(B).

In FIG. 8A, the channel length L200a and the channel length L200b of the transistor 200 are indicated by solid double-headed arrows. The channel length L200a and the channel length L200b correspond to the distance between the conductive layer 212a and the conductive layer 212b along the circumferential direction of the semiconductor layer 208 provided on the side wall of the recess 145. As shown in FIG. 8A, the annular semiconductor layer 208 is provided over the entire side wall of the recess 145, so that there are two paths connecting the conductive layer 212a and the conductive layer 212b in the semiconductor layer 208, one of which can be the channel length L200a and the other can be the channel length L200b. It is preferable that the channel length L200a and the channel length L200b are equal or approximately equal. In this case, it is preferable that the conductive layer 212a and the conductive layer 212b are arranged symmetrically with respect to the recess 145. For example, as shown in FIG. 8A, by providing conductive layers 212a and 212b at both ends of the circular recess 145, the channel length L200a and the channel length L200b can be made equal. In this manner, the channel length L200a and the channel length L200b of the transistor 200 can be controlled by the top surface shape and size of the recess 145. Therefore, the channel length L200a and the channel length L200b can be made greater than the channel length L100.

8B, the channel width W200 of the transistor 200 is indicated by a double-headed dashed arrow. The channel width W200 corresponds to the length of the side of the insulating layer 110b on the recess 145 side in a cross-sectional view. In other words, the channel width W200 is determined by the thickness T110b of the insulating layer 110b and the angle θ110 between the side of the insulating layer 110b on the recess 145 side and the surface on which the insulating layer 110b is formed (here, the upper surface of the insulating layer 110a). Also, as shown in FIG. 8A, when the channel length L200a and the channel length L200b are equal or approximately equal, both paths function as channel formation regions, so that the effective channel width of the transistor 200 may be twice the channel width W200.

The channel width W200 of the transistor 200 can be controlled by the thickness of the insulating layer 110 (particularly the thickness of the insulating layer 110b). Here, since the insulating layer 110 is common to the transistor 200 and the transistor 100, the channel width W200 of the transistor 200 can be made into a very fine structure below the exposure limit of photolithography. The channel width W200 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm.

As described above, in the transistor 200, the channel length L200a and the channel length L200b can be increased, and the channel width W200 can be decreased. This allows the transistor 200 to be a transistor with high saturation properties.

As described above, the channel length L100 of the transistor 100 can be set to a value smaller than the limit resolution of the exposure device. On the other hand, since the channel length L100 is determined by the film thickness of the insulating layer 110b, when multiple transistors 100 are formed on the same surface in the same process, the channel lengths of all the transistors 100 are the same. In contrast, the channel length L200a and the channel length L200b of the transistor 200 can be controlled by the upper surface shape and size of the recess 145. Furthermore, the transistor 200 can be formed by sharing some of the processes with the transistor 100. Therefore, the transistor 100 with a short channel length and the transistor 200 with a longer channel length can be formed on the same surface with good productivity. For example, by applying the transistor 100 to a transistor requiring a large on-current and the transistor 200 to a transistor requiring high saturation, a high-performance semiconductor device 10 that makes use of the advantages of each transistor can be realized. For example, when the semiconductor device 10 is used in a display device, the transistor 100 can be used as a selection transistor that functions as a switch, and the transistor 200 can be used as a drive transistor for controlling the current flowing through a light-emitting element.

As described above, the transistors 100 and 200 can be formed in part by sharing some of the steps. Specifically, the semiconductor layer 108 and the semiconductor layer 208 can be formed in the same step. A part of the insulating layer 106 functions as a gate insulating layer for the transistor 100, and another part of the insulating layer 106 functions as a gate insulating layer for the transistor 200. The conductive layer 104 and the conductive layer 204 can be formed in the same step. The conductive layer 112a, the conductive layer 212a, and the conductive layer 212b can be formed in the same step. Therefore, the productivity of the semiconductor device 10 can be increased, and the manufacturing cost can be reduced.

In addition, in FIG. 8B and other figures, the height of the upper end of the semiconductor layer 208 and the height of the upper surface of the insulating layer 110b are shown to be the same or approximately the same, but the present invention is not limited to this. For example, as in the transistor 200A shown in FIG. 10A, the height of the upper end of the semiconductor layer 208 may be lower than the height of the upper surface of the insulating layer 110b. In this case, the insulating layer 106 contacts a part of the side surface of the insulating layer 110b.

8B and the like, the side end of the conductive layer 212a and the conductive layer 212b on the recess 145 side protrudes from the side of the insulating layer 110, but the present invention is not limited to this. For example, as in the transistor 200B shown in FIG. 10B, the side of the conductive layer 212a and the conductive layer 212b on the recess 145 side may be configured to roughly coincide with the side of the insulating layer 110. In this configuration, the semiconductor layer 208 contacts the side of the insulating layer 110 in the recess 145, the side of the conductive layer 212a in the recess 145, and the side of the conductive layer 212b in the recess 145. For example, when a manufacturing method is used in which the recess 145 is formed and the conductive layer 212a and the conductive layer 212b are formed at the same time, a configuration like the transistor 200B may be realized. This is preferable because it reduces the total number of steps compared to when the conductive layers 212a and 212b are formed separately from the recess 145.

In addition, when the transistor 200 is formed in parallel with the transistor 100, the angle between the side surface in the recess 145 of the insulating layer 110b and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a) may coincide or approximately coincide with the angle θ110, as in the transistor 100. Note that in FIG. 8B and the like, an example is shown in which the side surface in the recess 145 of the insulating layer 110 is perpendicular or approximately perpendicular to the surface on which the insulating layer 110 is to be formed, but the side surface in the recess 145 of the insulating layer 110 can also be tapered, as in the transistor 200C shown in FIG. 11A. When the side surface in the recess 145 of the insulating layer 110 is perpendicular or approximately perpendicular to the surface on which the insulating layer 110 is to be formed, this is preferable because it allows for miniaturization of the transistor. On the other hand, when the side surface in the recess 145 of the insulating layer 110 has a tapered shape, this is preferable because it allows for improved coverage of the film to be formed on the recess 145.

In addition, in FIG. 8B and other figures, the transistor 200 has only one gate electrode, but the present invention is not limited to this. For example, the transistor may have a back gate electrode, as in the case of transistor 200D shown in FIG. 11B.

Transistor 200D differs from transistor 200 mainly in that it has conductive layer 216 on conductive layer 212a and conductive layer 212b, and in that insulating layer 110 has a six-layer structure.

Here, the conductive layer 216 corresponds to the conductive layer 116 described above, and the description of the conductive layer 116 can be referred to. That is, the conductive layer 216 functions as a back gate electrode of the transistor 200D. The insulating layer 110 has a structure similar to that of the insulating layer 110 shown in FIG. 12B. That is, a part of the insulating layer 110 functions as a back gate insulating layer of the transistor 200D.

Therefore, in the transistor 200D, the semiconductor layer 208 also has a region that faces the conductive layer 204 via the insulating layer 106, and a region that faces the conductive layer 116 via a part of the insulating layer 110 (particularly, the insulating layer 110b2 and the insulating layer 110d2). In other words, at least a part of the semiconductor layer 208 is sandwiched between the conductive layer 204 and the conductive layer 216 in the recess 145. In the recess 145, the insulating layer 106 is provided between at least a part of the semiconductor layer 208 and the conductive layer 204. In addition, a part of the insulating layer 110 (particularly, the insulating layer 110b2 and the insulating layer 110d2) is provided between at least a part of the semiconductor layer 208 and the conductive layer 216.

Because the transistor 200D has a back gate electrode, the potential on the back gate side of the semiconductor layer 208 can be fixed. This makes it possible to further increase the saturation of the Id-Vd characteristics of the transistor 200D.

In addition, since the transistor 200D has a back gate electrode, the potential of the back channel of the semiconductor layer 208 can be fixed, and the shift in the threshold voltage can be suppressed. This makes it possible to realize a transistor with normally-off characteristics.

The following describes in detail the materials that can be used in the semiconductor device 10 of one embodiment of the present invention.

[Semiconductor layer 108, semiconductor layer 208]
Metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 will be specifically described. Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium or zinc. The metal oxide preferably contains two or three elements selected from indium, element M, and zinc. The element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more of gallium and tin. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.

The semiconductor layer 108 and the semiconductor layer 208 may each contain, for example, indium oxide (In oxide), indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also referred to as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide), or Oxide, also written as AZO. ), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO. ), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO (registered trademark). ), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO. ), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO. ), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO. ), etc. can be used. Alternatively, indium tin oxide containing silicon (also written as ITSO. ), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used. Materials that do not contain Zn, such as indium oxide, are suitable because they have a high affinity with Si processes. On the other hand, materials that contain Zn are suitable because they can improve crystallinity.

By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field effect mobility of the transistor can be increased. In addition, a transistor with a large on-current can be realized.

Note that the metal oxide may have one or more metal elements with a large periodic number instead of or in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by having a metal element with a large periodic number, the field effect mobility of the transistor may be increased. Examples of metal elements with a large periodic number include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

The metal oxide may contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the carrier concentration increases or the band gap decreases, which may increase the field effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

By increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide becomes highly crystalline and the diffusion of impurities in the metal oxide can be suppressed. This suppresses fluctuations in the electrical characteristics of the transistor and increases its reliability.

By increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, it is possible to suppress the formation of oxygen vacancies (V _O ) in the metal oxide. Therefore, carrier generation due to oxygen vacancies (V _O ) is suppressed, and a transistor with a small off-state current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

The electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the semiconductor layer 108 and the semiconductor layer 208. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required for the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M :Zn=6:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, and compositions in the vicinity of these. Note that the composition in the vicinity includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-current or field effect mobility of the transistor can be increased.

The atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, and compositions close to these. By increasing the proportion of M atoms in the metal oxide, the generation of oxygen vacancies ( _VO ) can be suppressed.

When element M contains multiple metal elements, the total proportion of the atomic numbers of the metal elements can be regarded as the proportion of the atomic number of element M.

In this specification, the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained may be referred to as the indium content. The same applies to other metal elements.

By using a material with a high indium content for the semiconductor layer 108 and the semiconductor layer 208, the on-state current or field effect mobility of the transistor can be increased. Furthermore, by having the element M, the generation of oxygen vacancies (V ₀ ) can be suppressed. The content of the element M (the ratio of the number of atoms of the element M to the sum of the number of atoms of all the metal elements contained) is preferably 0.1% to 3%, and more preferably 0.1% to 2%. This allows a transistor with good electrical characteristics to be obtained. For example, it is preferable to use In:M:Zn=40:1:10 and metal oxides in the vicinity thereof. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, In:Sn:Zn=40:1:10 and metal oxides in the vicinity thereof can be preferably used. Or, In:Al:Zn=40:1:10 and metal oxides in the vicinity thereof can be preferably used.

Here, if a metal oxide having a polycrystalline structure is used for the semiconductor layer 108 and the semiconductor layer 208, the grain boundaries become the recombination center, and carriers are captured, which may reduce the on-current of the transistor. When using a metal oxide having a composition that is likely to form a polycrystalline structure, it is preferable to include an element that inhibits crystallization. For example, compared to ITO, ITSO is less likely to form a polycrystalline structure, so it can be suitably used for the semiconductor layer 108 and the semiconductor layer 208. When ITSO is used, the silicon content (the ratio of the number of silicon atoms to the sum of the number of atoms of all metal elements contained) is preferably 1% or more and 20% or less, more preferably 3% or more and 20% or less, even more preferably 3% or more and 15% or less, and even more preferably 5% or more and 15% or less. Specifically, In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity of these can be suitably used.

The composition of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

The sputtering method can be suitably used to form the metal oxide. When forming the metal oxide by the sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.

The semiconductor layer 108 and the semiconductor layer 208 may each have a stacked structure having two or more metal oxide layers. The two or more metal oxide layers in the semiconductor layer 108 and the semiconductor layer 208 may each have the same or approximately the same composition. By forming a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs.

The two or more metal oxide layers in each of the semiconductor layer 108 and the semiconductor layer 208 may have different compositions. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto provided on the first metal oxide layer can be suitably used. In addition, it is particularly preferable to use gallium, aluminum, or tin as the element M. The element M in the first metal oxide layer and the second metal oxide layer may be the same or different from each other. For example, the first metal oxide layer and the second metal oxide layer may be IGZO layers having different compositions from each other.

For example, a laminated structure of a first metal oxide layer having a composition of In:Zn=4:1 [atomic ratio] or a composition close thereto and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto provided on the first metal oxide layer can be suitably used.

For example, a laminated structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.

When a laminate structure is formed of a first metal oxide layer having a first metal oxide and a second metal oxide layer having a second metal oxide, and the composition of the first metal oxide and the composition of the second metal oxide are the same or approximately the same, the boundary (interface) between the first metal oxide layer and the second metal oxide layer may not be clearly identified.

It is preferable to use a crystalline metal oxide for the semiconductor layer 108 and the semiconductor layer 208. Examples of the structure of a crystalline metal oxide include a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline structure, and a nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide, the density of defect states in the semiconductor layer 108 and the semiconductor layer 208 can be reduced, and a highly reliable semiconductor device can be realized.

It is preferable to use CAAC-OS or nc-OS for the semiconductor layer 108 and the semiconductor layer 208, respectively.

CAAC-OS has multiple layered crystals. The c-axis of the crystals is oriented in the normal direction of the surface on which the semiconductor layer 108 and the semiconductor layer 208 are preferably layered crystals parallel or approximately parallel to the surface on which the semiconductor layer 108 is formed. For example, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the side surface in the region in contact with the side surface of the conductive layer 112b in the opening 143. In particular, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110, which is the surface on which the semiconductor layer 108 is formed, in the opening 141. With this configuration, the layered crystals of the semiconductor layer 108 are formed approximately parallel to the channel length direction of the transistor 100, so that the transistor can have a large on-current. Similarly, the semiconductor layer 208 preferably has layered crystals parallel or approximately parallel to the surface on which the semiconductor layer 108 is formed (here, the side surface of the insulating layer 110, the side surface and the top surface of the conductive layer 212a, and the side surface and the top surface of the conductive layer 212b). In particular, it is preferable that the semiconductor layer 208 has layered crystals that are parallel or approximately parallel to the side surface of the insulating layer 110, which is the surface on which the semiconductor layer 208 is formed, in the region where the semiconductor layer 208 overlaps with the conductive layer 204.

By using a metal oxide with high crystallinity in the channel formation region, the density of defect states in the channel formation region can be reduced. On the other hand, by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

When forming a metal oxide by sputtering, the higher the substrate temperature during formation, the more crystalline the metal oxide can be formed. The substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. In addition, the higher the ratio of the flow rate of oxygen gas to the total deposition gas used in formation (hereinafter also referred to as the oxygen flow rate ratio) or the higher the oxygen partial pressure in the processing chamber, the more crystalline the metal oxide can be formed.

The crystallinity of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable to reduce V _O H in the channel formation region as much as possible to make it highly pure and intrinsic or substantially highly pure and intrinsic. In order to obtain a metal oxide with sufficiently reduced V _O H, it is important to remove impurities such as water and hydrogen in the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to repair oxygen vacancies (V _O ). By using a metal oxide with sufficiently reduced impurities such as _{V O} H for the channel formation region of a transistor, stable electrical characteristics can be imparted. Note that supplying oxygen to a metal oxide to repair oxygen vacancies (V _O ) may be referred to as oxygen addition treatment.

When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the carrier concentration of the channel formation region is preferably 1×10 ¹⁸ cm ^-3 or less, more preferably less than 1×10 ¹⁷ cm ^-3 , even more preferably less than 1×10 ¹⁶ cm ^-3 , still more preferably less than 1×10 ¹³ cm ^-3 , and still more preferably less than 1×10 ¹² cm ^-3 . Note that there is no limitation on the lower limit of the carrier concentration of the channel formation region, but it can be, for example, 1×10 ^-9 cm ^-3 .

OS transistors have small variations in electrical characteristics due to radiation exposure, i.e., are highly resistant to radiation, and therefore can be suitably used in environments where radiation may be present. It can also be said that OS transistors are highly reliable against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. OS transistors can also be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

The semiconductor layer 108 and the semiconductor layer 208 may each have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (representatively MoS ₂ ), molybdenum selenide (representatively MoSe ₂ ), molybdenum tellurium (representatively MoTe ₂ ), tungsten sulfide (representatively WS ₂ ), tungsten selenide (representatively WSe ₂ ), tungsten tellurium (representatively WTe ₂ ), hafnium sulfide (representatively HfS ₂ ), hafnium selenide (representatively HfSe ₂ ), zirconium sulfide (representatively ZrS ₂ ), zirconium selenide (representatively ZrSe ₂ ), and the like.

[Conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 204, conductive layer 212a, conductive layer 212b]
The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b may each have a single-layer structure or a stacked structure of two or more layers. Examples of materials that can be used for the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b include chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, and the like. The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, and the conductive layer 112b may include one or more of manganese, nickel, iron, cobalt, molybdenum, and niobium, and an alloy containing one or more of the above metals. The conductive layers 212a and 212b can be made of a low-resistance conductive material including one or more of copper, silver, gold, and aluminum. In particular, copper and aluminum are suitable for mass production. This is preferable because it has excellent

Conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 204, conductive layer 212a, and conductive layer 212b can each be made of a metal oxide (oxide conductor) having electrical conductivity. Examples of oxide conductors (OC) include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called ITO containing silicon, ITSO), zinc oxide to which gallium is added, and In-Ga-Zn oxide. In particular, conductive oxides containing indium are preferred because of their high electrical conductivity.

When oxygen vacancies are created in a metal oxide with semiconducting properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes a conductor. A metal oxide that has become a conductor can be called an oxide conductor.

The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b may each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) described above and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced.

A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied to each of conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 204, conductive layer 212a, and conductive layer 212b. By using a Cu-X alloy film, it is possible to process it by wet etching, thereby reducing manufacturing costs.

Note that the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b may be made of the same material or different materials. For example, the conductive layer 112a, the conductive layer 212a, and the conductive layer 212b, which can be formed in the same process, are preferably made of the same material. In addition, the conductive layer 104 and the conductive layer 204, which can be formed in the same process, are preferably made of the same material.

The conductive layer 112a and the conductive layer 112b have a region in contact with the semiconductor layer 108. The conductive layer 212a and the conductive layer 212b have a region in contact with the semiconductor layer 208. When a metal oxide is used as the semiconductor layer 108, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112a and the conductive layer 112b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a and the semiconductor layer 108 and between the conductive layer 112b and the semiconductor layer 108, which may hinder the conduction between them. Similarly, when a metal oxide is used as the semiconductor layer 208, if a metal that is easily oxidized is used for the conductive layer 212a and the conductive layer 212b, an insulating oxide may be formed between the conductive layer 212a and the semiconductor layer 208 and between the conductive layer 212b and the semiconductor layer 208, which may hinder the conduction between them. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductive material for the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b.

For conductive layer 112a, conductive layer 112b, conductive layer 112a, and conductive layer 112b, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel, respectively. These are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain low electrical resistance even when oxidized.

The conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b can each be made of the oxide conductors described above. Specifically, conductive oxides such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide doped with gallium can be used.

The conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride.

The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 may each have a stacked structure. In this case, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductive material in at least the region in contact with the semiconductor layer 108 or the semiconductor layer 208. In addition, it is preferable to use a material with low electrical resistivity in the region not in contact with the semiconductor layer 108 or the semiconductor layer 208. This can reduce the electrical resistance of the conductive layer. For example, ITSO can be suitably used in the region in contact with the semiconductor layer 108 or the semiconductor layer 208, and copper or tungsten can be suitably used in the region not in contact with the semiconductor layer 108 or the semiconductor layer 208. In particular, the conductive layer 112a, the conductive layer 212a, and the conductive layer 212b, which are in contact with the semiconductor layer 108 or the semiconductor layer 208 and are formed on the flat portion of the insulating layer 102, are preferably formed in a laminated structure in which an ITSO layer is provided on a copper layer. The conductive layer 112a, the conductive layer 212a, and the conductive layer 212b can be relatively easily routed as wiring. Therefore, by forming the conductive layer 112a, the conductive layer 212a, and the conductive layer 212b in the above-mentioned laminated structure, oxidation of the low-resistance copper layer can be reduced, and the conductive layer 112a can function as a good wiring with low electrical resistance.

[Insulating layer 106]
The insulating layer 106 may have a single-layer structure or a stacked structure of two or more layers. The insulating layer 106 preferably has one or more inorganic insulating films. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides. The insulating layer 106 can be made of the materials that can be used for the insulating layer 110.

The insulating layer 106 has a region in contact with the semiconductor layer 108 and the semiconductor layer 208. When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable to use any of the above-mentioned oxides and oxynitrides for at least the film that is in contact with the semiconductor layer 108 and the semiconductor layer 208 among the films that constitute the insulating layer 106. It is more preferable to use a film that releases oxygen when heated for the insulating layer 106.

Specifically, when the insulating layer 106 has a single-layer structure, it is preferable to use an oxide or an oxynitride for the insulating layer 106. Specifically, it is preferable to use silicon oxide or silicon oxynitride for the insulating layer 106.

When the insulating layer 106 has a stacked structure, it is preferable that the insulating film in contact with the semiconductor layer 108 and the semiconductor layer 208 has an oxide or an oxynitride, and the insulating film in contact with the conductive layer 104 and the conductive layer 204 has a nitride or a nitride oxide. As the oxide or oxynitride, for example, silicon oxide or silicon oxynitride can be preferably used. As the nitride or nitride oxide, silicon nitride or silicon nitride oxide can be preferably used.

Silicon nitride and silicon nitride oxide are suitable for use as the insulating layer 106 because they release a small amount of impurities (e.g., water and hydrogen) and are difficult for oxygen and hydrogen to permeate. By preventing impurities from diffusing from the insulating layer 106 to the semiconductor layer 108 and the semiconductor layer 208, the electrical characteristics of the transistor can be improved and the reliability can be increased. In this way, the insulating layer 106 preferably functions as a barrier film against at least one of oxygen, water, and hydrogen.

In this specification, a barrier film refers to a film that has barrier properties. For example, an insulating layer that has barrier properties can be called a barrier insulating layer. In this specification, barrier properties refer to one or both of the function of suppressing the diffusion of the corresponding substance (also called low permeability) and the function of capturing or fixing the corresponding substance (also called gettering).

In a fine transistor, if the thickness of the gate insulating layer becomes thin, the leakage current may become large. By using a material with a high relative dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[Insulating layer 195]
The insulating layer 195, which functions as a protective layer for the transistors 100 and 200, is preferably made of a material from which impurities do not easily diffuse. By providing the insulating layer 195, diffusion of impurities from the outside into the transistors can be effectively suppressed, and the reliability of the semiconductor device can be improved. Examples of impurities include water and hydrogen.

The insulating layer 195 can be an insulating layer having an inorganic material or an insulating layer having an organic material. For example, an inorganic material such as oxide, oxynitride, nitride oxide, or nitride can be suitably used for the insulating layer 195. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, one or more of acrylic resin and polyimide resin can be used as the organic material. A photosensitive material may be used as the organic material. In addition, two or more of the above insulating films may be stacked. The insulating layer 195 may have a stacked structure of an insulating layer having an inorganic material and an insulating layer having an organic material.

[Insulating layer 102]
The insulating layer 102, which functions as a base film for the transistors 100 and 200, is preferably made of a material through which impurities do not easily diffuse. By providing the insulating layer 102, diffusion of impurities from the outside into the transistors can be effectively suppressed, and the reliability of the semiconductor device can be improved. Examples of impurities include water and hydrogen.

The insulating layer 102 may have a single layer structure or a laminated structure of two or more layers. The insulating layer 102 preferably has one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides. The insulating layer 102 may be made of the materials that can be used for the insulating layer 110. For example, the insulating layer 102 may have a three-layer laminated structure of silicon nitride, silicon oxynitride on silicon nitride, and silicon nitride on silicon oxynitride.

The insulating layer 102 is preferably provided on a substrate having at least a heat resistance sufficient to withstand subsequent heat treatment. For example, the substrate may be a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate. A semiconductor element may be provided on the substrate. The semiconductor substrate and the insulating substrate may be circular or rectangular in shape.

A flexible substrate may be used as the substrate, and the transistor 100, etc. may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and the transistor 100, etc. By providing a peeling layer, after a part or whole of a semiconductor device is completed on the substrate, it is possible to separate the semiconductor device from the substrate and transfer it to another substrate. In this case, the transistor 100, etc. may be transferred to a substrate with poor heat resistance or a flexible substrate.

This embodiment and the corresponding drawings, etc. can be implemented by appropriately combining at least a part of them with other embodiments or examples described in this specification. In addition, the multiple configurations shown in this embodiment and the corresponding drawings, etc. can be appropriately combined with each other.

(Embodiment 3)
In this embodiment, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to Fig. 13A to Fig. 21C. Note that with regard to materials and formation methods of elements, description of the same parts as those described in Embodiment 2 may be omitted.

Note that in Figures 13(A) to 16(C), an example of a manufacturing method limited to the transistor 200 (VLFET) of the semiconductor device 10 is described, and in Figures 17(A) to 21(C), an example of a manufacturing method in which both the transistor 200 (VLFET) and the transistor 100 (VFET) are formed at the same time is described.

First, we will explain an example of a method for manufacturing the transistor 200 included in the semiconductor device 10.

Figures 13(A) to 16(C) show a cross-sectional view between dashed dotted lines A1-A2 and B1-B2 shown in Figure 7(A) side by side.

Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), etc. CVD methods include PECVD and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

The thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, or knife coating.

When processing the thin film that constitutes the semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Also, island-shaped thin films may be directly formed by a film formation method using a shielding mask such as a metal mask.

There are two typical photolithography methods. One is to form a resist mask on the thin film to be processed, process the thin film by etching or other methods, and then remove the resist mask. The other is to form a photosensitive thin film, and then expose and develop it to process the thin film into the desired shape.

In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light such as ultraviolet light, KrF laser light, or ArF laser light may also be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. Electron beams may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

To etch the thin film, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

First, the insulating layer 102 is formed on a substrate (not shown) that has sufficient heat resistance to withstand the subsequent heat treatment described above. The insulating layer 102 can be formed preferably by sputtering or PECVD.

Next, a film that will become the conductive layer 212a and the conductive layer 212b is formed on the insulating layer 102, and the film is processed to form the conductive layer 212a and the conductive layer 212b (FIG. 13(A)). A sputtering method can be suitably used to form the film. In addition, a wet etching method, for example, can be suitably used to form the conductive layer 212a and the conductive layer 212b.

For example, ITSO can be used as the conductive layer 212a and the conductive layer 212b. For example, a stacked film having a copper layer with high conductivity and an ITSO layer on the copper layer may be used as the conductive layer 212a and the conductive layer 212b. In the semiconductor device shown in this embodiment, the conductive layer 212a and the conductive layer 212b are disposed on a flat portion on the insulating layer 102, so that even if a conductive film with high conductivity such as copper is used, the conductive layer 212a and the conductive layer 212b can be relatively easily routed. Therefore, the conductive layer 212a and the conductive layer 212b can function as wiring with low electrical resistance.

Next, insulating layer 110a and insulating layer 110b are formed in this order on insulating layer 102, conductive layer 212a, and conductive layer 212b (FIG. 13B). The channel width W200 of transistor 200 depends on the film thickness of insulating layer 110b. Therefore, the film thickness of insulating layer 110b can be set according to the electrical characteristics desired for transistor 200.

The insulating layer 110a and the insulating layer 110b can be preferably formed by sputtering or PECVD. After forming the insulating layer 110a, it is preferable to form the insulating layer 110b continuously in a vacuum without exposing the surface of the insulating layer 110a to the atmosphere. By forming the insulating layer 110a and the insulating layer 110b continuously, it is possible to prevent impurities derived from the atmosphere from adhering to the surface of the insulating layer 110a. Examples of such impurities include water and organic matter.

The substrate temperature during the formation of the insulating layer 110a and the insulating layer 110b is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. By setting the substrate temperature during the formation of the insulating layer 110a and the insulating layer 110b within the above-mentioned range, it is possible to reduce the release of impurities (e.g., water and hydrogen) from the insulating layer 110a and the insulating layer 110b, and to suppress the diffusion of the impurities into the semiconductor layer 208. Therefore, it is possible to obtain a transistor that exhibits good electrical characteristics and is highly reliable.

In addition, since the insulating layers 110a and 110b are formed before the semiconductor layer 208, there is no need to worry about oxygen being desorbed from the semiconductor layer 208 due to the heat applied during the formation of the insulating layers 110a and 110b.

After the insulating layer 110b is formed, oxygen may be supplied to the insulating layer 110b. For example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used as a method for supplying oxygen. For the plasma treatment, an apparatus that turns oxygen gas into plasma by high-frequency power can be preferably used. For example, a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus can be given as an apparatus that turns a gas into plasma by high-frequency power. The plasma treatment is preferably performed in an atmosphere containing oxygen. For example, the plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, nitrous oxide (N ₂ O), nitrogen dioxide (NO ₂ ), carbon monoxide, and carbon dioxide.

The plasma treatment may be performed continuously in a vacuum without exposing the surface of the insulating layer 110b to the atmosphere. For example, when a PECVD apparatus is used to form the insulating layer 110b, it is preferable to perform the plasma treatment in the PECVD apparatus. This can increase productivity. Specifically, after the insulating layer 110b is formed in the PECVD apparatus, an N ₂ O plasma treatment can be performed continuously in a vacuum.

It is also preferable to form a metal oxide layer 137 on the insulating layer 110b (FIG. 13C). By forming the metal oxide layer 137, oxygen can be supplied to the insulating layer 110b.

The conductivity of the metal oxide layer 137 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the metal oxide layer 137. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide, or indium tin oxide containing silicon can be used as the metal oxide layer 137.

It is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 208 as the metal oxide layer 137. In particular, it is preferable to use a metal oxide material that can be applied to the semiconductor layer 208.

When forming the metal oxide layer 137, the amount of oxygen supplied to the insulating layer 110b can be increased by increasing the oxygen flow ratio of the deposition gas introduced into the processing chamber of the deposition apparatus or the oxygen partial pressure in the processing chamber. The oxygen flow ratio or oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% or more and 100% or less, more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow ratio to 100% and the oxygen partial pressure as close to 100% as possible.

In this manner, by forming the metal oxide layer 137 by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating layer 110b and oxygen can be prevented from being released from the insulating layer 110b during the formation of the metal oxide layer 137. As a result, a large amount of oxygen can be trapped in the insulating layer 110b. Then, a large amount of oxygen can be supplied to the semiconductor layer 208 by a later heat treatment. As a result, oxygen vacancies and _VOH in the semiconductor layer 208 can be reduced, and a transistor with good electrical characteristics and high reliability can be obtained.

After the metal oxide layer 137 is formed, a heat treatment may be performed. By performing a heat treatment after forming the metal oxide layer 137, oxygen can be effectively supplied from the metal oxide layer 137 to the insulating layer 110b.

The temperature of the heat treatment is preferably 150°C or higher and lower than the distortion point of the substrate, 200°C or higher and 450°C or lower, 230°C or higher and 400°C or lower, 250°C or higher and 350°C or lower, or 250°C or higher and 300°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the atmosphere containing nitrogen or the atmosphere containing oxygen, dry air (CDA: Clean Dry Air) may be used. Note that it is preferable that the content of hydrogen, water, and the like in the atmosphere is as small as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower. By using an atmosphere containing as little hydrogen, water, and the like as possible, it is possible to prevent hydrogen, water, and the like from being taken into the insulating layer 110a and the insulating layer 110b as much as possible. For the heat treatment, an oven, a rapid heating (RTA: Rapid Thermal Annealing) device, or the like can be used. By using an RTA device, the heating process time can be shortened.

After forming the metal oxide layer 137 or after the above-mentioned heat treatment, oxygen may be further supplied to the insulating layer 110b through the metal oxide layer 137. As a method for supplying oxygen, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used. For the plasma treatment, the above description can be referred to, and therefore a detailed description is omitted.

Then, the metal oxide layer 137 is removed. There is no particular limitation on the method for removing the metal oxide layer 137, but a wet etching method can be preferably used. By using the wet etching method, it is possible to prevent the insulating layer 110b from being etched when the metal oxide layer 137 is removed. This makes it possible to prevent the thickness of the insulating layer 110b from becoming thin, and to make the thickness of the insulating layer 110b uniform.

After removing the metal oxide layer 137, oxygen may be further supplied to the insulating layer 110b. The above description can be referred to for the method of supplying oxygen. For example, a film may be formed on the insulating layer 110b, and oxygen may be supplied to the insulating layer 110b through the film (not shown). For this treatment, plasma treatment in an atmosphere containing oxygen can be used. For this film, it is preferable to use a conductive film or a semiconductor film. For this film, a metal oxide film, a metal film, or an alloy film can be used. If a metal oxide film is used as the film and formed by a sputtering method or the like in an atmosphere containing oxygen, oxygen can be supplied to the insulating layer 110b even during the formation of the film, which is preferable.

The thickness of the film is preferably thin. Specifically, the thickness of the film is preferably 1 nm to 20 nm, 2 nm to 15 nm, or 3 nm to 10 nm. Typically, the thickness is about 5 nm.

The substrate temperature during the formation of the film is preferably 350°C or less, more preferably 340°C or less, even more preferably 330°C or less, and even more preferably 300°C or less. This allows a large amount of oxygen to be supplied to the insulating layer 110b.

By providing this film, when a bias voltage is applied between the pair of electrodes when oxygen is supplied, ionized oxygen is more likely to be attracted. Therefore, the amount of oxygen supplied to the insulating layer 110b can be increased.

As the processing apparatus for supplying oxygen, a dry etching apparatus, an ashing apparatus, or a PECVD apparatus can be suitably used. In particular, it is preferable to use an ashing apparatus. When a bias voltage is applied between a pair of electrodes of the processing apparatus, the bias voltage may be, for example, 10 V or more and 1 kV or less. Alternatively, the power density of the bias may be, for example, 1 W/cm ² or more and 5 W/cm ² or less.

Then, the film is removed. A wet etching method can be suitably used to remove the film.

The process of supplying oxygen to the insulating layer 110b is not limited to the above-mentioned method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions are supplied to the insulating layer 110b by ion doping, ion implantation, or plasma treatment. In addition, after forming a film that suppresses oxygen detachment on the insulating layer 110b, oxygen may be supplied to the insulating layer 110b through the film. It is preferable to remove the film after supplying oxygen. As the above-mentioned film that suppresses oxygen detachment, a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

After the insulating layer 110b is formed, the upper surface of the insulating layer 110b may be planarized by chemical mechanical polishing (CMP). This can eliminate unevenness on the upper surface of the insulating layer 110b caused by the conductive layers 212a and 212b, thereby improving the coverage of the layer formed on the insulating layer 110c. The planarization process may be performed before or after the process of supplying oxygen to the insulating layer 110b.

Next, insulating layer 110c is formed on insulating layer 110b (FIG. 14A). The formation of insulating layer 110c can be performed by referring to the description of the formation of insulating layer 110a and insulating layer 110b, so a detailed description is omitted.

Next, a resist mask 158 is formed on the insulating layer 110c. The resist mask 158 is formed in an area that does not overlap with the transistor 200.

Next, the insulating layer 110 (insulating layer 110c, insulating layer 110b, and insulating layer 110a) and the insulating layer 102 are processed through the resist mask 158 to form a recess 145 in the insulating layer 110 and the insulating layer 102 (FIG. 14B). The recess 145 is provided so as to have an area overlapping with the conductive layer 212a and the conductive layer 212b in a plan view. One or both of a wet etching method and a dry etching method can be suitably used to form the recess 145. For example, a dry etching method can be suitably used to form the recess 145. Note that the recess 145 may be formed on the insulating layer 110 and the insulating layer 102 at the same time, or may be formed by changing the processing conditions for the insulating layer 110 and the insulating layer 102.

Then, the resist mask 158 is removed.

Next, a metal oxide film 208f that becomes the semiconductor layer 208 is formed on the insulating layer 110 and the insulating layer 102 so as to cover the recess 145. The metal oxide film 208f is provided in contact with the upper surface and side surface of the insulating layer 110, the upper surface and side surface of the conductive layer 212a, and the upper surface and side surface of the conductive layer 212b. In the semiconductor device 10 of one embodiment of the present invention, as shown in Figures 7 (A) and 7 (B), the ends of the conductive layer 212a and the conductive layer 212b protrude in the recess 145. That is, the end of the conductive layer 212a and the end of the conductive layer 212b are located inside the recess 145, rather than the sidewall of the opening 145a formed in the insulating layer 110 and the sidewall of the recess 145b formed in the insulating layer 102. Therefore, in the cross section between A1 and A2, the metal oxide film 208f is stepped at the end of the conductive layer 212a and the end of the conductive layer 212b exposed in the recess 145, and the stepped portion is formed as the material layer 208m on the bottom surface of the recess 145. In addition, as shown in FIG. 7C, the semiconductor device 10 according to one embodiment of the present invention has a configuration in which the side wall of the recess 145b formed in the insulating layer 102 is located outside the side wall of the opening 145a formed in the insulating layer 110 in the region that does not overlap with the conductive layer 212a and the conductive layer 212b in the recess 145. Therefore, in the cross section between B1 and B2, the metal oxide film 208f is stepped at the bottom end of the opening 145a formed in the insulating layer 110, and the stepped portion is formed as the material layer 208m on the bottom surface of the recess 145 (FIG. 14C).

In this way, in one embodiment of the present invention, the semiconductor layer 208 can be formed in a self-aligned manner only on the sidewalls of the recess 145 (the side surfaces of the insulating layer 110, the side surfaces of the conductive layer 212a, and the side surfaces of the conductive layer 212b) by simply depositing the metal oxide film 208f. Therefore, after forming the metal oxide film 208f, a separate process for separating the region of the metal oxide film 208f on the sidewalls in the recess 145 from the region on the bottom surface in the recess 145 is not required, and the total number of steps in the manufacture of the semiconductor device can be reduced.

It is preferable to form the metal oxide film 208f by a sputtering method using a metal oxide target. In the sputtering method, in which particles emitted from a sputtering target are deposited on the workpiece to form a film, the coverage of the film to be formed is easily affected by the shape of the workpiece. Therefore, it is preferable to use a sputtering method to form the metal oxide film 208f, since the metal oxide film 208f is likely to break at the ends of the conductive layer 212a and the conductive layer 212b that are exposed in the recess 145.

It is preferable that the metal oxide film 208f is a dense film with as few defects as possible. It is also preferable that the metal oxide film 208f is a high-purity film in which impurities including hydrogen elements are reduced as much as possible. In particular, it is preferable to use a metal oxide film having crystallinity as the metal oxide film 208f.

It is preferable to use oxygen gas when forming the metal oxide film 208f. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or an oxynitride is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

By supplying oxygen to the insulating layer 110b, oxygen can be supplied to the channel formation region of the semiconductor layer 208 in a later step, and oxygen vacancies and _VOH in the channel formation region can be reduced.

When forming the metal oxide film 208f, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas (oxygen flow ratio) in the total deposition gas when forming the metal oxide film or the oxygen partial pressure in the processing chamber, the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio or the oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film can be, and the higher the on-current of the transistor can be.

Here, if the oxygen flow ratio or oxygen partial pressure is high, the metal oxide film may become polycrystalline. In the case of a polycrystalline metal oxide film, the grain boundaries become the recombination center, and carriers may be captured, resulting in a small on-current of the transistor. Therefore, it is preferable to adjust the oxygen flow ratio or oxygen partial pressure so that the metal oxide film 208f does not become polycrystalline. Since the ease with which the metal oxide film becomes polycrystalline differs depending on the composition of the metal oxide film, the oxygen flow ratio or oxygen partial pressure may be adjusted according to the composition of the metal oxide film 208f.

The higher the substrate temperature when forming the metal oxide film, the higher the crystallinity and the denser the metal oxide film can be. On the other hand, the lower the substrate temperature, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film can be.

The substrate temperature during the formation of the metal oxide film 208f is preferably from room temperature to 250°C, more preferably from room temperature to 200°C, and even more preferably from room temperature to 140°C. For example, a substrate temperature of from room temperature to 140°C is preferable because it increases productivity. In addition, by forming the metal oxide film 208f at room temperature or without heating the substrate, the crystallinity can be reduced.

If the substrate temperature is high, the metal oxide film may become polycrystalline. It is preferable to adjust the substrate temperature so that the metal oxide film 208f does not become polycrystalline. The substrate temperature can be adjusted according to the composition to be applied to the metal oxide film 208f.

Methods for controlling the composition of the resulting film include adjusting one or more of the type of source gas, the flow rate ratio of the source gas, the time for which the source gas is flowed, and the order in which the source gas is flowed. By adjusting these, the composition of the metal oxide film 208f can be controlled. In addition, by adjusting these, a film whose composition changes continuously can be formed. The composition of the metal oxide film 208f may be configured to change continuously.

Before forming the metal oxide film 208f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110. For example, a heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, a plasma treatment in an atmosphere containing oxygen may be performed. Alternatively, oxygen may be supplied to the insulating layer 110 by a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N ₂ O). When a plasma treatment containing nitrous oxide gas is performed, oxygen can be supplied while the organic substances on the surface of the insulating layer 110 are suitably removed. After such a treatment, it is preferable to continuously form the metal oxide film 208f without exposing the surface of the insulating layer 110 to the air.

When the semiconductor layer 208 has a laminated structure, it is preferable to deposit a next metal oxide film in succession after depositing the first metal oxide film without exposing the surface to the air.

After the metal oxide film 208f is formed, a heat treatment may be performed. By performing the heat treatment, oxygen can be effectively supplied from the insulating layer 110 to the metal oxide film 208f. The temperature of the heat treatment is preferably 200° C. or higher and 450° C. or lower. The heat treatment may be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. Dry air may be used as the atmosphere containing nitrogen or the atmosphere containing oxygen. The heat treatment may be performed using an oven, an RTA apparatus, or the like.

Next, a positive photoresist 159f is applied onto the metal oxide film 208f and the material layer 208m so as to fill the recess 145.

Next, the entire surface of the photoresist 159f is irradiated with light 149 (e.g., visible light or ultraviolet light) (Figure 15 (A)).

Next, the portions of the photoresist 159f that were irradiated with the light 149 (exposed portions) are removed to form a resist mask 159 (FIG. 15B). In other words, the resist mask 159 corresponds to the areas of the photoresist 159f that were not reached by the light 149 (unexposed areas) when the photoresist 159f was irradiated with the light 149.

Here, the region of the metal oxide film 208f that contacts the insulating layer 110 in the recess 145 is a region that can later function as a channel formation region of the transistor 200. Therefore, it is preferable that the resist mask 159 is provided so as to have at least a region that contacts the sidewall of the recess 145 (particularly, the side surface of the insulating layer 110). This exposes a part of the metal oxide film 208f (specifically, a part that is located higher than the upper surface of the resist mask 159 relative to the substrate surface).

15B shows an example in which the entire resist mask 159 is located within the recess 145 and the height of the upper surface of the resist mask 159 is lower than the height of the upper surface of the metal oxide film 208f, but this is not a limitation of one embodiment of the present invention. For example, a part of the resist mask 159 may extend outside the recess 145 and the height of the upper surface of the resist mask 159 may be higher than the height of the upper surface of the metal oxide film 208f. In this case, the resist mask 159 has not only a region that fills the recess 145 but also a region that covers the upper surface of the metal oxide film 208f.

Next, the exposed portion of the metal oxide film 208f is removed, and a process is performed to form a semiconductor layer 208 that contacts the sidewalls of the recess 145 (the side of the insulating layer 110, the side of the conductive layer 212a, and the side of the conductive layer 212b) (FIG. 15(C)). For the formation of the semiconductor layer 208, one or both of a wet etching method and a dry etching method can be suitably used. In the region where the semiconductor layer 208 overlaps with the conductive layer 212a and the conductive layer 212b in a plan view, the semiconductor layer 208 contacts the side of the insulating layer 110 in the recess 145, the upper surface and the side of the conductive layer 212a in the recess 145, and the upper surface and the side of the conductive layer 212b in the recess 145. In addition, in the region where the semiconductor layer 208 does not overlap with the conductive layer 212a and the conductive layer 212b in a plan view, the semiconductor layer 208 contacts the side of the insulating layer 110 in the recess 145. By this process, the upper surface of the insulating layer 110 is exposed.

Then, the resist mask 159 remaining in the recess 145 is removed (Figure 16 (A)).

Next, the insulating layer 106 is formed to cover the semiconductor layer 208, the material layer 208m, the conductive layer 212a, the conductive layer 212b, and the insulating layer 110 (FIG. 16B). For example, the PECVD method, the ALD method, or the sputtering method can be suitably used to form the insulating layer 106.

When a metal oxide is used for the semiconductor layer 208, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. When the insulating layer 106 has a function of suppressing oxygen diffusion, oxygen contained in the semiconductor layer 208 is suppressed from diffusing above the insulating layer 106, and an increase in oxygen vacancies ( _VO ) in the semiconductor layer 208 can be suppressed. As a result, a transistor 200 that exhibits favorable electrical characteristics and is highly reliable can be realized.

By increasing the temperature during the formation of the insulating layer 106 functioning as a gate insulating layer, an insulating layer with fewer defects can be obtained. However, if the temperature during the formation of the insulating layer 106 is high, oxygen may be released from the semiconductor layer 208, and oxygen vacancies (V _O ) and V _O H in the semiconductor layer 208 may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180° C. to 450° C., more preferably 200° C. to 450° C., more preferably 250° C. to 450° C., even more preferably 300° C. to 450° C., and even more preferably 300° C. to 400° C. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen release from the semiconductor layer 208 can be suppressed. Therefore, a transistor 200 exhibiting good electrical characteristics and high reliability can be realized.

Before forming the insulating layer 106, a plasma treatment may be performed on the surface of the semiconductor layer 208. The plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 208. Therefore, impurities at the interface between the semiconductor layer 208 and the insulating layer 106 can be reduced, and a highly reliable transistor 200 can be realized. This is particularly suitable for the case where the surface of the semiconductor layer 208 is exposed to the air between the formation of the semiconductor layer 208 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere of, for example, oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. In addition, it is preferable that the plasma treatment and the formation of the insulating layer 106 are performed successively without exposure to the air.

16B shows an example in which the insulating layer 106 forms a cavity 227 surrounded by the insulating layer 106, the material layer 208m, and the insulating layer 102 in the recess 145, but this is not a limitation of one embodiment of the present invention. For example, the insulating layer 106 may be provided in the recess 145 in contact with the lower surfaces (surfaces on the insulating layer 102 side) of the conductive layers 212a and 212b and the upper surface of the insulating layer 102, and may not have a cavity 227.

Next, a film that will become the conductive layer 204 is formed on the insulating layer 106, and the film is processed to form the conductive layer 204 (FIG. 16(C)). Here, at least a part of the conductive layer 204 is formed so as to face the semiconductor layer 208 in the recess 145 via the insulating layer 106. For example, a sputtering method, a thermal CVD method (including a MOCVD method), or an ALD method can be suitably used to form the film.

Next, the insulating layer 195 is formed to cover the conductive layer 204 and the insulating layer 106 (FIG. 7B). The insulating layer 195 can be preferably formed by the PECVD method.

After the insulating layer 195 is formed, a heat treatment may be performed. Note that this heat treatment does not have to be performed. Alternatively, the heat treatment may not be performed here, and may serve as a heat treatment performed in a later step. Also, if there is a high-temperature process (e.g., a film formation process) in a later step, this may serve as the heat treatment.

Through the above steps, a transistor 200 included in the semiconductor device 10 of one embodiment of the present invention can be manufactured (Figures 8(A) and 8(B)).

Next, an example of a manufacturing method for simultaneously forming both the transistor 200 and the transistor 100 in the semiconductor device 10 will be described. Note that explanations of parts that overlap with the previous explanation may be omitted.

Figures 17(A) to 21(C) show cross-sectional views taken along dashed line A1-A2 in Figure 7(A).

First, the insulating layer 102 is formed on a substrate (not shown) that has sufficient heat resistance to withstand the subsequent heat treatment described above. For the method of forming the insulating layer 102, the contents described in FIG. 13 (A) can be referred to.

Next, a film that will become the conductive layer 112a, the conductive layer 212a, and the conductive layer 212b is formed on the insulating layer 102, and the film is processed to form the conductive layer 112a, the conductive layer 212a, and the conductive layer 212b (FIG. 17(A)). For the method of forming the film, etc., the contents described in FIG. 13(A) can be referred to.

Next, insulating layer 110a and insulating layer 110b are formed in this order on insulating layer 102, conductive layer 112a, conductive layer 212a, and conductive layer 212b. The channel width W200 of transistor 200 and the channel length L100 of transistor 100 depend on the film thickness of insulating layer 110b. Therefore, the film thickness of insulating layer 110b may be set according to the electrical characteristics required for transistor 200 and transistor 100. For the method of forming insulating layer 110a and insulating layer 110b, the contents described in FIG. 13B can be referred to.

After the insulating layer 110b is formed, oxygen may be supplied to the insulating layer 110b. For the method of supplying oxygen, see the description of FIG. 13B.

The plasma treatment may also be performed continuously in a vacuum without exposing the surface of the insulating layer 110b to the atmosphere.

Next, it is preferable to perform a planarization process using a CMP method on the upper surface of the insulating layer 110b (Figure 17 (B)). This allows the conductive layer 112b, which will later become the other of the source electrode or drain electrode of the transistor 100, to be formed so as to be embedded accurately in the insulating layer 110.

Next, it is preferable to form a metal oxide layer 137 on the insulating layer 110b (FIG. 17C). By forming the metal oxide layer 137, oxygen can be supplied to the insulating layer 110b. For materials that can be used for the metal oxide layer 137 and a method for forming the metal oxide layer 137, the contents described in FIG. 13C can be referred to.

Next, the metal oxide layer 137 is removed. For the method of removing the metal oxide layer 137, refer to the description in FIG. 13(C).

After removing the metal oxide layer 137, oxygen may be further supplied to the insulating layer 110b. For the method of supplying oxygen, see the description of FIG. 13(C).

The process of planarizing the upper surface of the insulating layer 110b may be performed after the process of supplying oxygen to the insulating layer 110b by the metal oxide layer 137 described above.

Next, a resist mask 156 is formed on the insulating layer 110b. The resist mask 156 is formed in an area that does not overlap with the transistor 100.

Then, the insulating layer 110b is processed through the resist mask 156 to form a recess 142 in the insulating layer 110b (FIG. 18(A)). The recess 142 is formed in a region that overlaps with the conductive layer 112a. To form the recess 142, one or both of a wet etching method and a dry etching method can be suitably used.

Then, the resist mask 156 is removed.

Next, insulating layer 110c is formed on insulating layer 110b (FIG. 18(B)). For the method of forming insulating layer 110c, etc., refer to the contents described in FIG. 14(A).

Next, a conductive film 112f that will become the conductive layer 212b is formed on the insulating layer 110c (FIG. 18C). The conductive film 112f can be formed by, for example, a sputtering method.

Then, the conductive film 112f is planarized using a CMP method until the upper surface of the insulating layer 110c is exposed, and a conductive layer 112s is formed inside the recess 142 (FIG. 19(A)). This process makes the height of the upper surface of the conductive layer 112s roughly equal to the height of the upper surface of the insulating layer 110 in the area that does not overlap with the conductive layer 112s.

Next, a resist mask 158 is formed on the conductive layer 112s and the insulating layer 110. The resist mask 158 is formed in an area that does not overlap with the transistor 200 and the transistor 100.

Next, the conductive layer 112s, the insulating layer 110 (insulating layer 110c, insulating layer 110b, and insulating layer 110a), and the insulating layer 102 are processed through the resist mask 158. As a result of this processing, a recess 145 is formed in the insulating layer 110 and the insulating layer 102 in the region overlapping with the transistor 200. Also, in the region overlapping with the transistor 100, an opening 143 is formed in the conductive layer 112s, and an opening 141 is formed in the insulating layer 110. Also, as a result of this processing, the conductive layer 112s becomes the conductive layer 112b having the opening 143 (FIG. 19B). The recess 145 is provided so as to have an area overlapping with the conductive layer 212a and the conductive layer 212b in a plan view. Also, the conductive layer 112a is exposed in the opening 141. The recess 145, the opening 143, and the opening 141 can be formed by using either or both of a wet etching method and a dry etching method. The recess 145, the opening 143, and the opening 141 can be formed all at once, or the processing conditions can be changed for each of them. For example, the processing conditions for the formation of the opening 143 and the processing conditions for the formation of the opening 141 can be changed. Also, for example, the processing conditions can be changed after the formation of the opening 143 is performed first, and then the processing conditions can be changed to form the opening 141 and the recess 145 all at once.

Then, the resist mask 158 is removed.

Next, a metal oxide film 208f that will become the semiconductor layer 208 and the semiconductor layer 108 is formed on the conductive layer 112a, the conductive layer 112b, the insulating layer 110, and the insulating layer 102. The metal oxide film 208f is provided in contact with the upper surface of the conductive layer 112a, the upper surface and side surface of the conductive layer 112b, the upper surface and side surface of the insulating layer 110, the upper surface and side surface of the conductive layer 212a, and the upper surface and side surface of the conductive layer 212b. At this time, the metal oxide film 208f is cut at the ends of the conductive layer 212a and the conductive layer 212b that are exposed in the recess 145, and the cut portions are formed as the material layer 208m on the bottom surface of the recess 145 (FIG. 19(C)).

In this way, in one embodiment of the present invention, the semiconductor layer 208 can be formed in a self-aligned manner only on the sidewalls of the recess 145 (the side surfaces of the insulating layer 110, the side surfaces of the conductive layer 212a, and the side surfaces of the conductive layer 212b) by simply depositing the metal oxide film 208f. Therefore, after forming the metal oxide film 208f, a separate process for separating the region of the metal oxide film 208f on the sidewalls in the recess 145 from the region on the bottom surface in the recess 145 can be eliminated. At the same time, a metal oxide film that will later become the semiconductor layer 108 can be formed on the inner walls and bottom surfaces of the openings 143 and 141. Therefore, the transistors 200 and 100 can be formed simultaneously, which reduces the total number of steps in the manufacture of a semiconductor device.

For details on the method of forming the metal oxide film 208f, please refer to the contents described in FIG. 14(C).

Before forming the metal oxide film 208f, it is preferable to perform at least one of a process for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a process for supplying oxygen into the insulating layer 110. For details of the process, refer to the contents described in FIG. 14(C).

When the semiconductor layer 208 and the semiconductor layer 108 have a laminated structure, it is preferable to deposit the next metal oxide film in succession after depositing the first metal oxide film without exposing the surface to the air.

After the metal oxide film 208f is formed, heat treatment may be performed. By performing the heat treatment, oxygen can be effectively supplied from the insulating layer 110 to the metal oxide film 208f. For details of the heat treatment, refer to the contents described in FIG. 14C.

Next, a positive photoresist 159f is applied onto the metal oxide film 208f and the material layer 208m so as to fill the recess 145, the opening 143, and the opening 141.

Next, light 149 (e.g., visible light or ultraviolet light) is irradiated onto the entire surface of the photoresist 159f (Figure 20 (A)).

Next, the portions of the photoresist 159f that were irradiated with the light 149 (exposed portions) are removed to form a resist mask 159 (FIG. 20(B)). In other words, the resist mask 159 corresponds to the areas of the photoresist 159f that were not reached by the light 149 (unexposed areas) when the photoresist 159f was irradiated with the light 149.

Here, the region of the metal oxide film 208f that contacts the insulating layer 110 in the recess 145 is a region that can later function as a channel formation region of the transistor 200. Also, the region of the metal oxide film 208f that contacts the insulating layer 110 in the opening 141 is a region that can later function as a channel formation region of the transistor 100, and the region that contacts the conductive layer 112b in the opening 143 is a region that will later become the other of the source region or drain region of the transistor 100. Therefore, it is preferable that the resist mask 159 has a region that contacts at least the sidewall of the recess 145 (particularly, the side surface of the insulating layer 110) and the sidewall of the opening 143 (the side surface of the conductive layer 112b). As a result, a part of the metal oxide film 208f (specifically, a part located higher than the upper surface of the resist mask 159 relative to the substrate surface) is exposed.

20B shows an example in which the entire resist mask 159 is located in the recess 145 and in the openings 143 and 141, and the height of the upper surface of the resist mask 159 is lower than the height of the upper surface of the metal oxide film 208f, but this is not a limitation of one embodiment of the present invention. For example, a part of the resist mask 159 may extend outside the recess 145 and the openings 143 and 141, and the height of the upper surface of the resist mask 159 may be higher than the height of the upper surface of the metal oxide film 208f. In this case, the resist mask 159 has not only a region filling the recess 145 and the openings 143 and 141, but also a region covering the upper surface of the metal oxide film 208f.

The photoresist (photoresist 159f) used to form the resist mask 159 is not limited to a positive type, and a negative type may be used. When a negative type photoresist is used, the photoresist is applied onto the insulating layer 110c, and then light 149 is irradiated onto the recess 145 and the area that does not overlap with the opening 143 and the opening 141. The unexposed area of the photoresist (area that was not exposed to light) is then removed, thereby forming the resist mask 159 in the area that overlaps with the recess 145 and the opening 143 and the opening 141.

Next, the exposed portion of the metal oxide film 208f is removed, and a process is performed to form the semiconductor layer 208 in contact with the sidewalls of the recess 145 (sides of the insulating layer 110, the conductive layer 212a, and the conductive layer 212b), and the semiconductor layer 108 in contact with the sidewalls of the opening 143 (sides of the conductive layer 112b), and the sidewalls (sides of the insulating layer 110) and bottom surface (top surface of the conductive layer 112a) of the opening 141 (FIG. 20(C)). One or both of the wet etching method and the dry etching method can be suitably used to form the semiconductor layer 208 and the semiconductor layer 108. In the region where the semiconductor layer 208 overlaps with the conductive layer 212a and the conductive layer 212b in a plan view, the semiconductor layer 208 contacts the side of the insulating layer 110 in the recess 145, the top surface and side of the conductive layer 212a in the recess 145, and the top surface and side of the conductive layer 212b in the recess 145. In addition, in a plan view, in the region not overlapping with the conductive layer 212a and the conductive layer 212b, the semiconductor layer 108 contacts the side surface of the insulating layer 110 in the recess 145. The semiconductor layer 108 also contacts the side surface of the conductive layer 112b in the opening 143, the side surface of the insulating layer 110 in the opening 141, and the top surface of the conductive layer 112a in the opening 141. By this treatment, the top surface of the conductive layer 112b and the top surface of the insulating layer 110 are exposed.

Next, the resist mask 159 remaining in the recess 145, the opening 143, and the opening 141 is removed (Figure 21 (A)).

Next, the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b, the semiconductor layer 208, the material layer 208m, the conductive layer 212a, the conductive layer 212b, and the insulating layer 110 (FIG. 21(B)). For the method of forming the insulating layer 106, the contents described in FIG. 16(B) can be referred to.

Before forming the insulating layer 106, the surfaces of the semiconductor layer 208 and the semiconductor layer 108 may be subjected to plasma treatment. The plasma treatment can reduce impurities such as water adsorbed on the surfaces of the semiconductor layer 208 and the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 208 and the insulating layer 106 and impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and highly reliable transistors 200 and 100 can be realized. This is particularly suitable for the case where the surfaces of the semiconductor layer 208 and the semiconductor layer 108 are exposed to the air between the formation of the semiconductor layer 208 and the semiconductor layer 108 and the formation of the insulating layer 106. For details of the plasma treatment, refer to the contents described in FIG. 16B.

21B shows an example in which the insulating layer 106 forms a cavity 227 surrounded by the insulating layer 106, the material layer 208m, and the insulating layer 102 in the recess 145, but this is not a limitation of one embodiment of the present invention. For example, the insulating layer 106 may be provided in the recess 145 in contact with the lower surfaces (surfaces on the insulating layer 102 side) of the conductive layers 212a and 212b and the upper surface of the insulating layer 102, and may not have a cavity 227.

Next, a film that will become the conductive layer 204 is formed on the insulating layer 106, and the film is processed to form the conductive layer 204 and the conductive layer 104 (FIG. 21(C)). Here, at least a part of the conductive layer 204 is formed so as to face the semiconductor layer 208 in the recess 145 through the insulating layer 106. Also, at least a part of the conductive layer 104 is formed so as to face the semiconductor layer 108 through the insulating layer 106 in the opening 143 and the opening 141. For the method of forming the film, etc., refer to the contents described in FIG. 16(C).

Next, the insulating layer 195 is formed to cover the conductive layer 204, the conductive layer 104, and the insulating layer 106 (FIG. 7B). The above description can be referred to for the method of forming the insulating layer 195.

By the above steps, both the transistor 100 and the transistor 200 included in the semiconductor device 10 of one embodiment of the present invention can be manufactured at the same time (Figures 7(A) to 7(C)).

By using the manufacturing method of one embodiment of the present invention, a transistor 100 with a short channel length and a transistor 200 with a longer channel length can be formed on the same surface with good productivity. For example, by applying the transistor 100 to a transistor that requires a large on-state current and the transistor 200 to a transistor that requires high saturation, a high-performance semiconductor device 10 that utilizes the advantages of each transistor can be realized.

This embodiment and the corresponding drawings, etc. can be implemented by appropriately combining at least a part of them with other embodiments or examples described in this specification. In addition, the multiple configurations shown in this embodiment and the corresponding drawings, etc. can be appropriately combined with each other.

(Embodiment 4)
In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

The display device of this embodiment can be a high-resolution display device or a large display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, in the display section of a wristwatch-type or bracelet-type information terminal (wearable device), as well as in the display section of a wearable device that can be worn on the head, such as a head-mounted display (HMD) or other VR device, or a glasses-type AR device.

The semiconductor device according to one embodiment of the present invention can be used in a display device or a module having the display device. Examples of the module having the display device include a module in which a connector such as a flexible printed circuit (hereinafter, referred to as FPC) or a TCP (Tape Carrier Package) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a COG (Chip On Glass) method or a COF (Chip On Film) method.

The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also called sensor elements) that can detect the proximity or contact of a detectable object such as a finger can be applied to the display device.

Sensor types include, for example, capacitive type, resistive film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.

Examples of the capacitance type include the surface capacitance type and the projected capacitance type. Examples of the projected capacitance type include the self-capacitance type and the mutual capacitance type. The mutual capacitance type is preferable because it allows simultaneous multi-point detection.

Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell touch panel is one in which electrodes constituting a sensing element are provided on one or both of a substrate supporting a display element (also called a display device) and an opposing substrate.

<Configuration Example 1>
FIG. 22A shows a perspective view of a display device 50A.

Display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together. In FIG. 22(A), substrate 152 is indicated by a dashed line.

The display device 50A has a display portion 162, a connection portion 140, a circuit portion 164, a conductive layer 165, etc. FIG. 22(A) shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in FIG. 22(A) can also be said to be a display module having the display device 50A, an IC, and an FPC.

The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 22(A) shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion. In the connection portion 140, the common electrode of the display element and the conductive layer are electrically connected, and a potential can be supplied to the common electrode.

The circuit portion 164 has, for example, a scanning line driver circuit (also called a gate driver). The circuit portion 164 may also have both a scanning line driver circuit and a signal line driver circuit (also called a source driver).

The conductive layer 165 has a function of supplying signals and power to the display unit 162 and the circuit unit 164. The signals and power are input to the conductive layer 165 from the outside via the FPC 172, or are input to the conductive layer 165 from the IC 173.

Figure 22 (A) shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like. For example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173. Note that the display device 50A and the display module may be configured without an IC. Also, the IC may be mounted on an FPC by a COF method, or the like.

The semiconductor device of one embodiment of the present invention can be used, for example, as one or both of the display portion 162 and the circuit portion 164 of the display device 50A.

For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, the reliability of the display device can be improved by using it in the display device.

The display unit 162 is an area in the display device 50A that displays an image, and has a number of periodically arranged pixels 210. Figure 22 (A) shows an enlarged view of one pixel 210.

The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied. Examples of pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

The pixel 210 shown in FIG. 22(A) has a pixel 230R that emits red light, a pixel 230G that emits green light, and a pixel 230B that emits blue light. A full-color display can be realized by configuring one pixel 210 with the pixels 230R, 230G, and 230B. The pixels 230R, 230G, and 230B each function as a subpixel. In addition, the display device 50A shown in FIG. 22(A) shows an example in which the pixels 230 that function as subpixels are arranged in a stripe array. The number of subpixels that configure one pixel 210 is not limited to three, and may be four or more. For example, the pixel 210 may have four subpixels that emit R, G, B, and white (W) light. Or, the pixel 210 may have four subpixels that emit R, G, B, and Y light.

Pixel 230R, pixel 230G, and pixel 230B each have a display element and a circuit that controls the driving of the display element.

Various elements can be used as the display element, including, for example, a liquid crystal element (also called a liquid crystal device) and a light-emitting device. In addition, a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element, a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type, etc., can also be used. In addition, a QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot materials may also be used.

Display devices using liquid crystal elements include, for example, transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

Modes that can be used in display devices using liquid crystal elements include, for example, vertical alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetrically aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, ECB (Electrically Examples of VA modes include a Multi-Domain Vertical Alignment (MVA) mode, a Patterned Vertical Alignment (PVA) mode, and an Advanced Super View (ASV) mode.

Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), ferroelectric liquid crystal, and antiferroelectric liquid crystal. Depending on the conditions, these liquid crystal materials can exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, a blue phase, and the like. In addition, either positive type liquid crystal or negative type liquid crystal can be used as the liquid crystal material, and can be selected according to the mode or design to be applied.

Examples of light-emitting devices include self-emitting light-emitting devices such as LEDs, OLEDs (organic LEDs), and semiconductor lasers. Examples of LEDs that can be used include mini LEDs and micro LEDs.

Examples of light-emitting materials that light-emitting devices have include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF materials), and inorganic compounds (quantum dot materials, etc.).

The light emitting device can emit light of infrared, red, green, blue, cyan, magenta, yellow, or white. The color purity can be increased by providing the light emitting device with a microcavity structure.

Of the pair of electrodes that a light-emitting device has, one electrode functions as an anode and the other electrode functions as a cathode.

Note that the display device of one embodiment of the present invention may be a top emission type that emits light in a direction opposite to the substrate on which the light-emitting device is formed, a bottom emission type that emits light toward the substrate on which the light-emitting device is formed, or a dual emission type that emits light on both sides.

In this embodiment, we will mainly use an example in which a light-emitting device is used as a display element.

Figure 22 (B) is a block diagram illustrating the display device 50A. The display device 50A has a display unit 162 and a circuit unit 164. The display unit 162 has a plurality of periodically arranged pixels 230 (pixels 230[1,1] to 230[m,n], where m and n are each independently an integer of 2 or more). The circuit unit 164 has a first driver circuit unit 231 and a second driver circuit unit 232.

The circuit included in the first drive circuit unit 231 functions, for example, as a scanning line drive circuit. The circuit included in the second drive circuit unit 232 functions, for example, as a signal line drive circuit. Note that some kind of circuit may be provided at a position facing the first drive circuit unit 231 across the display unit 162. Some kind of circuit may be provided at a position facing the second drive circuit unit 232 across the display unit 162.

The circuit portion 164 may include various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit. The circuit portion 164 may include transistors, capacitor elements, and the like. The transistors included in the circuit portion 164 may be formed in the same process as the transistors included in the pixel 230.

The display device 50A has wirings 236 that are arranged substantially parallel to each other and whose potential is controlled by a circuit included in the first drive circuit unit 231, and wirings 238 that are arranged substantially parallel to each other and whose potential is controlled by a circuit included in the second drive circuit unit 232. Note that FIG. 22B shows an example in which wirings 236 and 238 are connected to pixel 230. However, wirings 236 and 238 are just an example, and wirings connected to pixel 230 are not limited to wirings 236 and 238.

In the semiconductor device according to one embodiment of the present invention, a VFET having a channel length of submicron size and a large on-current and a VLFET having a long channel length and high saturation can be formed by using some common steps. An oxide semiconductor (OS) can be preferably used for the channel formation region of these transistors, and the transistors can have a small off-current. The semiconductor device according to one embodiment of the present invention can be preferably used for one or both of the display portion 162 and the circuit portion 164. In addition, the semiconductor device according to one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all the transistors included in the display device can be OS transistors. By using OS transistors for all the transistors included in the display device in this way, it is possible to achieve an effect of reducing manufacturing costs.

<Configuration Example 2>
As a circuit that can be used for the circuit portion 164, a latch circuit will be taken as an example to describe a configuration example.

Figure 23 (A) is a circuit diagram showing an example of the configuration of a latch circuit LAT. The latch circuit LAT shown in Figure 23 (A) has transistors Tr31, Tr33, Tr35, Tr36, a capacitance element C31, and an inverter circuit INV. In Figure 23 (A), the node to which one of the source or drain of transistor Tr33, the gate of transistor Tr35, and one electrode of the capacitance element C31 are electrically connected is referred to as node N.

In the latch circuit LAT shown in FIG. 23A, when a high potential signal is input to the terminal SMP, the transistor Tr33 is turned on. As a result, the potential of the node N becomes a potential corresponding to the potential of the terminal ROUT, and data corresponding to the signal input from the terminal ROUT to the latch circuit LAT is written to the latch circuit LAT. After the data is written to the latch circuit LAT, when the potential of the terminal SMP is set to a low potential, the transistor Tr33 is turned off. As a result, the potential of the node N is held, and the data written to the latch circuit LAT is held. Specifically, for example, when the potential of the node N is low, data with a value of "0" is held in the latch circuit LAT, and when the potential of the node N is high, data with a value of "1" is held in the latch circuit LAT.

It is preferable to use a transistor with a small off-state current for the transistor Tr33. An OS transistor can be suitably used for the transistor Tr33. This allows the latch circuit LAT to retain data for a long period of time. This reduces the frequency with which data is rewritten to the latch circuit LAT.

In this specification, writing data to the latch circuit LAT such that the signal input from terminal SP2 is output to terminal LIN may be simply referred to as "writing data to the latch circuit LAT." In other words, writing data with a value of "1" to the latch circuit LAT may be simply referred to as "writing data to the latch circuit LAT."

A semiconductor device according to one embodiment of the present invention can be preferably used for the latch circuit LAT. For example, the transistor 100 or the transistor 200 shown in FIG. 7B or the like can be used for one or more of the transistors Tr31, Tr33, Tr35, and Tr36.

A configuration example of the inverter circuit INV is shown in FIG. 23(B). The inverter circuit INV has transistors Tr41, Tr43, Tr45, Tr47, and a capacitance element C41.

By configuring the latch circuit LAT as shown in FIG. 23(A) and the inverter circuit INV as shown in FIG. 23(B), all the transistors in the latch circuit LAT can be transistors of the same polarity, for example, n-channel transistors. As a result, for example, in addition to transistor Tr33, transistors Tr31, Tr35, Tr36, Tr41, Tr43, Tr45, and Tr47 can be OS transistors. Therefore, all the transistors in the latch circuit LAT can be manufactured in the same process.

A semiconductor device according to one embodiment of the present invention can be preferably used for the inverter circuit INV. For example, the transistor 100 or the transistor 200 shown in FIG. 7B or the like can be used for one or more of the transistors Tr41, Tr43, Tr45, and Tr47.

For transistors that require high saturation, one or more of the transistors 20 and 200 can be preferably used. Furthermore, by using the transistor 100, the occupied area can be reduced, and a display device with a narrow frame can be obtained. Furthermore, the transistor 100 can be preferably used for transistors that require a large on-current. This allows a display device with high performance to be obtained.

<Configuration Example 3>
24A shows a configuration example of a pixel 230. The pixel 230 includes a pixel circuit 51 and a light-emitting device 61.

The pixel circuit 51 shown in FIG. 24A is a 2Tr1C type pixel circuit having a transistor 52A, a transistor 52B, and a capacitor 53. Note that there is no particular limitation on the pixel circuit that can be applied to the display device of one embodiment of the present invention.

The anode of the light-emitting device 61 is electrically connected to one of the source or drain of the transistor 52B and one electrode of the capacitance element 53. The other of the source or drain of the transistor 52B is electrically connected to the wiring ANO. The gate of the transistor 52B is electrically connected to one of the source or drain of the transistor 52A and the other electrode of the capacitance element 53. The other of the source or drain of the transistor 52A is electrically connected to the wiring GL. The gate of the transistor 52A is electrically connected to the wiring GL. The cathode of the light-emitting device 61 is electrically connected to the wiring VCOM.

The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 238. The wiring VCOM is a wiring that provides a potential for supplying a current to the light-emitting device 61. The transistor 52A has a function of controlling the conductive state or non-conductive state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

Transistor 52B has a function of controlling the amount of current flowing through light-emitting device 61. Capacitive element 53 has a function of holding the gate potential of transistor 52B. The intensity of the light emitted by light-emitting device 61 is controlled according to an image signal supplied to the gate of transistor 52B.

A backgate may be provided for some or all of the transistors included in the pixel circuit 51. The pixel circuit 51 shown in FIG. 24(A) shows a configuration in which the transistor 52B has a backgate, and the backgate is electrically connected to one of the source or drain of the transistor 52B. Note that the backgate of the transistor 52B may be electrically connected to the gate of the transistor 52B.

The above-mentioned semiconductor device can be suitably used in the pixel circuit 51. Compared with the transistor 52A that functions as a selection transistor for controlling the selection state of the pixel 230, the transistor 52B that functions as a drive transistor for controlling the current flowing through the light-emitting device 61 preferably has high saturation. By applying one of the transistors 20 and 200, which have a long channel length, to the transistor 52B, a highly reliable display device can be obtained. In addition, by applying the transistor 100 to the transistor 52A, the area occupied by the pixel circuit 51A can be reduced, resulting in a high-definition display device.

Note that the transistor 100 may also be used as the transistor 52B. By using a transistor with a short channel length as the transistor 52B, a display device with high brightness can be obtained. In addition, the area occupied by the pixel circuit 51 can be reduced, and a high-definition display device can be obtained.

Figure 24 (B) shows an example of a configuration different from that of the pixel 230 shown in Figure 24 (A). The pixel 230 has a pixel circuit 51A and a light-emitting device 61.

The pixel circuit 51A shown in FIG. 24(B) differs from the pixel circuit 51 shown in FIG. 24(A) mainly in that it has a transistor 52C. The pixel circuit 51A is a 3Tr1C type pixel circuit having a transistor 52A, a transistor 52B, a transistor 52C, and a capacitance element 53.

One of the source or drain of transistor 52C is electrically connected to one of the source or drain of transistor 52B. The other of the source or drain of transistor 52C is electrically connected to wiring V0. For example, a reference potential is supplied to wiring V0. The gate of transistor 52C is electrically connected to wiring GL.

Transistor 52C has a function of controlling the conductive or non-conductive state between one of the source electrode or drain electrode of transistor 52B and wiring V0 based on the potential of wiring GL. The reference potential of wiring V0 provided via transistor 52C can suppress variations in the gate-source voltage of transistor 52B.

The wiring V0 can be used to obtain a current value that can be used to set pixel parameters. Specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting device 61 to the outside. The current output to the wiring V0 can be converted to a voltage by a source follower circuit and output to the outside, or converted to a digital signal by an AD converter and output to the outside.

The above-mentioned semiconductor device can be suitably used for the pixel circuit 51A. By applying one of the transistors 20 and 200, which have a long channel length, to the transistor 52B, a highly reliable display device can be obtained. In addition, by applying the transistor 100 to the transistors 52A and 52C, the area occupied by the pixel circuit 51A can be reduced, and a high-definition display device can be obtained. Note that the transistor 100 may also be applied to the transistor 52B.

A configuration example of pixel circuit 51 is shown in FIG. 24(C). FIG. 24(C) is a cross-sectional view of pixel circuit 51. FIG. 24(C) shows an excerpt of transistor 52A, transistor 52B, and pixel electrode of light-emitting device 61. Note that the electrical connection between transistor 52A and transistor 52B is omitted.

Transistor 52A has a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. Transistor 52B has an insulating layer 106, a semiconductor layer 208, a conductive layer 204, a conductive layer 212a, and a conductive layer 212b. The above description can be referred to for transistors 52A and 52B, so detailed description is omitted.

The transistor 52A and the transistor 52B are provided on the insulating layer 102. An insulating layer 195 is provided to cover the transistor 52A, the transistor 52B, and the capacitor 53, an insulating layer 233 is provided to cover the insulating layer 195, and an insulating layer 235 is provided to cover the insulating layer 233. A light-emitting device 61 can be provided on the insulating layer 235. FIG. 24C shows a pixel electrode 111 that functions as one electrode of the light-emitting device 61. The insulating layer 195, the insulating layer 233, the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c have a first opening that reaches the conductive layer 212b, and a conductive layer 234 is provided to cover the first opening. The conductive layer 234 is electrically connected to the conductive layer 212b through the first opening. The insulating layer 235 has a second opening that reaches the conductive layer 234, and the pixel electrode 111 is provided to cover the second opening. The pixel electrode 111 is electrically connected to the conductive layer 234 through the second opening. The insulating layer 195 can be described in the above, so detailed description is omitted. The insulating layer 233 and the insulating layer 235 have the function of reducing unevenness caused by the transistors 52A, 52B, and 52C, and making the surface on which the light-emitting device 61 is formed more flat. Note that in this specification and the like, the insulating layer 233 and the insulating layer 235 may each be referred to as a planarization layer.

It is preferable to use an organic insulating film for each of the insulating layers 233 and 235. Examples of materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. The insulating layer 235 may have a laminated structure of an organic insulating film and an inorganic insulating film. It is preferable to use a laminated structure of an organic insulating film and an inorganic insulating film on the organic insulating film. This allows the inorganic insulating film to function as an etching protection layer when forming the light-emitting device 61. Specifically, it is possible to prevent a part of the insulating layer 235 from being etched when the pixel electrode 111 is formed, and a recess from being formed in the insulating layer 235. Alternatively, a recess may be provided in the insulating layer 235 when the pixel electrode 111 is formed. Similarly, the insulating layer 233 may have a laminated structure of an organic insulating film and an inorganic insulating film.

<Configuration Example 4>
25 shows an example of a configuration different from the above. The display device 50B has a configuration in which a pixel circuit, a driver circuit, and the like are provided on a substrate 310. The display device 50B has an element layer 71, an element layer 73, an element layer 75, and a wiring layer 77. The wiring layer 77 is a layer in which wirings are provided.

The element layer 71 has a substrate 310, and a transistor 300 is formed on the substrate 310. A wiring layer 77 is provided above the transistor 300, and wiring is provided in the wiring layer 77 to electrically connect the transistor 300, the transistor MTCK, the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B. An element layer 73 and an element layer 75 are provided above the wiring layer 77, and the element layer 73 has the transistor MTCK and the like. The element layer 75 has the light-emitting device 130 (in FIG. 25, the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B) and the like.

The transistor 300 may be a transistor included in the element layer 71. The transistor MTCK may be a transistor included in the element layer 73. The light-emitting device 130 may be a light-emitting device included in the element layer 75.

For example, a semiconductor substrate (for example, a single crystal substrate made of silicon or germanium) can be used for the substrate 310. In addition to a semiconductor substrate, for example, a silicon-on-insulator (SOI) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film can be used for the substrate 310. In this embodiment, the substrate 310 is described as a semiconductor substrate having silicon as a material. Therefore, the transistor included in the element layer 71 can be a Si transistor.

The transistor 300 has an element isolation layer 312, a conductive layer 316, an insulating layer 315, an insulating layer 317, a semiconductor region 313 formed of a part of the substrate 310, and a low resistance region 314a and a low resistance region 314b functioning as a source region or a drain region. Therefore, the transistor 300 is a Si transistor. Note that FIG. 25 shows a configuration in which one of the source and drain of the transistor 300 is electrically connected to a conductive layer 330, a conductive layer 356, and a conductive layer 514 described later through a conductive layer 328 described later, but the electrical connection configuration of the display device of one embodiment of the present invention is not limited to this. The display device of one embodiment of the present invention may have a configuration in which, for example, the gate of the transistor 300 is electrically connected to the conductive layer 514 through the conductive layer 328.

The transistor 300 can be made into a Fin type by, for example, covering the upper surface and the side surface in the channel width direction of the semiconductor region 313 with the conductive layer 316 via the insulating layer 315 that functions as a gate insulating layer. By making the transistor 300 into a Fin type, the effective channel width can be increased, and the on characteristics of the transistor 300 can be improved. In addition, the contribution of the electric field of the gate electrode can be increased, and therefore the off characteristics of the transistor 300 can be improved. The transistor 300 may be a planar type instead of a Fin type.

The transistor 300 may be either a p-channel type or an n-channel type. Alternatively, multiple transistors 300 may be provided, and both p-channel and n-channel types may be used.

The region in which the channel of the semiconductor region 313 is formed, the region nearby, and the low resistance region 314a and low resistance region 314b that become the source region or drain region preferably contain a silicon-based semiconductor, specifically, single crystal silicon. Alternatively, each of the above-mentioned regions may be formed using, for example, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be, for example, a HEMT (High Electron Mobility Transistor) using gallium arsenide and aluminum gallium arsenide.

The conductive layer 316 functioning as the gate electrode can be made of a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron or aluminum. Alternatively, the conductive layer 316 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material.

Note that since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use one or both of titanium nitride and tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use one or both of tungsten and aluminum as a laminated material for the conductor, and in particular, it is preferable to use tungsten in terms of heat resistance.

The element isolation layer 312 is provided to isolate the multiple transistors formed on the substrate 310 from each other. The element isolation layer can be formed, for example, by using a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

On the transistor 300 shown in FIG. 25, an insulating layer 320 and an insulating layer 322 are stacked in this order from the substrate 310 side.

For example, one or more materials selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride may be used as insulating layer 320 and insulating layer 322.

The insulating layer 322 may function as a planarizing film that flattens steps caused by the insulating layer 320 and the transistor 300 covered by the insulating layer 322. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method to improve flatness.

A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and connects to the transistor MTCK and the like that are provided above the insulating layer 322. The conductive layer 328 functions as a plug or wiring. For this reason, the conductive layer 328 can be made of a material that can be applied to the conductive layer MPG.

In the display device 50B, a wiring layer 77 is provided on the transistor 300. The wiring layer 77 includes, for example, an insulating layer 324, an insulating layer 326, a conductive layer 330, an insulating layer 350, an insulating layer 352, an insulating layer 354, and a conductive layer 356.

An insulating layer 324 and an insulating layer 326 are laminated in this order on the insulating layer 322 and the conductive layer 328. In addition, an opening is formed in the insulating layer 324 and the insulating layer 326 in the region overlapping the conductive layer 328. Furthermore, the conductive layer 330 is embedded in the opening.

On the insulating layer 326 and on the conductive layer 330, insulating layers 350, 352, and 354 are laminated in this order. In addition, in the region overlapping with the conductive layer 330, openings are formed in the insulating layers 350, 352, and 354. Furthermore, the conductive layer 356 is embedded in the openings.

The conductive layer 330 and the conductive layer 356 function as a plug or wiring that connects to the transistor 300. Note that the conductive layer 330 and the conductive layer 356 can be formed using a material similar to that of the conductive layer 328 or the conductive layer 596 described above.

For example, the insulating layers 324 and 350 are preferably made of an insulator having a barrier property against one or more of hydrogen, oxygen, and water, similar to the insulating layer 592. For the insulating layers 326, 352, and 354, it is preferable to use an insulator having a relatively low dielectric constant, similar to the insulating layer 594, in order to reduce the parasitic capacitance generated between wirings. The insulating layers 326, 352, and 354 function as an interlayer insulating film and a planarizing film. The conductive layer 356 preferably includes a conductor having a barrier property against one or more of hydrogen, oxygen, and water.

For example, tantalum nitride may be used as a conductor having a barrier property against hydrogen. By stacking tantalum nitride and highly conductive tungsten, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulating layer 350 having a barrier property against hydrogen.

An insulating layer 512 is provided above the insulating layer 354 and the conductive layer 356. An insulating layer IS1 is provided on the insulating layer 512. A conductive layer 514 that functions as a plug or wiring is embedded in the insulating layer IS1 and the insulating layer 512. This electrically connects one of the source or drain of the transistor MTCK to one of the source or drain of the transistor 300. For example, a material that can be used for the conductive layer MPG can be used for the conductive layer 514.

A transistor MTCK is provided on the insulating layer IS1 and the conductive layer 514. An insulating layer IS3 is formed above the transistor MTCK. An insulating layer IS2 is formed below the insulating layer IS3. An insulating layer 574 and an insulating layer 581 are stacked in this order on the insulating layer IS3. A conductive layer MPG that functions as a plug or wiring is embedded in the insulating layer GI1, the insulating layer IS2, the insulating layer IS3, the insulating layer 574, and the insulating layer 581. Note that the insulating layers, conductive layers, and semiconductor layers around the transistor MTCK can be referred to in embodiment 2.

The insulating layer 574 preferably has a function of suppressing the diffusion of impurities such as water and hydrogen (e.g., hydrogen atoms and/or hydrogen molecules). In other words, the insulating layer 574 preferably functions as a barrier insulating film that suppresses the impurities from being mixed into the transistor MTCK. The insulating layer 574 also preferably has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and/or oxygen molecules). For example, the insulating layer 574 preferably has lower oxygen permeability than the insulating layer IS2 and the insulating layer IS3.

Therefore, the insulating layer 574 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen. Therefore, the insulating layer 574 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N ₂ O, NO, and NO ₂ ), and copper atoms (through which the above impurities are unlikely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules) (through which the above oxygen is unlikely to permeate).

As an insulator having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, an insulator containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum may be used in a single layer or a laminate. Specifically, as an insulator having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be mentioned. In addition, as an insulator having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, an oxide containing aluminum and hafnium (hafnium aluminate) can be mentioned. Examples of insulators that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxynitride, and silicon nitride.

In particular, it is preferable to use aluminum oxide or silicon nitride for the insulating layer 574. This can prevent impurities such as water and hydrogen from diffusing from above the insulating layer 574 to the transistor MTCK. Alternatively, it can prevent oxygen contained in the insulating layer IS3, etc. from diffusing above the insulating layer 574.

The insulating layer 581 is a film that functions as an interlayer film, and preferably has a lower dielectric constant than the insulating layer 574. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance occurring between wirings can be reduced. For example, the relative dielectric constant of the insulating layer 581 is preferably less than 4, and more preferably less than 3. Also, for example, the relative dielectric constant of the insulating layer 581 is preferably 0.7 times or less the relative dielectric constant of the insulating layer 574, and more preferably 0.6 times or less. By using a material with a low dielectric constant as the interlayer film for the insulating layer 581, the parasitic capacitance occurring between wirings can be reduced.

It is preferable that the concentration of impurities such as water and hydrogen in the insulating layer 581 is reduced. In this case, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used for the insulating layer 581. For example, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies can be used for the insulating layer 581. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating. In addition, resin can be used for the insulating layer 581. In addition, the material that can be applied to the insulating layer 581 may be an appropriate combination of the above-mentioned materials.

Insulating layer 592 and insulating layer 594 are laminated in this order on insulating layer 574 and insulating layer 581.

For the insulating layer 592, it is preferable to use an insulating film (referred to as a barrier insulating film) having a barrier property that prevents impurities such as water and hydrogen from diffusing from the substrate 310 and the transistor MTCK to a region above the insulating layer 592 (for example, a region where the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B are provided). Therefore, it is preferable to use an insulating material for the insulating layer 592 that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (the impurities are unlikely to permeate through the insulating material). Depending on the situation, it is preferable to use an insulating material for the insulating layer 592 that has a function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N ₂ O, NO, and NO ₂ ), and copper atoms (the oxygen is unlikely to permeate through the insulating material). Alternatively, it is preferable to have a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules).

As a film with barrier properties against hydrogen, for example, silicon nitride formed by the CVD method can be used.

The amount of desorption of hydrogen can be analyzed, for example, by thermal desorption spectrometry (TDS). For example, the amount of desorption of hydrogen from the insulating layer 324 may be 10×10 15 atoms/cm 2 or less, preferably 5×10 ¹⁵ atoms/cm ² or less, calculated per area of the insulating layer 324, when the film surface temperature is in the range of 50° C. to 500° C., as calculated in terms of ^hydrogen atoms, in ^TDS .

The insulating layer 594 is preferably an interlayer film with a low dielectric constant, similar to the insulating layer 581. For this reason, the insulating layer 594 can be made of a material that can be used for the insulating layer 581.

It is preferable that the insulating layer 594 has a lower dielectric constant than the insulating layer 592. For example, the relative dielectric constant of the insulating layer 594 is preferably less than 4, and more preferably less than 3. Also, for example, the relative dielectric constant of the insulating layer 594 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulating layer 592. By using a material with a low dielectric constant as the interlayer film for the insulating layer 594, the parasitic capacitance generated between the wirings can be reduced.

A conductive layer MPG functioning as a plug or wiring is embedded in the insulating layers GI1, IS2, IS3, 574, and 581, and a conductive layer 596 functioning as a plug or wiring is embedded in the insulating layers 592 and 594. In particular, the conductive layer MPG and the conductive layer 596 are electrically connected to a light-emitting device or the like provided above the insulating layer 594. In addition, the conductive layer having the function of a plug or wiring may be given the same reference numeral as a group of multiple structures. In addition, in this specification, the wiring and the plug connected to the wiring may be an integral part. That is, there are cases where a part of the conductive layer functions as a wiring, and cases where a part of the conductive layer functions as a plug.

As the material for each plug and wiring (e.g., conductive layer MPG and conductive layer 596), one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials can be used in a single layer or a laminated layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, it is preferable to form it from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

Insulating layer 598 and insulating layer 599 are formed in order on insulating layer 594 and conductive layer 596.

As with insulating layer 592, insulating layer 598 is preferably made of an insulator having barrier properties against one or more of hydrogen, oxygen, and water. As with insulating layer 594, insulating layer 599 is preferably made of an insulator having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. Insulating layer 599 also functions as an interlayer insulating film and a planarizing film.

The light-emitting device 130 and the connection portion 140 are formed on the insulating layer 599.

The connection portion 140 may be called a cathode contact portion, and is electrically connected to the cathode electrodes of the light-emitting devices 130R, 130G, and 130B. In FIG. 25, the connection portion 140 has one or more conductive layers selected from the conductive layers 182a to 182c described below, at least one conductive layer from the conductive layers 126a to 126c described below, one or more conductive layers selected from the conductive layers 129a to 129c described below, a common layer 114 described below, and a common electrode 115 described below.

The connection portion 140 may be provided so as to surround the four sides of the display portion in a plan view, or may be provided within the display portion (e.g., between adjacent light-emitting devices 130) (not shown).

The light-emitting device 130R has a conductive layer 182a, a conductive layer 126a on the conductive layer 182a, and a conductive layer 129a on the conductive layer 126a. The conductive layers 182a, 126a, and 129a can all be called pixel electrodes, or some of them can be called pixel electrodes. The light-emitting device 130G has a conductive layer 182b, a conductive layer 126b on the conductive layer 182b, and a conductive layer 129b on the conductive layer 126b. As with the light-emitting device 130R, the conductive layers 182b, 126b, and 129b can all be called pixel electrodes, or some of them can be called pixel electrodes. The light-emitting device 130B has a conductive layer 182c, a conductive layer 126c on the conductive layer 182c, and a conductive layer 129c on the conductive layer 126c. As with light-emitting device 130R and light-emitting device 130G, conductive layer 182c, conductive layer 126c, and conductive layer 129c can all be referred to as pixel electrodes, or only some of them can be referred to as pixel electrodes.

For example, a conductive layer functioning as a reflective electrode can be used for the conductive layers 182a to 182c and the conductive layers 126a to 126c. For example, a silver, aluminum, or an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film) can be used as a conductive layer with high reflectivity to visible light for the conductive layer functioning as a reflective electrode. In addition, for the conductive layers 182a to 182c and the conductive layers 126a to 126c, a laminated film of aluminum sandwiched between a pair of titanium (a laminated film in the order of Ti, Al, and Ti) or a laminated film of silver sandwiched between a pair of indium tin oxide (a laminated film in the order of ITO, Ag, and ITO) can be used.

For example, a conductive layer that functions as a reflective electrode may be used for the conductive layers 182a to 182c, and a material with high light-transmitting properties may be used for the conductive layers 126a to 126c. Examples of materials with high light-transmitting properties include an alloy of silver and magnesium and indium tin oxide (sometimes referred to as ITO).

The conductive layers 129a to 129c can be, for example, a conductive layer that functions as a transparent electrode. The conductive layer that functions as a transparent electrode can be, for example, the conductive layer with high light transmittance described above.

A microcavity structure (microresonator structure) may be provided in the light-emitting device 130, which will be described in detail later. The microcavity structure refers to a structure in which the distance between the bottom surface of the light-emitting layer and the top surface of the lower electrode is set to a thickness according to the wavelength of the color of light emitted by the light-emitting layer. In this case, it is preferable to use a conductive material having light-transmitting and light-reflecting properties for the conductive layers 129a to 129c, which are the upper electrodes (common electrodes), and a conductive material having light-reflecting properties for the conductive layers 182a to 182c and the conductive layers 126a to 126c, which are the lower electrodes (pixel electrodes).

A microcavity structure is a structure in which the optical distance between the lower electrode and the light-emitting layer is adjusted to (2n-1)λ/4 (where n is an integer equal to or greater than 1, and λ is the wavelength of the light emission to be amplified). As a result, the light reflected back by the lower electrode (reflected light) causes significant interference with the light that is directly incident on the upper electrode from the light-emitting layer (incident light). This allows the phases of the reflected light and incident light of wavelength λ to be matched, further amplifying the light emission from the light-emitting layer. On the other hand, if the reflected light and incident light have a wavelength other than λ, the phases will no longer match, and the light will attenuate without resonating.

The conductive layer 182a is connected to the conductive layer 596 embedded in the insulating layer 594 through an opening provided in the insulating layer 599. In addition, the end of the conductive layer 126a is located outside the end of the conductive layer 182a. The end of the conductive layer 126a and the end of the conductive layer 129a are aligned or approximately aligned.

The conductive layers 182b, 126b, and 129b in the light-emitting device 130G, and the conductive layers 182c, 126c, and 129c in the light-emitting device 130B are similar to the conductive layers 182a, 126a, and 129a in the light-emitting device 130R, respectively, and therefore will not be described in detail.

Conductive layers 182a, 182b, and 182c have recesses formed therein so as to cover the openings provided in insulating layer 599. Layer 128 is embedded in the recesses.

The layer 128 has a function of planarizing the recesses of the conductive layers 182a to 182c. The conductive layers 126a to 126c are provided on the conductive layers 182a to 182c and on the layer 128, and are electrically connected to the conductive layers 182a to 182c. Therefore, the regions overlapping with the recesses of the conductive layers 182a to 182c can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased.

Layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for layer 128. In particular, layer 128 is preferably formed using an insulating material.

An insulating layer containing an organic material can be suitably used for layer 128. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of these resins can be applied to layer 128. Also, a photosensitive resin can be used for layer 128. Examples of photosensitive resins include positive-type materials and negative-type materials.

By using a photosensitive resin, layer 128 can be manufactured only through the steps of exposure and development, and the influence of dry etching or wet etching on the surfaces of conductive layer 182a, conductive layer 182b, and conductive layer 182c can be reduced. In addition, by forming layer 128 using a negative photosensitive resin, layer 128 can be formed using the same photomask (exposure mask) as that used to form the opening in insulating layer 599.

Light-emitting device 130R has a first layer 113a, a common layer 114 on the first layer 113a, and a common electrode 115 on the common layer 114. Light-emitting device 130G has a second layer 113b, a common layer 114 on the second layer 113b, and a common electrode 115 on the common layer 114. Light-emitting device 130B has a third layer 113c, a common layer 114 on the third layer 113c, and a common electrode 115 on the common layer 114.

The first layer 113a is formed so as to cover the upper and side surfaces of the conductive layer 126a and the upper and side surfaces of the conductive layer 129a. Similarly, the second layer 113b is formed so as to cover the upper and side surfaces of the conductive layer 126b and the upper and side surfaces of the conductive layer 129b. Similarly, the third layer 113c is formed so as to cover the upper and side surfaces of the conductive layer 126c and the upper and side surfaces of the conductive layer 129c. Therefore, the entire area in which the conductive layer 126a, the conductive layer 126b, and the conductive layer 126c are provided can be used as the light-emitting area of the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B, and the aperture ratio of the pixel can be increased.

In light-emitting device 130R, first layer 113a and common layer 114 can be collectively referred to as the EL layer. Similarly, in light-emitting device 130G, second layer 113b and common layer 114 can be collectively referred to as the EL layer. Similarly, in light-emitting device 130B, third layer 113c and common layer 114 can be collectively referred to as the EL layer.

The configuration of the light-emitting device of this embodiment is not particularly limited, and it may be a single structure or a tandem structure.

The first layer 113a, the second layer 113b, and the third layer 113c are processed into an island shape by photolithography. Therefore, the first layer 113a, the second layer 113b, and the third layer 113c have a shape in which the angle between the top surface and the side surface at the end is close to 90 degrees. On the other hand, for example, an organic film formed using FMM tends to become gradually thinner as it approaches the end, and for example, the top surface is formed in a slope shape over a range of 1 μm to 10 μm, making it difficult to distinguish between the top surface and the side surface.

The first layer 113a, the second layer 113b, and the third layer 113c have a clear distinction between the top and side surfaces. As a result, in adjacent first and second layers 113a and 113b, one side surface of the first layer 113a and one side surface of the second layer 113b are arranged opposite each other. This is the same for any combination of the first layer 113a, the second layer 113b, and the third layer 113c.

The first layer 113a, the second layer 113b, and the third layer 113c each have at least a light-emitting layer. For example, it is preferable that the first layer 113a has a light-emitting layer that emits red light, the second layer 113b has a light-emitting layer that emits green light, and the third layer 113c has a light-emitting layer that emits blue light. In addition, each light-emitting layer can be of a color other than the above, such as cyan, magenta, yellow, or white.

The first layer 113a, the second layer 113b, and the third layer 113c preferably have a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. The surfaces of the first layer 113a, the second layer 113b, and the third layer 113c may be exposed during the manufacturing process of the display device, so by providing a carrier transport layer on the light-emitting layer, it is possible to prevent the light-emitting layer from being exposed to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting device.

The common layer 114 has, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or may have a hole transport layer and a hole injection layer stacked together. The common layer 114 is shared by the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B.

The common electrode 115 is shared by the light-emitting devices 130R, 130G, and 130B. As shown in FIG. 25, the common electrode 115 shared by the multiple light-emitting devices is electrically connected to a conductive layer included in the connection portion 140.

The insulating layer 125 preferably functions as a barrier insulating layer against water and/or oxygen. The insulating layer 125 preferably has a function of suppressing the diffusion of water and/or oxygen. The insulating layer 125 preferably has a function of capturing or fixing (also called gettering) water and/or oxygen. The insulating layer 125 has a function of a barrier insulating layer or a gettering function, so that the insulating layer 125 can suppress the intrusion of impurities (typically, water and/or oxygen) that can diffuse from the outside into each light-emitting device. This configuration can provide a highly reliable light-emitting device and a highly reliable display panel.

It is preferable that the insulating layer 125 has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer. In addition, by lowering the impurity concentration in the insulating layer 125, it is possible to improve the barrier properties against water and/or oxygen. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, or preferably both.

An insulating layer having an organic material can be suitably used as the insulating layer 127. It is preferable to use a photosensitive organic resin as the organic material, for example, a photosensitive resin composition containing an acrylic resin. The viscosity of the material of the insulating layer 127 may be 1 cP or more and 1500 cP or less, and preferably 1 cP or more and 12 cP or less. By setting the viscosity of the material of the insulating layer 127 in the above range, the insulating layer 127 having a tapered shape described later can be formed relatively easily. In this specification and the like, the acrylic resin does not only refer to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

Note that the insulating layer 127 only needs to have a tapered shape on the side as described later, and the organic material that can be used for the insulating layer 127 is not limited to the above. For example, the insulating layer 127 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins. In addition, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral (PVB), polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin may be used for the insulating layer 127. In addition, the insulating layer 127 may be made of, for example, a photoresist as a photosensitive resin. In addition, the photosensitive resin may be a positive material or a negative material.

The insulating layer 127 may be made of a material that absorbs visible light. By having the insulating layer 127 absorb the light emitted from the light-emitting device, it is possible to suppress leakage of light (stray light) from the light-emitting device to an adjacent light-emitting device through the insulating layer 127. This can improve the display quality of the display panel. In addition, since the display quality can be improved without using a polarizing plate in the display panel, the display panel can be made lighter and thinner.

Materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorbing properties (e.g., polyimide), and resin materials that can be used in color filters (color filter materials). In particular, it is preferable to use a resin material in which two or more colors of color filter materials are laminated or mixed, as this can enhance the visible light blocking effect. In particular, by mixing three or more colors of color filter materials, it is possible to create a resin layer that is black or close to black.

The insulating layer 127 can be formed using a wet film formation method such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, or knife coating. In particular, it is preferable to form the organic insulating film that becomes the insulating layer 127 by spin coating.

The insulating layer 127 is formed at a temperature lower than the heat resistance temperature of the EL layer. The substrate temperature when forming the insulating layer 127 is typically 200°C or less, preferably 180°C or less, more preferably 160°C or less, more preferably 150°C or less, and more preferably 140°C or less.

The following describes the structure of the insulating layer 127 and other structures, taking the structure of the insulating layer 127 between the light-emitting device 130R and the light-emitting device 130G as an example. The same can be said for the insulating layer 127 between the light-emitting device 130G and the light-emitting device 130B, and the insulating layer 127 between the light-emitting device 130B and the light-emitting device 130R. The following may be described using the end of the insulating layer 127 on the second layer 113b as an example, but the same can be said for the end of the insulating layer 127 on the first layer 113a and the end of the insulating layer 127 on the third layer 113c.

In a cross-sectional view of the display device, the insulating layer 127 preferably has a tapered shape with a taper angle θ1 on the side. The taper angle θ1 is the angle between the side of the insulating layer 127 and the substrate surface. However, it is not limited to the substrate surface, and may be the angle between the top surface of the flat portion of the insulating layer 125 or the top surface of the flat portion of the second layer 113b and the side of the insulating layer 127. Furthermore, by making the side of the insulating layer 127 tapered, the side of the insulating layer 125 and the side of the mask layer 118a may also be tapered.

The taper angle θ1 of the insulating layer 127 is less than 90 degrees, preferably 60 degrees or less, and more preferably 45 degrees or less. By forming the side end of the insulating layer 127 in such a forward tapered shape, the common layer 114 and the common electrode 115 provided on the side end of the insulating layer 127 can be formed with good coverage without causing discontinuities or localized thinning. This improves the in-plane uniformity of the common layer 114 and the common electrode 115, thereby improving the display quality of the display device.

In a cross-sectional view of the display device, the upper surface of the insulating layer 127 preferably has a convex curved shape. The convex curved shape of the upper surface of the insulating layer 127 is preferably a shape that bulges gently toward the center. In addition, the convex curved portion at the center of the upper surface of the insulating layer 127 is preferably a shape that is continuously connected to the tapered portion at the side end. By forming the insulating layer 127 in such a shape, the common layer 114 and the common electrode 115 can be formed with good coverage over the entire insulating layer 127.

The insulating layer 127 is formed in the region between the two EL layers (e.g., the region between the first layer 113a and the second layer 113b). At this time, a part of the insulating layer 127 is disposed in a position sandwiched between a side end of one EL layer (e.g., the first layer 113a) and a side end of the other EL layer (e.g., the second layer 113b).

It is preferable that one end of the insulating layer 127 overlaps with the conductive layer 126a that functions as a pixel electrode, and the other end of the insulating layer 127 overlaps with the conductive layer 126b that functions as a pixel electrode. With this structure, the end of the insulating layer 127 can be formed on a roughly flat region of the first layer 113a (second layer 113b). Therefore, it is relatively easy to process the tapered shape of the insulating layer 127 as described above.

As described above, by providing the insulating layer 127, etc., it is possible to prevent the formation of discontinuities and locally thin areas in the common layer 114 and common electrode 115 from the roughly flat area of the first layer 113a to the roughly flat area of the second layer 113b. This makes it possible to prevent connection failures caused by discontinuities and increases in electrical resistance caused by locally thin areas in the common layer 114 and common electrode 115 between the light-emitting devices.

The display device of this embodiment can narrow the distance between the light-emitting devices. Specifically, the distance between the light-emitting devices, the distance between the EL layers, or the distance between the pixel electrodes can be less than 10 μm, 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the display device of this embodiment has an area where the distance between two adjacent island-shaped EL layers is 1 μm or less, preferably has an area where the distance is 0.5 μm (500 nm) or less, and more preferably has an area where the distance is 100 nm or less. In this way, by narrowing the distance between each light-emitting device, a display device with high definition and large aperture ratio can be provided.

A protective layer 131 is provided on the light-emitting device 130. The protective layer 131 is a film that functions as a passivation film that protects the light-emitting device 130. By providing the protective layer 131 that covers the light-emitting device, it is possible to suppress impurities such as water and oxygen from entering the light-emitting device, and to increase the reliability of the light-emitting device 130. For example, aluminum oxide, silicon nitride, or silicon oxynitride can be used for the protective layer 131.

The protective layer 131 and the substrate 119 are bonded via an adhesive layer 107. A solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting device. In FIG. 25, the space between the substrate 310 and the substrate 119 is filled with the adhesive layer 107, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 107 may be provided so as not to overlap with the light-emitting device. The space may also be filled with a resin different from the adhesive layer 107 provided in a frame shape.

For the adhesive layer 107, various curing adhesives such as ultraviolet-curing photocuring adhesives, reaction-curing adhesives, heat-curing adhesives, and anaerobic adhesives can be used. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. In particular, epoxy resins with low moisture permeability are preferred. Two-part mixed resins may also be used. An adhesive sheet may also be used.

The display device 50B is a top emission type. Light emitted by the light emitting device is emitted to the substrate 119 side. For this reason, it is preferable to use a material that is highly transparent to visible light for the substrate 119. For example, a substrate that is highly transparent to visible light may be selected for the substrate 119 from among the substrates that can be used for the substrate 310. The pixel electrode contains a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

Note that the display device of one embodiment of the present invention may be a bottom emission type in which light emitted from the light-emitting device is emitted toward the substrate 310, rather than a top emission type. In this case, a substrate that has high transparency to visible light may be selected as the substrate 310.

By applying one of the configuration examples described above to a display device, it may be possible to realize a display device with high resolution and high definition. Specifically, for example, it may be possible to realize a display device with a resolution of HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). Also, specifically, it may be possible to realize a display device with a resolution of, for example, 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 6000 ppi or more.

Note that this embodiment can be combined as appropriate with the same or other embodiments shown in this specification. For example, the configuration, structure, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, structure, method, etc. shown in the present embodiment. Also, for example, the configuration, structure, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, structure, method, etc. shown in other embodiments.

This embodiment and the corresponding drawings, etc. can be implemented by appropriately combining at least a part of them with other embodiments or examples described in this specification. In addition, the multiple configurations shown in this embodiment and the corresponding drawings, etc. can be appropriately combined with each other.

(Embodiment 5)
In this embodiment, an electronic device and a display device according to one embodiment of the present invention will be described. The one embodiment of the present invention can be suitably used for a wearable electronic device for VR or AR use, for example.

<Example of configuration of electronic device>
Fig. 26A is a perspective view of a glasses-type electronic device 150 as an example of a wearable electronic device. In the electronic device 150 shown in Fig. 26A, a pair of display devices 90 (a display device 90_L and a display device 90_R), a motion detection unit 101, a gaze detection unit 84, a calculation unit 103, and a communication unit 85 are provided in a housing 105.

Figure 26 (B) is a block diagram of the electronic device 150 of Figure 26 (A). As in Figure 26 (A), the electronic device 150 has a display device 90_L, a display device 90_R, a motion detection unit 101, a gaze detection unit 84, a calculation unit 103, and a communication unit 85, and transmits and receives various signals to and from each other via the bus wiring BW. The display device 90_L and the display device 90_R each have a plurality of pixels 230, a drive circuit 65, and a function circuit 40. One pixel 230 includes one light-emitting device 61 and one pixel circuit 51. Thus, the display device 90_L and the display device 90_R each include a plurality of light-emitting devices 61 and a plurality of pixel circuits 51.

The motion detection unit 101 has a function of detecting the motion of the housing 105, i.e., the motion of the head of the user wearing the electronic device 150. For example, a motion sensor using MEMS technology can be used for the motion detection unit 101. As the motion sensor, a three-axis motion sensor or a six-axis motion sensor can be used. Information regarding the motion of the housing 105 detected by the motion detection unit 101 may be referred to as first information or motion information.

The gaze detection unit 84 has a function of acquiring information about the user's gaze. Specifically, it has a function of detecting the user's gaze. The user's gaze may be acquired, for example, by an eye tracking method such as the Pupil Center Corneal Reflection method or the Bright/Dark Pupil Effect method. Alternatively, it may be acquired by an eye tracking method using a laser or ultrasound.

The calculation unit 103 has a function of calculating the user's gaze point using the gaze detection result in the gaze detection unit 84. That is, it is possible to know which object the user is gazing at in the images displayed on the display device 90_L and the display device 90_R. It is also possible to know whether the user is gazing at a part other than the screen. Note that the information regarding the user's gaze obtained by the gaze detection unit 84 (gaze detection result) may be referred to as second information, gaze information, etc.

The calculation unit 103 has a function of performing drawing processing (calculation processing of image data) according to the movement of the housing 105. The drawing processing according to the movement of the housing 105 in the calculation unit 103 is performed using the first information and image data input from the outside via the communication unit 85. For example, 360-degree omnidirectional image data can be used as the image data. The 360-degree omnidirectional image data may be, for example, image data captured by an omnidirectional camera (omnidirectional camera, 360-degree camera), or may be image data generated by computer graphics or the like. The calculation unit 103 has a function of converting the 360-degree omnidirectional image data into image data that can be displayed on the display device 90_L and the display device 90_R according to the first information.

The calculation unit 103 has a function of using the second information to determine the size and shape of multiple areas to be set on the display unit of each of the display devices 90_L and 90_R. Specifically, the calculation unit 103 calculates a gaze point on the display unit according to the second information, and sets a first area S1 to a third area S3, etc., described below, on the display unit based on the gaze point.

As the calculation unit 103, in addition to a central processing unit (CPU), other microprocessors such as a DSP (Digital Signal Processor) and a GPU (Graphics Processing Unit) can be used alone or in combination. Furthermore, these microprocessors may be realized by a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array).

The calculation unit 103 performs various data processing and program control by interpreting and executing commands from various programs using the processor. The programs that can be executed by the processor may be stored in a memory area of the processor, or may be stored in a separately provided storage unit. As the storage unit, for example, a storage device using a non-volatile storage element such as a flash memory, MRAM (Magnetoresistive Random Access Memory), PRAM (Phase change RAM), ReRAM (Resistive RAM), or FeRAM (Ferroelectric RAM), or a storage device using a volatile storage element such as a DRAM (Dynamic RAM) or SRAM (Static RAM), may be used.

The communication unit 85 has a function of communicating with external devices wirelessly or via wires to acquire various data such as image data. The communication unit 85 may, for example, be provided with a high-frequency circuit (RF circuit) and transmit and receive RF signals. The high-frequency circuit is a circuit that converts between electromagnetic signals and electrical signals in a frequency band determined by the legislation of each country, and uses the electromagnetic signals to wirelessly communicate with other communication devices. When performing wireless communication, communication standards such as LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000), and WCDMA (Wideband Code Division Multiple Access: registered trademark), or IEEE communication standardized specifications such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and ZigBee (registered trademark), can be used as communication protocols or communication technologies. Additionally, the third generation mobile communication system (3G), fourth generation mobile communication system (4G), or fifth generation mobile communication system (5G) defined by the International Telecommunications Union (ITU) can also be used.

The communication unit 85 may have external ports such as a terminal for connecting to a LAN (Local Area Network), a terminal for receiving digital broadcasts, and a terminal for connecting an AC adapter.

The display device 90_L and the display device 90_R each have a plurality of light-emitting devices 61, a plurality of pixel circuits 51, a drive circuit 65, and a functional circuit 40. The pixel circuit 51 has a function of controlling the light emission of the light-emitting devices 61. The drive circuit 65 has a function of controlling the pixel circuit 51.

The information on the multiple regions in the display unit of the display device determined by the calculation unit 103 is used for driving the display unit to have different resolutions for each region. The functional circuit 40 has a function of controlling the drive circuit 65 to perform a high-resolution display in a region close to the gaze point, and to control the drive circuit 65 to perform a low-resolution display in a region far from the gaze point.

For example, a low-resolution display can be achieved by rewriting image data every other pixel or every few pixels. Reducing the number of pixels for which image data is rewritten can reduce the power consumption of the display device.

The electronic device 150 may be provided with a sensor 97. The sensor 97 may have a function of acquiring one or more of the user's visual, auditory, tactile, taste, and olfactory information. More specifically, the sensor 97 may have a function of detecting or measuring one or more of the following information: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, magnetism, temperature, sound, time, electric field, current, voltage, power, radiation, humidity, gradient, vibration, odor, and infrared. The electronic device 150 may be provided with one or more sensors 97.

The sensor 97 may be used to measure the surrounding temperature, humidity, illuminance, odor, etc. The sensor 97 may also be used to obtain information for personal authentication using, for example, a fingerprint, palm print, iris, retina, pulse shape (including vein shape and artery shape), or face. The sensor 97 may also be used to measure the number of times the user blinks, eyelid behavior, pupil size, body temperature, pulse rate, or oxygen saturation in the blood, and detect the user's fatigue level and health condition, etc. The electronic device 150 may detect the user's fatigue level and health condition, etc., and display a warning, etc. on the display device 90.

The operation of the electronic device 150 may be controlled by detecting the movement of the user's line of sight and eyelids. Since the user does not need to touch the electronic device 150 to operate it, input operations can be performed without holding anything in both hands (both hands are free).

Fig. 27(A) is a perspective view showing an electronic device 150. In Fig. 27(A), the housing 105 of the electronic device 150 has, in addition to a pair of display devices 90_L, a display device 90_R, and a calculation unit 103, as one example, a mounting unit 86, a cushioning member 87, a pair of lenses 88, etc. The pair of display devices 90_L and 90_R are each provided in a position inside the housing 105 where they can be viewed through the lens 88.

The housing 105 shown in FIG. 27(A) is provided with an input terminal 98 and an output terminal 89. The input terminal 98 can be connected to a cable that supplies an image signal (image data) from a video output device or the like, or power for charging a battery (not shown) provided within the housing 105. The output terminal 89 functions as, for example, an audio output terminal, and can be connected to earphones, headphones, etc.

It is preferable that the housing 105 has a mechanism that can adjust the left-right positions of the lens 88 and the display devices 90_L and 90_R so that they are optimally positioned according to the position of the user's eyes. It is also preferable that the housing 105 has a mechanism that can adjust the focus by changing the distance between the lens 88 and the display devices 90_L and 90_R.

The cushioning member 87 is the part that comes into contact with the user's face (forehead, cheeks, etc.). The cushioning member 87 comes into close contact with the user's face, preventing the intrusion of external light (light leakage), and enhancing the sense of immersion. It is preferable that the cushioning member 87 is made of a soft material so that it comes into close contact with the user's face when the user wears the electronic device 150. Using such a material is preferable because it feels good on the skin and does not make the user feel cold when worn in cold seasons, etc. It is preferable that the members that come into contact with the user's skin, such as the cushioning member 87 or the attachment part 86, are removable, as this makes cleaning or replacement easier.

The electronic device of one aspect of the present invention may further include an earphone 99A. The earphone 99A has a communication unit (not shown) and has a wireless communication function. The earphone 99A can output audio data using the wireless communication function. The earphone 99A may have a vibration mechanism that functions as a bone conduction earphone.

The earphone 99A can be configured to be connected directly or by wire to the mounting portion 86, like the earphone 99B shown in FIG. 27(B). The earphone 99B and the mounting portion 86 may also have a magnet. This allows the earphone 99B to be fixed to the mounting portion 86 by magnetic force, which is preferable as it makes storage easier.

<Example of the configuration of the display device>
The configuration of a display device 90A that can be applied to the display device 90_L and the display device 90_R shown in FIGS. 26A and 26B will be described with reference to FIGS. 28A, 28B, and 29. FIG.

Figure 28 (A) is a perspective view of a display device 90A that can be used with the display devices 90_L and 90_R shown in Figures 26 (A) and 26 (B).

The display device 90A has a substrate 91 and a substrate 92. The display device 90A has a display section 93 provided between the substrate 91 and the substrate 92. The display section 93 has a plurality of pixels 230. The pixels 230 have a pixel circuit 51 and a light-emitting device 61. The display section 93 is an area in the display device 90A that displays an image.

When the pixels 230 are arranged in a matrix of 1920 x 1080 pixels, a display unit 93 capable of displaying at a resolution of so-called full high vision (also called "2K resolution", "2K1K", or "2K"). Also, for example, when the pixels 230 are arranged in a matrix of 3840 x 2160 pixels, a display unit 93 capable of displaying at a resolution of so-called ultra high vision (also called "4K resolution", "4K2K", or "4K"). Also, for example, when the pixels 230 are arranged in a matrix of 7680 x 4320 pixels, a display unit 93 capable of displaying at a resolution of so-called super high vision (also called "8K resolution", "8K4K", or "8K"). By increasing the number of pixels 230, it is also possible to realize a display unit 93 capable of displaying at a resolution of 16K or even 32K.

The pixel density (resolution) of the display unit 93 is preferably 1000 ppi or more and 10000 ppi or less. For example, it may be 2000 ppi or more and 6000 ppi or less, or 3000 ppi or more and 5000 ppi or less.

There is no particular limitation on the screen ratio (aspect ratio) of the display unit 93. The display unit 93 can support various screen ratios, such as 1:1 (square), 4:3, 16:9, and 16:10.

In this specification and the like, the term "element" may be alternatively referred to as "device." For example, a display element, a light-emitting device, and a liquid crystal element may be alternatively referred to as a display device, a light-emitting device, and a liquid crystal device, respectively.

The display device 90A receives various signals and power supply potentials from the outside via the terminal section 94, and can display images using the display elements provided in the display section 93. Various elements can be used as the display elements. Representative examples include light-emitting devices that have the function of emitting light, such as organic EL elements and LED elements, liquid crystal elements, and MEMS (Micro Electro Mechanical Systems) elements.

Between the substrate 91 and the substrate 92, multiple layers are provided, and each layer is provided with a transistor for performing circuit operation or a display element for emitting light. In the multiple layers, pixel circuits having the function of controlling the operation of the display elements, drive circuits having the function of controlling the pixel circuits, functional circuits having the function of controlling the drive circuits, etc. are provided.

Figure 28 (B) shows a perspective view that illustrates the configuration of each layer provided between substrate 91 and substrate 92.

A layer 62 is provided on the substrate 91. The layer 62 has a driver circuit 65, a functional circuit 40, and an input/output circuit 80. The layer 62 has a transistor 63 (also called a Si transistor) having silicon in a channel formation region 64. For example, a silicon substrate can be used for the substrate 91. A silicon substrate is preferable because it has higher thermal conductivity than a glass substrate. By providing the driver circuit 65, the functional circuit 40, and the input/output circuit 80 in the same layer, the wiring that electrically connects the driver circuit 65, the functional circuit 40, and the input/output circuit 80 can be shortened. Therefore, the charge and discharge time of the control signal for the functional circuit 40 to control the driver circuit 65 is shortened, and power consumption can be reduced. In addition, the charge and discharge time for the input/output circuit 80 to supply a signal to the functional circuit 40 and the driver circuit 65 is shortened, and power consumption can be reduced.

The transistor 63 can be, for example, a transistor having single crystal silicon in the channel formation region (also called a "c-Si transistor"). In particular, when a transistor having single crystal silicon in the channel formation region is used as the transistor provided in the layer 62, the on-current of the transistor can be increased. Therefore, it is preferable because the circuit of the layer 62 can be driven at high speed. In addition, since a Si transistor can be formed by microfabrication with a channel length of 3 nm to 10 nm, it can be a display device 90A in which a CPU, an accelerator such as a GPU, an application processor, etc. are integrally provided with the display unit.

A transistor having polycrystalline silicon in a channel formation region (also called a "Poly-Si transistor") may be provided in layer 62. LTPS may be used as the polycrystalline silicon. Note that a transistor having LTPS in a channel formation region is also called an "LTPS transistor." In addition, an OS transistor may be provided in layer 62 as necessary.

As the driving circuit 65, various circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, and a logic circuit can be used. The driving circuit 65 has, for example, a gate driver circuit, a source driver circuit, and the like. In addition, it may have an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Since it is possible to arrange the gate driver circuit, the source driver circuit, and other circuits on top of the display unit 93, the width of the non-display area (also called a frame) existing on the periphery of the display unit 93 of the display device 90A can be made extremely narrow compared to the case where these circuits and the display unit 93 are arranged side by side, and the display device 90A can be made smaller.

The functional circuit 40 has, for example, the function of an application processor for controlling each circuit in the display device 90A and generating signals for controlling each circuit. The functional circuit 40 may also have a circuit for correcting image data such as an accelerator such as a CPU or a GPU. The functional circuit 40 may also have an LVDS (Low Voltage Differential Signaling) circuit having a function as an interface for receiving image data from outside the display device 90A, a MIPI (Mobile Industry Processor Interface) circuit, and a D/A (Digital to Analog) conversion circuit. The functional circuit 40 may also have a circuit for compressing and expanding image data, a power supply circuit, etc.

A layer 83 is provided on the layer 62. The layer 83 has a pixel circuit group 55 including a plurality of pixel circuits 51. An OS transistor may be provided in the layer 83. The pixel circuit 51 may be configured to include an OS transistor. Note that the layer 83 can be stacked on the layer 62.

A Si transistor may be provided in layer 83. For example, pixel circuit 51 may be configured to include a transistor having single crystal silicon or polycrystalline silicon in the channel formation region. LTPS may be used as the polycrystalline silicon. For example, layer 83 may be formed on a separate substrate and bonded to layer 62.

For example, the pixel circuit 51 may be composed of multiple types of transistors using different semiconductor materials. When the pixel circuit 51 is composed of multiple types of transistors using different semiconductor materials, the transistors may be provided in different layers for each type of transistor. For example, when the pixel circuit 51 is composed of Si transistors and OS transistors, the Si transistors and the OS transistors may be provided in a stacked manner. By providing the transistors in a stacked manner, the area occupied by the pixel circuit 51 is reduced. This can improve the resolution of the display device 90A. Note that a configuration in which LTPS transistors and OS transistors are combined may be referred to as LTPO.

As the transistor 52, which is an OS transistor, it is preferable to use a transistor having an oxide containing at least one of indium, element M (element M is aluminum, gallium, yttrium, or tin), and zinc in the channel formation region 54. Such an OS transistor has a characteristic of having a very low off-state current. Therefore, it is particularly preferable to use an OS transistor as a transistor provided in a pixel circuit, because analog data written to the pixel circuit can be retained for a long period of time.

A layer 81 is provided on the layer 83. A substrate 92 is provided on the layer 81. The substrate 92 is preferably a substrate having translucency or a layer made of a material having translucency. A plurality of light-emitting devices 61 are provided on the layer 81. The layer 81 can be configured to be stacked on the layer 83. For example, an organic electroluminescence element (also called an organic EL element) can be used as the light-emitting device 61. However, the light-emitting device 61 is not limited to this, and for example, an inorganic EL element made of an inorganic material can be used. Note that the "organic EL element" and the "inorganic EL element" may be collectively called the "EL element". The light-emitting device 61 may have an inorganic compound such as a quantum dot. For example, quantum dots can be used in the light-emitting layer to function as a light-emitting material.

As shown in FIG. 28B, the display device 90A of one embodiment of the present invention can have a stacked structure of the light-emitting device 61, the pixel circuit 51, the driver circuit 65, and the functional circuit 40, and therefore the aperture ratio (effective display area ratio) of the pixel can be extremely high. For example, the aperture ratio of the pixel can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. In addition, the pixel circuits 51 can be arranged at an extremely high density, and the resolution of the pixel can be extremely high. For example, in the display portion 93 of the display device 90A (the region where the pixel circuit 51 and the light-emitting device 61 are stacked), the pixels can be arranged with a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20000 ppi or less, or 30000 ppi or less.

Since such a display device 90A has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration in which the display unit of the display device 90A is viewed through an optical component such as a lens, the display device 90A has an extremely high-resolution display unit, so that even if the display unit is enlarged with a lens, the pixels are not visible, and a highly immersive display can be achieved.

When the display device 90A is used as a wearable VR or AR display device, the diagonal size of the display unit 93 can be 0.1 inches or more and 5.0 inches or less, preferably 0.5 inches or more and 2.0 inches or less, and more preferably 1 inch or more and 1.7 inches or less. For example, the diagonal size of the display unit 93 may be 1.5 inches or close to 1.5 inches. By making the diagonal size of the display unit 93 2.0 inches or less, it becomes possible to process the display unit 93 in a single exposure process using an exposure device (typically, a scanner device), thereby improving the productivity of the manufacturing process.

The display device 90A according to one embodiment of the present invention can be applied to devices other than wearable electronic devices. In this case, the diagonal size of the display unit 93 may exceed 2.0 inches. The configuration of the transistors used in the pixel circuit 51 may be appropriately selected according to the diagonal size of the display unit 93. For example, when a single crystal Si transistor is used in the pixel circuit 51, the diagonal size of the display unit 93 is preferably 0.1 inches or more and 3 inches or less. When an LTPS transistor is used in the pixel circuit 51, the diagonal size of the display unit 93 is preferably 0.1 inches or more and 30 inches or less, and more preferably 1 inch or more and 30 inches or less. When an LTPO (a configuration in which an LTPS transistor and an OS transistor are combined) is used in the pixel circuit 51, the diagonal size of the display unit 93 is preferably 0.1 inches or more and 50 inches or less, and more preferably 1 inch or more and 50 inches or less. Furthermore, when an OS transistor is used in the pixel circuit 51, the diagonal size of the display section 93 is preferably 0.1 inches or more and 200 inches or less, and more preferably 50 inches or more and 100 inches or less.

It is very difficult to increase the size of a display device using single crystal Si transistors in the pixel circuit 51, etc., due to the size of the single crystal Si substrate. In addition, it is difficult to accommodate large displays (typically screen sizes exceeding 30 inches in diagonal size) when using LTPS transistors in the pixel circuit 51, etc., because a laser crystallization device is used in the manufacturing process. On the other hand, OS transistors are not restricted by the use of a laser crystallization device in the manufacturing process, or can be manufactured at a relatively low process temperature (typically 450°C or lower), so they can accommodate display devices with a relatively large area (typically 50 inches or more and 100 inches or less in diagonal size). In addition, LTPO can be applied to the diagonal size of the display part in the area between when LTPS transistors are used and when OS transistors are used (typically 1 inch or more and 50 inches or less).

A specific example of the configuration of the drive circuit 65 and the functional circuit 40 will be described with reference to FIG. 29. FIG. 29 is a block diagram showing the configuration of the display device 90A, and shows multiple wirings connecting the pixel circuits 51, the drive circuit 65, and the functional circuit 40, as well as bus wirings within the display device 90A.

In the display device 90A shown in FIG. 29, a plurality of pixel circuits 51 are arranged in a matrix on the layer 83.

In the display device 90A shown in FIG. 29, a driving circuit 65, a functional circuit 40, and an input/output circuit 80 are arranged in the layer 62. The driving circuit 65 has, as an example, a source driver circuit 66, a digital-to-analog converter (DAC) 67, a gate driver circuit 33, a level shifter 34, an amplifier circuit 35, an inspection circuit 36, an image generation circuit 37, and an image distribution circuit 38. The functional circuit 40 has, as an example, a storage device 41, a GPU 42, an EL correction circuit 43, a timing controller 44, a CPU 45, a sensor controller 46, a power supply circuit 47, a temperature sensor 48, and a brightness correction circuit 49. The functional circuit 40 has the function of an application processor. Note that a GPU that performs calculations for artificial intelligence may be called an AI accelerator.

The input/output circuit 80 supports transmission methods such as LVDS (Low Voltage Differential Signaling), and has a function of distributing control signals and image data input via a terminal unit 94 to a drive circuit 65 and a function circuit 40. The input/output circuit 80 also has a function of outputting information from the display device 90A to the outside via the terminal unit 94.

The display device 90A in FIG. 29 illustrates a configuration in which the circuits included in the drive circuit 65, the circuits included in the functional circuit 40, and the input/output circuit 80 are each electrically connected to the bus wiring BSL.

As an example, the source driver circuit 66 has a function of transmitting image data to the pixel circuit 51 of the pixel 230. Therefore, the source driver circuit 66 is electrically connected to the pixel circuit 51 via the wiring SL. Note that multiple source driver circuits 66 may be provided.

The digital-to-analog conversion circuit 67 has a function of converting image data that has been digitally processed by a GPU, a correction circuit, etc., described below, into analog data. The image data converted into analog data is amplified by an amplifier circuit 35 such as an operational amplifier, and transmitted to the pixel circuit 51 via the source driver circuit 66. Note that the image data may be transmitted in the order of the source driver circuit 66, the digital-to-analog conversion circuit 67, and the pixel circuit 51. The digital-to-analog conversion circuit 67 and the amplifier circuit 35 may be included in the source driver circuit 66.

As an example, the gate driver circuit 33 has a function of selecting a pixel circuit in the pixel circuit 51 to which image data is to be sent. Therefore, the gate driver circuit 33 is electrically connected to the pixel circuit 51 via the wiring GL. Note that multiple gate driver circuits 33 may be provided in correspondence with the source driver circuits 66.

The level shifter 34 has the function of converting signals input to the source driver circuit 66, the digital-to-analog conversion circuit 67, the gate driver circuit 33, etc., to an appropriate level, for example.

As an example, the memory device 41 has a function of storing image data to be displayed in the pixel circuit 51. The memory device 41 can be configured to store image data as digital data or analog data.

When storing image data in the storage device 41, it is preferable that the storage device 41 is a non-volatile memory. In this case, for example, a NAND type memory can be used for the storage device 41.

When temporary data generated by the GPU 42, the EL correction circuit 43, the CPU 45, etc. is stored in the storage device 41, it is preferable that the storage device 41 is a volatile memory. In this case, for example, SRAM, DRAM, etc. can be used for the storage device 41.

As an example, the GPU 42 has a function of performing processing to output image data read from the storage device 41 to the pixel circuit 51. In particular, the GPU 42 is configured to perform pipeline processing in parallel, so that the image data to be output to the pixel circuit 51 can be processed at high speed. The GPU 42 can also function as a decoder for restoring an encoded image.

The functional circuit 40 may include a plurality of circuits capable of improving the display quality of the display device 90A. For example, such a circuit may include a correction circuit (color adjustment, dimming) that detects color unevenness in the displayed image and corrects the color unevenness to produce an optimal image. For example, when a light-emitting device using an organic EL is applied to the display element, the functional circuit 40 may include an EL correction circuit that corrects image data according to the characteristics of the light-emitting device. As an example, the functional circuit 40 includes an EL correction circuit 43.

Artificial intelligence may be used for the image correction described above. For example, the current flowing through the pixel circuit (or the voltage applied to the pixel circuit) may be monitored and acquired, and the displayed image may be acquired by an image sensor or the like, and the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (e.g., an artificial neural network, etc.), and the output result may be used to determine whether or not the image needs to be corrected.

Artificial intelligence calculations can be applied not only to image correction, but also to up-conversion processing that increases the resolution of image data. As an example, the GPU 42 in FIG. 29 illustrates blocks for performing various correction calculations (color unevenness correction 42a, up-conversion 42b, etc.).

The algorithm for up-converting image data can be selected from the Nearest Neighbor method, Bilinear method, Bicubic method, RAISR (Rapid and Accurate Image Super-Resolution) method, ANR (Anchored Neighborhood Regression) method, A+ method, SRCNN (Super-Resolution Convolutional Neural Network) method, etc.

The upconversion process may be configured to change the algorithm used for the upconversion process for each area determined according to the gaze point. For example, the upconversion process for the gaze point and the area near the gaze point may be performed using an algorithm that has a slow processing speed but high accuracy, and the upconversion process for areas other than the gaze point may be performed using an algorithm that has a fast processing speed but low accuracy. With this configuration, the time required for the upconversion process can be shortened. Also, the power consumption required for the upconversion process can be reduced.

In addition to up-conversion processing, down-conversion processing may be performed to reduce the resolution of image data. If the resolution of the image data is greater than the resolution of the display unit 93, a portion of the image data may not be displayed on the display unit 93. In such a case, down-conversion processing can be performed to display the entire image data on the display unit 93.

As an example, the timing controller 44 has a function of controlling the drive frequency (frame frequency, frame rate, refresh rate, etc.) at which an image is displayed. For example, when a still image is displayed on the display device 90A, the drive frequency can be lowered by the timing controller 44, thereby reducing the power consumption of the display device 90A.

The CPU 45 has a function to perform general-purpose processing such as, for example, running an operating system, controlling data, performing various calculations, and running programs. The CPU 45 has a role to execute commands such as writing or reading image data in the storage device 41, correcting image data, and operating a sensor, which will be described later. In addition, for example, the CPU 45 may have a function to send a control signal to at least one of the circuits included in the functional circuit 40.

As an example, the sensor controller 46 has a function of controlling the sensor. Also, in FIG. 29, wiring SNCL is illustrated as wiring for electrically connecting to the sensor.

The sensor may be, for example, a touch sensor that may be provided on the display unit. Alternatively, the sensor may be, for example, an illuminance sensor.

The power supply circuit 47 has a function of generating a voltage to be supplied to the pixel circuits 51, the drive circuit 65, and the circuits included in the functional circuit 40, for example. The power supply circuit 47 may also have a function of selecting the circuit to which the voltage is to be supplied. For example, the power supply circuit 47 can reduce the power consumption of the entire display device 90A by stopping the supply of voltage to the CPU 45, the GPU 42, etc. during the period when a still image is being displayed.

As described above, the display device according to one embodiment of the present invention can have a stacked structure of a display element, a pixel circuit, a driver circuit, and a functional circuit 40. The driver circuit and the functional circuit, which are peripheral circuits, can be arranged to overlap with the pixel circuit, and the width of the frame can be made extremely narrow, so that the display device can be made compact. In addition, the display device according to one embodiment of the present invention can be made lightweight because the wiring connecting the circuits can be shortened by stacking the circuits. In addition, the display device according to one embodiment of the present invention can have a display portion with improved pixel resolution, so that the display device has excellent display quality.

<Example of display module configuration>
Next, a configuration example of a display module including the display device 90A will be described.

Figures 30(A) to 30(C) are perspective views of a display module 500. The display module 500 has a structure in which an FPC 504 is provided on the terminal portion 94 of the display device 90A. The FPC 504 has a structure in which wiring is provided on a film made of an insulating material. The FPC 504 is flexible. The FPC 504 functions as wiring for supplying video signals, control signals, power supply potential, and the like from the outside to the display device 90A. An IC may also be mounted on the FPC 504.

The display module 500 shown in FIG. 30(B) has a configuration in which a display device 90A is provided on a printed wiring board 501. The printed wiring board 501 has a structure in which wiring is provided inside or on the surface, or inside and on the surface, of a substrate made of an insulating material.

In the display module 500 shown in FIG. 30(B), the terminal portion 94 of the display device 90A and the terminal portion 502 of the printed wiring board 501 are electrically connected via a wire 503. The wire 503 can be formed by wire bonding. Also, ball bonding or wedge bonding can be used as the wire bonding.

After the wire 503 is formed, the wire 503 may be covered with a resin material or the like. The electrical connection between the display device 90A and the printed wiring board 501 may be achieved by a method other than wire bonding. For example, the electrical connection between the display device 90A and the printed wiring board 501 may be achieved by an anisotropic conductive adhesive or bumps.

30B, the terminal portion 502 of the printed wiring board 501 is electrically connected to the FPC 504. For example, when the pitch of the electrodes of the terminal portion 94 of the display device 90A is different from the pitch of the electrodes of the FPC 504, the terminal portion 94 and the FPC 504 may be electrically connected via the printed wiring board 501. Specifically, the spacing (pitch) of the multiple electrodes of the terminal portion 94 can be converted to the spacing of the multiple electrodes of the terminal portion 502 by using wiring formed on the printed wiring board 501. That is, even when the pitch of the electrodes of the terminal portion 94 is different from the pitch of the electrodes of the FPC 504, the electrical connection of the electrodes of both can be realized.

The printed wiring board 501 can be provided with various elements such as resistor elements, capacitor elements, and semiconductor elements.

As in the display module 500 shown in FIG. 30(C), the terminal portion 502 may be electrically connected to a connection portion 505 provided on the underside of the printed wiring board 501 (the side on which the display device 90A is not provided). For example, by making the connection portion 505 a socket-type connection portion, the display module 500 can be easily attached to and detached from other devices.

<Example of pixel circuit configuration>
31A and 31B show a configuration example of a pixel circuit 51 and a light-emitting device 61 connected to the pixel circuit 51. Fig. 31A is a diagram showing the connections of the various elements, and Fig. 31B is a diagram showing a schematic hierarchical relationship between a layer 62 including a driver circuit, a layer 83 including a plurality of transistors included in the pixel circuit, and a layer 81 including a light-emitting device.

The pixel circuit 51 shown as an example in FIG. 31(A) and FIG. 31(B) includes a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The transistors 52A, 52B, and 52C can be OS transistors. Each of the OS transistors 52A, 52B, and 52C preferably includes a backgate electrode. In this case, the backgate electrode can be configured to receive the same signal as the gate electrode, or the backgate electrode can be configured to receive a signal different from the gate electrode.

Transistor 52B has a gate electrode electrically connected to transistor 52A, a first electrode electrically connected to light-emitting device 61, and a second electrode electrically connected to wiring ANO. Wiring ANO is a wiring for providing a potential for supplying a current to light-emitting device 61.

Transistor 52A has a first terminal electrically connected to the gate electrode of transistor 52B, a second terminal electrically connected to the wiring SL that functions as a source line, and a gate electrode that has the function of controlling the conductive state or non-conductive state based on the potential of the wiring GL1 that functions as a gate line.

Transistor 52C has a first terminal electrically connected to wiring V0, a second terminal electrically connected to light-emitting device 61, and a gate electrode that has a function of controlling a conductive state or a non-conductive state based on the potential of wiring GL2 that functions as a gate line. Wiring V0 is a wiring for providing a reference potential and a wiring for outputting a current flowing through pixel circuit 51 to drive circuit 65 or function circuit 40.

The capacitive element 53 includes a conductive film electrically connected to the gate electrode of the transistor 52B and a conductive film electrically connected to the second electrode of the transistor 52B.

The light-emitting device 61 has a first electrode electrically connected to the first electrode of the transistor 52B and a second electrode electrically connected to the wiring VCOM. The wiring VCOM is a wiring for providing a potential for supplying a current to the light-emitting device 61.

This allows the intensity of the light emitted by the light-emitting device 61 to be controlled according to the image signal applied to the gate electrode of transistor 52B. In addition, the reference potential of wiring V0 applied via transistor 52C can suppress variations in the gate-source voltage of transistor 52B.

A current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting device 61 to the outside. The current output to the wiring V0 is converted to a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted to a digital signal by an A-D converter or the like and output to the functional circuit 40, etc.

The light-emitting device described in one embodiment of the present invention is a self-luminous display element such as an organic electroluminescent element (also called an OLED). The light-emitting device electrically connected to the pixel circuit can be a self-luminous light-emitting device such as an LED, a micro LED, a QLED, or a semiconductor laser.

In the configuration shown as an example in FIG. 31B, the wiring electrically connecting the pixel circuit 51 and the drive circuit 65 can be shortened, so that the wiring resistance of the wiring can be reduced. Therefore, data can be written at high speed, so that the display device 90A can be driven at high speed. As a result, even if the display device 90A has a large number of pixel circuits 51, a sufficient frame period can be secured, so that the pixel density of the display device 90A can be increased. In addition, by increasing the pixel density of the display device 90A, the resolution of the image displayed by the display device 90A can be increased. For example, the pixel density of the display device 90A can be 1000 ppi or more, or 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 90A can be, for example, a display device for AR or VR, and can be suitably applied to electronic devices such as HMDs in which the display unit is close to the user.

Note that although the pixel circuit 51 having a total of three transistors is shown as an example in FIG. 31(A) and FIG. 31(B), one embodiment of the present invention is not limited to this. Below, a configuration example and a driving method example of a pixel circuit that can be applied to the pixel circuit 51 will be described.

The pixel circuit 51A shown in FIG. 32(A) includes a transistor 52A, a transistor 52B, and a capacitor 53. FIG. 32(A) also illustrates a light-emitting device 61 connected to the pixel circuit 51A. The pixel circuit 51A is electrically connected to wiring SL, wiring GL, wiring ANO, and wiring VCOM. The pixel circuit 51A has a configuration in which the transistor 52C is removed from the pixel circuit 51 shown in FIG. 31(A) and wiring GL1 and wiring GL2 are replaced with wiring GL.

The gate of the transistor 52A is electrically connected to the wiring GL, one of the source or drain is electrically connected to the wiring SL, and the other is electrically connected to the gate of the transistor 52B and one electrode of the capacitor C1. The source or drain of the transistor 52B is electrically connected to the wiring ANO, and the other is electrically connected to the anode of the light-emitting device 61. The other electrode of the capacitor C1 is electrically connected to the anode of the light-emitting device 61. The cathode of the light-emitting device 61 is electrically connected to the wiring VCOM.

The pixel circuit 51B shown in FIG. 32(B) has a configuration in which a transistor 52C is added to the pixel circuit 51A. In addition, the pixel circuit 51B is electrically connected to the wiring V0.

Pixel circuit 51C shown in FIG. 32(C) is an example in which a transistor with a pair of gates electrically connected is applied to transistor 52A and transistor 52B of pixel circuit 51A. Pixel circuit 51D shown in FIG. 32(D) is an example in which the same transistor is applied to pixel circuit 51B. This can increase the current that the transistor can pass. Note that, although transistors with a pair of gates electrically connected are applied to all transistors here, this is not limited to this. Also, transistors having a pair of gates that are electrically connected to different wirings may be applied. For example, reliability can be improved by using a transistor in which one of the gates is electrically connected to a source.

The pixel circuit 51E shown in FIG. 33A has a configuration in which a transistor 52D is added to the above-mentioned 51B. The pixel circuit 51E is electrically connected to wirings GL1, GL2, and GL3 that function as gate lines. Note that in this embodiment and the like, the wirings GL1, GL2, and GL3 may be collectively referred to as wirings GL. Therefore, the number of wirings GL is not limited to one, and may be multiple.

The gate of transistor 52D is electrically connected to wiring GL3, one of the source and drain is electrically connected to the gate of transistor 52B, and the other is electrically connected to wiring V0. The gate of transistor 52A is electrically connected to wiring GL1, and the gate of transistor 52C is electrically connected to wiring GL2.

By simultaneously turning on transistors 52C and 52D, the source and gate of transistor 52B are at the same potential, and transistor 52B can be turned off. This makes it possible to forcibly cut off the current flowing through light-emitting device 61. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternated.

The pixel circuit 51F shown in FIG. 33(B) is an example in which a capacitive element 53A is added to the pixel circuit 51E. The capacitive element 53A functions as a storage capacitor.

Pixel circuit 51G shown in FIG. 33(C) and pixel circuit 51H shown in FIG. 33(D) are examples in which a transistor having a pair of gates is applied to pixel circuit 51E or pixel circuit 51F, respectively. Transistors 52A, 52C, and 52D are transistors in which a pair of gates are electrically connected, and transistor 52B is a transistor in which one gate is electrically connected to a source.

<Modification 1>
34A and 34B are perspective views of a display device 90B, which is a modified example of the display device 90A. Fig. 34B is a perspective view for explaining the configuration of each layer of the display device 90B. In order to reduce repetition of explanation, differences from the display device 90A will be mainly explained.

The display device 90B has a pixel circuit group 55 including a plurality of pixel circuits 51 and a drive circuit 65 stacked on top of each other. In the display device 90B, the pixel circuit group 55 is divided into a plurality of sections 59, and the drive circuit 65 is divided into a plurality of sections 39. Each of the plurality of sections 39 has a source driver circuit 66 and a gate driver circuit 33.

35(A) shows a configuration example of the pixel circuit group 55 of the display device 90B. FIG. 35(B) shows a configuration example of the drive circuit 65 of the display device 90B. The partitions 59 and 39 are arranged in a matrix of m rows and n columns (m and n are integers of 1 or more). In this specification, the partition 59 in the first row and first column is indicated as partition 59[1,1], and the partition 59 in the mth row and nth column is indicated as partition 59[m,n]. Similarly, the partition 39 in the first row and first column is indicated as partition 39[1,1], and the partition 39 in the mth row and nth column is indicated as partition 39[m,n]. FIG. 35(A) and FIG. 35(B) show a case where m is 4 and n is 8. That is, the pixel circuit group 55 and the drive circuit 65 are each divided into 32.

Each of the multiple sections 59 has multiple pixel circuits 51, multiple wirings SL, and multiple wirings GL. In each of the multiple sections 59, one of the multiple pixel circuits 51 is electrically connected to at least one of the multiple wirings SL and at least one of the multiple wirings GL.

One of the sections 59 and one of the sections 39 are provided to overlap (see FIG. 35(C)). For example, the section 59[i,j] (i is an integer between 1 and m, and j is an integer between 1 and n) and the section 39[i,j] are provided to overlap. The source driver circuit 66[i,j] of the section 39[i,j] is electrically connected to the wiring SL of the section 59[i,j]. The gate driver circuit 33[i,j] of the section 39[i,j] is electrically connected to the wiring GL of the section 59[i,j]. The source driver circuit 66[i,j] and the gate driver circuit 33[i,j] have the function of controlling the multiple pixel circuits 51 of the section 59[i,j].

By overlapping the sections 59[i,j] and 39[i,j], the connection distance (wiring length) between the pixel circuit 51 in section 59[i,j] and the source driver circuit 66 and gate driver circuit 33 in section 39[i,j] can be made extremely short. As a result, the wiring resistance and parasitic capacitance are reduced, so the time required for charging and discharging is shortened, and high-speed driving can be achieved. In addition, power consumption can be reduced. Also, miniaturization and weight reduction can be achieved.

The display device 90B has a configuration in which each section 39 has a source driver circuit 66 and a gate driver circuit 33. Therefore, the display unit 93 can be divided into sections 59 corresponding to the sections 39, and images can be rewritten. For example, it is possible to rewrite image data only in sections of the display unit 93 where changes have occurred in the image, and to retain image data in sections where no changes have occurred, thereby realizing a reduction in power consumption.

In the present embodiment and the like, one of the display units 93 divided into sections 59 is called a sub-display unit 95. Therefore, the sub-display unit 95 is also one of the display units 93 divided into sections 39. The display unit 93 has multiple sub-display units 95. It can also be said that the display unit 93 is composed of multiple sub-display units 95. In the display device 90B described using Figures 34 (A) to 35 (D), a case is shown in which the display unit 93 is divided into 32 sub-display units 95 (see Figure 34 (A)). The sub-display unit 95 includes multiple pixels 230 shown in Figure 31 and the like. Specifically, one sub-display unit 95 includes one of the sections 59 including multiple pixel circuits 51 and multiple light-emitting devices 61. Also, one section 39 has the function of controlling the multiple pixels 230 included in one sub-display unit 95.

The display device 90B can arbitrarily set the drive frequency for image display for each sub-display unit 95 by using the timing controller 44 of the functional circuit 40. The functional circuit 40 has a function of controlling the operation of each of the multiple sections 39 and the multiple sections 59. In other words, the functional circuit 40 has a function of controlling the drive frequency and operation timing of each of the multiple sub-display units 95 arranged in a matrix. The functional circuit 40 also has a function of adjusting synchronization between the sub-display units.

A timing controller 441 and an input/output circuit 442 may be provided for each partition 39 (see FIG. 35(D)). For example, an I2C (Inter-Integrated Circuit) interface or the like can be used as the input/output circuit 442. In FIG. 35(C) and FIG. 35(D), the timing controller 441 in partition 39[i,j] is shown as timing controller 441[i,j]. Also, the input/output circuit 442 in partition 39[i,j] is shown as input/output circuit 442[i,j].

For example, the functional circuit 40 supplies to the input/output circuit 442[i,j] operation parameters such as setting signals for the scanning direction and drive frequency of the gate driver circuit 33[i,j], and the number of pixels to be thinned out of the image data when reducing the resolution (the number of pixels that are not rewritten when the image data is rewritten). The source driver circuit 66[i,j] and the gate driver circuit 33[i,j] operate according to the operation parameters.

If the sub-display unit 95 has a light-receiving element described below, the input/output circuit 442 outputs information photoelectrically converted by the light-receiving element to the functional circuit 40.

The display device 90B in the electronic device according to one aspect of the present invention has pixel circuits 51 and drive circuits 65 stacked together, and can achieve low power consumption by varying the drive frequency for each sub-display section 95 in response to the movement of the user's line of sight.

Figure 36 (A) shows a display unit 93 having sub-display units 95 arranged in 4 rows and 8 columns. Also shown in Figure 36 (A) are a first region S1 to a third region S3 centered on a gaze point G. The calculation unit 103 assigns each of the multiple sub-display units 95 to either a first region 29A overlapping with the first region S1 or the second region S2, or a second region 29B overlapping with the third region S3. That is, the calculation unit 103 assigns each of the multiple sections 39 to either the first region 29A or the second region 29B. In this case, the first region 29A overlapping with the first region S1 and the second region S2 includes a region overlapping with the gaze point G. Also, the second region 29B includes a sub-display unit 95 located outside the first region 29A. (See Figure 36 (B)).

The operation of the driving circuits (the source driver circuit 66 and the gate driver circuit 33) of each of the multiple sections 39 is controlled by the functional circuit 40. For example, the second area 29B is an area that overlaps with the third area S3, which includes the stable fixation field, the induced field, and the auxiliary field, and is an area where the user's ability to distinguish is low. Therefore, even if the number of times image data is rewritten per unit time (hereinafter also referred to as the "number of times image is rewritten") is less in the second area 29B than in the first area 29A during image display, the actual display quality (hereinafter also referred to as the "actual display quality") perceived by the user is less degraded. In other words, even if the driving frequency (also referred to as the "second driving frequency") of the sub-display unit 95 included in the second area 29B is lower than the driving frequency (also referred to as the "first driving frequency") of the sub-display unit 95 included in the first area 29A, the actual display quality is less degraded.

Lowering the drive frequency can reduce the power consumption of the display device. On the other hand, lowering the drive frequency also reduces the display quality. In particular, the display quality during video display is reduced. According to one aspect of the present invention, by setting the second drive frequency lower than the first drive frequency, it is possible to reduce the power consumption in areas where the user's visibility is low, while suppressing the substantial degradation of the display quality. According to one aspect of the present invention, it is possible to maintain the display quality while reducing the power consumption.

The first drive frequency may be 30 Hz or more and 500 Hz or less, preferably 60 Hz or more and 500 Hz or less. The second drive frequency is preferably equal to or less than the first drive frequency, more preferably equal to or less than 1/2 the first drive frequency, and even more preferably equal to or less than 1/5 the first drive frequency.

Of the sub-display units 95 overlapping the third region S3, a third region 29C may be set outside the second region 29B (see FIG. 36(C)), and the drive frequency (also referred to as the "third drive frequency") of the sub-display units 95 included in the third region 29C may be lower than that of the second region 29B. The third drive frequency is preferably equal to or lower than the second drive frequency, more preferably equal to or lower than 1/2 the second drive frequency, and even more preferably equal to or lower than 1/5 the second drive frequency. By significantly reducing the number of times the image is rewritten, power consumption can be further reduced. Also, if necessary, rewriting of image data may be stopped. By stopping rewriting of image data, power consumption can be further reduced.

When performing such a driving method, it is preferable to use a transistor with an extremely low off-state current as the transistor that constitutes the pixel circuit 51. For example, an OS transistor is preferable as the transistor that constitutes the pixel circuit 51. Since an OS transistor has an extremely low off-state current, it is possible to hold image data supplied to the pixel circuit 51 for a long period of time. In particular, it is preferable to use an OS transistor as the transistor 52A.

When the video scene displayed on the display unit 93 changes, an image with significantly different brightness, contrast, or color tone than the previous image may be displayed. In such a case, a difference occurs in the timing of image switching between the first area 29A and an area with a lower drive frequency than the first area 29A, and the brightness, contrast, or color tone may differ significantly between the two areas, which may result in a loss of effective display quality. In such a case, when the video scene changes, the images in areas other than the first area 29A can be rewritten at the same drive frequency as the first area 29A, and then the drive frequency of the areas other than the first area 29A can be lowered.

If it is determined that the amount of change in the gaze point G has exceeded a certain amount, the image in areas other than the first area 29A may be rewritten at the same drive frequency as the first area 29A, and if it is determined that the amount of change is within the certain amount, the drive frequency in areas other than the first area 29A may be reduced. Also, if it is determined that the amount of change in the gaze point G is small, the drive frequency in areas other than the first area 29A may be further reduced.

If the display device 90B does not have a frame memory, which is a storage device that temporarily stores image data, or if it has one frame memory for the entire display unit 93, the second drive frequency and the third drive frequency must both be an integer fraction of the first drive frequency.

By providing frame memories corresponding to each of the multiple sub-display units 95, the second drive frequency and the third drive frequency can be set to any value, not limited to an integer division of the first drive frequency. By setting the second drive frequency and the third drive frequency to any value, the degree of freedom in setting the drive frequency can be increased. Therefore, the actual deterioration of the display quality can be reduced.

The areas set in the display unit 93 are not limited to the first area 29A, the second area 29B, and the third area 29C. Four or more areas may be set in the display unit 93. By setting multiple areas in the display unit 93 and gradually lowering the drive frequency, the actual degradation of the display quality can be further reduced.

The image to be displayed in the first area 29A may be subjected to the upconversion process described above. By displaying an upconverted image in the first area 29A, the display quality can be improved. Furthermore, the image to be displayed in an area other than the first area 29A may be subjected to the upconversion process described above. By displaying an upconverted image in an area other than the first area 29A, the actual decrease in display quality when the drive frequency in an area other than the first area 29A is reduced can be reduced.

The upconversion process of the image displayed in the first area 29A may be performed using a high-precision algorithm, and the upconversion process of the image displayed in areas other than the first area 29A may be performed using a low-precision algorithm. Even in such a case, the actual deterioration in display quality when the drive frequency of areas other than the first area 29A is reduced can be reduced.

When the resolution of the image data is greater than the resolution of the display unit 93, or when high-speed rewriting and reduced power consumption are to be prioritized, images displayed in areas other than the first area 29A may be down-converted depending on the purpose. For example, images displayed in areas other than the first area 29A may be rewritten every few rows, every few columns, or every few pixels, thereby realizing high-speed rewriting and reduced power consumption.

By making the resolution of the image displayed in areas other than the first area 29A smaller than the resolution of the image displayed in the first area 29A including the gaze point, the load during video signal generation (rendering) is reduced. This type of processing is also called "foveated rendering." By combining foveated rendering with a reduction in the drive frequency of areas other than the first area 29A, it is possible to achieve further reductions in power consumption while minimizing degradation in display quality.

By simultaneously rewriting image data for each sub-display section 95 on all sub-display sections 95, high-speed rewriting can be achieved. In other words, by simultaneously rewriting image data for each section 39 on all sections 39, high-speed rewriting can be achieved.

In general, in the case of line-sequential driving, the source driver circuit writes image data to all pixels in one row simultaneously while the gate driver circuit selects the pixels in one row. For example, if the display section 93 is not divided into the sub-display section 95 and has a resolution of 4000 x 2000 pixels, the source driver circuit needs to write image data to 4000 pixels while the gate driver circuit selects the pixels in one row. When the frame frequency is 120 Hz, the time for one frame is about 8.3 msec. Therefore, the gate driver needs to select 2000 rows in about 8.3 msec, and the time for selecting one gate line, that is, the time for writing image data per pixel, is about 4.17 μsec. In other words, the higher the resolution of the display section and the higher the frame frequency, the more difficult it becomes to ensure sufficient time for rewriting image data.

In the display device 90B exemplified in this embodiment, the display section 93 is divided into four in the row direction. Therefore, in one sub-display section 95, the time required to write image data per pixel can be four times longer than when the display section 93 is not divided. According to one aspect of the present invention, even when the frame frequency is set to 240 Hz or even 360 Hz, it is easy to ensure the time required to rewrite image data, thereby realizing a display device with high display quality.

In the display device 90B illustrated in this embodiment, the display unit 93 is divided into four in the row direction, so the length of the wiring SL that electrically connects the source driver circuit and the pixel circuit is reduced to one-quarter. As a result, the resistance value and parasitic capacitance of the wiring SL are each reduced to one-quarter, and the time required to write (rewrite) image data can be shortened.

In addition, in the display device 90B exemplified in this embodiment, the display unit 93 is divided into eight in the column direction, so the length of the wiring GL that electrically connects the gate driver circuit and the pixel circuit is reduced to one-eighth. As a result, the resistance value and parasitic capacitance of the wiring GL are each reduced to one-eighth, improving signal degradation and delay and making it easier to ensure the time required to rewrite image data.

According to the display device 90B of one aspect of the present invention, it is easy to ensure sufficient time for writing image data, so that high-speed rewriting of the displayed image can be realized. Therefore, a display device with high display quality can be realized. In particular, a display device with excellent moving image display can be realized.

Here, the application of the display device 90 according to one embodiment of the present invention to a thin client will be described. In recent years, thin clients that perform the main arithmetic processing on the server side and only limited processing on the client side have been attracting attention. As execution methods for thin clients, the network boot method, server-based method, blade PC method, and desktop virtualization (VDI) method have been proposed.

In either method, a thin client transmits a large amount of data from a server to a client, resulting in a large amount of power consumption during data transmission. By using an electronic device including a display device 90 according to one embodiment of the present invention as a client, it is possible to achieve power saving during data transmission.

In the display device 90B according to one embodiment of the present invention, the display unit 93 is divided into 32 sub-display units 95. However, the display device 90B according to one embodiment of the present invention is not limited to 32 divisions, and may be divided into 16, 64, or 128 divisions. Increasing the number of divisions of the display unit 93 can reduce the actual decrease in display quality felt by the user.

The configuration examples illustrated in this embodiment and the corresponding drawings, etc. can be combined, at least in part, with other configuration examples or drawings, etc. as appropriate.

This embodiment and the corresponding drawings, etc. can be implemented by appropriately combining at least a part of them with other embodiments or examples described in this specification. In addition, the multiple configurations shown in this embodiment and the corresponding drawings, etc. can be appropriately combined with each other.

(Embodiment 6)
In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

The electronic device of this embodiment has a display device of one embodiment of the present invention in a display portion. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device can be used in the display portion of various electronic devices.

The semiconductor device of one embodiment of the present invention can be applied to parts other than the display part of an electronic device. For example, by using the semiconductor device of one embodiment of the present invention in a control part of an electronic device, it is possible to reduce power consumption, which is preferable.

Examples of electronic devices include television devices, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

In particular, the display device of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display unit because it is possible to increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.

The display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), and 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or more is preferable. In addition, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display device having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. In addition, there is no particular limitation on the screen ratio (aspect ratio) of the display device of one embodiment of the present invention. For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

The electronic device of this embodiment may have a sensor (including a function to sense, detect, or measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).

The electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

The electronic device 6500 shown in FIG. 37(A) is a portable information terminal that can be used as a smartphone.

The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, etc. The display portion 6502 has a touch panel function.

A display device of one embodiment of the present invention can be applied to the display portion 6502.

Figure 37 (B) is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

A transparent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

The display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).

In an area outside the display unit 6502, a part of the display panel 6511 is folded back, and the FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

The flexible display device of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while keeping the thickness of the electronic device small. In addition, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the display portion 6502, an electronic device with a narrow frame can be realized.

Figure 37 (C) shows an example of a television device. In the television device 7100, a display unit 7000 is built into a housing 7101. In this example, the housing 7101 is supported by a stand 7103.

A display device according to one embodiment of the present invention can be applied to the display unit 7000.

The television set 7100 shown in FIG. 37C can be operated using an operation switch provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. The channel and volume can be operated by the operation keys or touch panel provided on the remote control 7111, and the image displayed on the display portion 7000 can be operated.

The television device 7100 is configured to include a receiver and a modem. The receiver can receive general television broadcasts. In addition, by connecting to a wired or wireless communication network via the modem, it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

Figure 37 (D) shows an example of a notebook personal computer. The notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. The display unit 7000 is incorporated in the housing 7211.

A display device according to one embodiment of the present invention can be applied to the display unit 7000.

Figures 37(E) and 37(F) show examples of digital signage.

The digital signage 7300 shown in FIG. 37 (E) has a housing 7301, a display unit 7000, a speaker 7303, and the like. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, and the like.

Figure 37 (F) shows a digital signage 7400 attached to a cylindrical pole 7401. The digital signage 7400 has a display unit 7000 that is provided along the curved surface of the pole 7401.

In Figures 37 (E) and 37 (F), a display device of one embodiment of the present invention can be applied to the display portion 7000.

The wider the display unit 7000, the more information can be provided at one time. Also, the wider the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of, for example, advertisements.

By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

As shown in FIG. 37(E) and FIG. 37(F), it is preferable that the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. In addition, the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.

The digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.

The electronic device shown in Figures 38(A) to 38(G) has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), a microphone 9008, etc.

In Figures 38(A) to 38(G), a display device of one embodiment of the present invention can be applied to the display portion 9001.

The electronic devices shown in Figures 38(A) to 38(G) have various functions. For example, they can have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they can have various functions. The electronic devices may have multiple display units. In addition, the electronic devices may have a function of providing a camera or the like to capture still images or videos and store them on a recording medium (external or built into the camera), a function of displaying the captured images on the display unit, etc.

The details of the electronic devices shown in Figures 38(A) to 38(G) are described below.

Fig. 38 (A) is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. The mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on a plurality of surfaces. Fig. 38 (A) shows an example in which three icons 9050 are displayed. Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, telephone calls, etc., the title of e-mail or SNS, the sender's name, the date and time, the remaining battery level, and radio wave intensity. Alternatively, an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.

Figure 38 (B) is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are each displayed on different sides. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and determine, for example, whether or not to answer a call.

Figure 38 (C) is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 is capable of executing various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games, for example. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of the housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

Figure 38 (D) is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also make hands-free calls by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also transmit data to and from other information terminals and charge itself through the connection terminal 9006. Note that charging may be performed by wireless power supply.

38(E) to 38(G) are perspective views showing a foldable mobile information terminal 9201. FIG. 38(E) shows the mobile information terminal 9201 in an unfolded state, FIG. 38(G) shows the mobile information terminal 9201 in a folded state, and FIG. 38(F) shows a perspective view of the mobile information terminal 9201 in a state in the middle of changing from one of FIG. 38(E) and FIG. 38(G) to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent visibility of the display. The display portion 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display portion 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.

This embodiment and the corresponding drawings, etc. can be implemented by appropriately combining at least a part of them with other embodiments or examples described in this specification. In addition, the multiple configurations shown in this embodiment and the corresponding drawings, etc. can be appropriately combined with each other.

(Seventh embodiment)
In this embodiment, a configuration example of a sub-display section 95 having a plurality of pixels 230 arranged in a matrix of p rows and q columns (p and q are each an integer of 2 or more) will be described. Fig. 39(A) is a block diagram illustrating the sub-display section 95. The sub-display section 95 is electrically connected to a source driver circuit 66 and a gate driver circuit 33 provided in a section 39.

In FIG. 39(A), pixel 230 in row p, column 1 is indicated as pixel 230[p,1], pixel 230 in row 1, column q is indicated as pixel 230[1,q], and pixel 230 in row p, column q is indicated as pixel 230[p,q].

The circuit included in the gate driver circuit 33 functions, for example, as a scanning line driving circuit. The circuit included in the source driver circuit 66 functions, for example, as a signal line driving circuit.

For example, an OS transistor may be used as the transistor constituting the pixel 230, and a Si transistor may be used as the transistor constituting the driver circuit. Since an OS transistor has a small off-state current, power consumption can be reduced. Furthermore, since an Si transistor has a faster operating speed than an OS transistor, it is preferable to use the Si transistor in the driver circuit. Furthermore, depending on the display device, an OS transistor may be used as both the transistor constituting the pixel 230 and the transistor constituting the driver circuit. Furthermore, depending on the display device, a Si transistor may be used as both the transistor constituting the pixel 230 and the transistor constituting the driver circuit. Alternatively, depending on the display device, a Si transistor may be used as the transistor constituting the pixel 230, and an OS transistor may be used as the transistor constituting the driver circuit.

Both Si transistors and OS transistors may be used for the transistors that make up the pixel 230. In addition, both Si transistors and OS transistors may be used for the transistors that make up the driver circuit.

39(A) shows p wirings GL arranged approximately in parallel and whose potentials are controlled by the gate driver circuit 33, and q wirings SL arranged approximately in parallel and whose potentials are controlled by the source driver circuit 66. For example, the pixel 230 arranged in the rth row (r indicates an arbitrary number, and in this embodiment, etc., is an integer of 1 to p) is electrically connected to the gate driver circuit 33 through the wiring GL in the rth row. The pixel 230 arranged in the sth column (s indicates an arbitrary number, and in this embodiment, etc., is an integer of 1 to q) is electrically connected to the source driver circuit 66 through the wiring SL in the sth column. In FIG. 39(A), the pixel 230 in the rth row and sth column is shown as pixel 230[r,s].

Note that the number of wirings GL electrically connected to the pixels 230 included in one row is not limited to one. Also, the number of wirings SL electrically connected to the pixels 230 included in one column is not limited to one. Also, the wirings GL and SL are merely examples, and the wirings connected to the pixels 230 are not limited to the wirings GL and SL.

A pixel 230 that controls red light, a pixel 230 that controls green light, and a pixel 230 that controls blue light are arranged in a stripe pattern, and these are grouped together to function as one pixel 240. By controlling the amount of light emitted (light emission brightness) of each pixel 230, a full-color display can be realized. In other words, each of the three pixels 230 functions as a sub-pixel. That is, each of the three sub-pixels controls the amount of light emitted, etc., of red light, green light, or blue light (see FIG. 39 (B1)). Note that the color of light controlled by each of the three sub-pixels is not limited to a combination of red (R), green (G), and blue (B), but may also be cyan (C), magenta (M), or yellow (Y) (see FIG. 39 (B2)).

When the pixels 240 are arranged in a 1920 x 1080 matrix, a display unit 93 capable of full-color display at so-called 2K resolution can be realized. Furthermore, for example, when the pixels 240 are arranged in a 3840 x 2160 matrix, a display unit 93 capable of full-color display at so-called 4K resolution can be realized. Furthermore, for example, when the pixels 240 are arranged in a 7680 x 4320 matrix, a display unit 93 capable of full-color display at so-called 8K resolution can be realized. By increasing the number of pixels 240, it is also possible to realize a display unit 93 capable of full-color display at 16K or even 32K resolution.

The arrangement of the three pixels 230 constituting one pixel 240 may be a delta arrangement (see FIG. 39 (B3)). Specifically, the three pixels 230 constituting one pixel 240 may be arranged so that the lines connecting the center points of each of them form a triangle. Note that the arrangement of the pixels 230 is not limited to the stripe arrangement and delta arrangement. The arrangement of the pixels 230 may be a zigzag arrangement, an S-stripe arrangement, a Bayer arrangement, or a Pentile arrangement.

The areas of the three sub-pixels (pixel 230) do not have to be the same. If the luminous efficiency and reliability differ depending on the luminous color, the area of the sub-pixels may be changed for each luminous color (see FIG. 39 (B4)).

Four subpixels may be combined to function as one pixel. For example, a subpixel that controls white light may be added to three subpixels that control red, green, and blue light, respectively (see FIG. 39 (B5)). By adding a subpixel that controls white light, the luminance of the display area can be increased. A subpixel that controls yellow light may be added to three subpixels that control red, green, and blue light, respectively (see FIG. 39 (B6)). A subpixel that controls white light may be added to three subpixels that control cyan, magenta, and yellow light, respectively (see FIG. 39 (B7)).

By increasing the number of sub-pixels that function as one pixel and by appropriately combining sub-pixels that control red, green, blue, cyan, magenta, and yellow light, the reproducibility of intermediate tones can be improved, thereby improving the display quality.

The display device of one embodiment of the present invention can reproduce color gamuts of various standards. For example, the PAL (Phase Alternating Line) standard and NTSC (National Television System Committee) standard used in television broadcasting, the sRGB (standard RGB) standard and Adobe RGB standard widely used in display devices for electronic devices such as personal computers, digital cameras, and printers, and the ITU-R BT. It can reproduce the color gamuts of the International Telecommunication Union Radiocommunication Sector Broadcasting Service (Television) 709 (International Telecommunication Union Radiocommunication Sector Broadcasting Service (Television) 709) standard, the Digital Cinema Initiatives P3 (DCI-P3) standard used in digital cinema projection, and the ITU-R BT. 2020 (REC. 2020 (Recommendation 2020)) standard used in UHDTV (Ultra High Definition Television, also known as Super Hi-Vision).

One pixel 240 may be provided with a pixel 237 including a light receiving element. In the pixel 240 shown in FIG. 40(A), a pixel 230 (G) that emits green light, a pixel 230 (B) that emits blue light, a pixel 230 (R) that emits red light, and a pixel 237 (S) that has a light receiving element are arranged in a stripe pattern. Note that in this specification and other places, the pixel 237 is also referred to as an "imaging pixel."

The light receiving element of pixel 237 is preferably an element that detects visible light, and is preferably an element that detects one or more of light such as blue, purple, blue-purple, green, yellow-green, yellow, orange, and red. The light receiving element of pixel 237 may also be an element that detects infrared light.

The pixel 240 shown in FIG. 40(A) has a stripe arrangement. When detecting light of a specific color using a pixel 237 having a light receiving element, it is preferable to arrange a pixel 230 that exhibits light of that color next to the pixel 237, as this can improve detection accuracy.

The pixel 240 shown in FIG. 40(B) has three pixels 230 and one pixel 237 arranged in a matrix. FIG. 40(B) shows an example in which the pixel 230 that emits red light is adjacent to the pixel 237 having a light receiving element in the row direction, and the pixel 230 that emits blue light and the pixel 230 that emits green light are adjacent to each other in the row direction, but this is not limiting.

The pixel 240 shown in FIG. 40(C) has a configuration in which pixel 237 is added to the S-stripe arrangement. The pixel 240 in FIG. 40(C) has one vertically elongated pixel 230, two horizontally elongated pixels 230, and one horizontally elongated pixel 237. Note that the vertically elongated pixel 230 may be R, G, or S, and there is no limitation on the order of the horizontally elongated sub-pixels.

Figure 40 (D) shows an example in which pixels 240a and pixels 240b are arranged alternately. Pixel 240a has a pixel 230 that exhibits blue light, a pixel 230 that exhibits green light, and a pixel 237 that has a light receiving element. Pixel 240b has a pixel 230 that exhibits red light, a pixel 230 that exhibits green light, and a pixel 237 that has a light receiving element. Pixels 240a and 240b function together as one pixel 240. In Figure 40 (D), both pixels 240a and 240b have a pixel 230 that exhibits green light and a pixel 237, but this is not limited thereto. By having both pixels 240a and 240b have pixel 237, the definition of the imaging pixel can be increased.

The layout shown in FIG. 40(E) is preferable because it increases the aperture ratio of each subpixel. Also, FIG. 40(F) shows an example in which the top surface shapes of pixel 230 and pixel 237 are hexagonal.

The pixel 240 shown in FIG. 40(F) is an example in which pixels 230 are arranged in a single horizontal row, with pixel 237 arranged below them.

The pixel 240 shown in FIG. 40(G) is an example in which pixel 230 and pixel 230X are arranged in a single horizontal row, with pixel 237 arranged below them.

For example, pixel 230 that emits infrared light (IR) can be applied to pixel 230X. That is, pixel 230X has a light-emitting device 61 that emits infrared light (IR). In this case, pixel 237 preferably has a light-receiving element that detects infrared light. For example, while an image is displayed by pixel 230 that emits visible light, reflected infrared light emitted by sub-pixel X can be detected by pixel 237.

A single pixel 240 may have multiple pixels 237. In this case, the wavelength range of light detected by the multiple pixels 237 may be the same or different. For example, some of the multiple pixels 237 may detect visible light, and other parts may detect infrared light.

Pixel 237 does not have to be provided in all pixels 240. Pixels 240 including pixel 237 may be provided for every certain number of pixels.

By using the pixel 237, or by using the pixel 237 and the sensor 97 described above, it is possible to detect information for personal authentication using, for example, a fingerprint, palm print, iris, retina, pulse shape (including vein shape and artery shape), face, etc. In addition, by using the pixel 237, or by using the pixel 237 and the sensor 97, it is possible to measure the number of times the user blinks, eyelid behavior, pupil size, body temperature, pulse rate, oxygen saturation in the blood, etc., and detect the user's fatigue level and health condition, etc.

The movement of the user's gaze, the number of blinks, the blinking rhythm, and the like can be used to operate the electronic device. Specifically, the pixel 237, or the pixel 237 and the sensor 97, can be used to detect information such as the movement of the user's gaze, the number of blinks, and the blinking rhythm, and one or more combinations of this information can be used as an operation signal for the electronic device. For example, blinks can be replaced with mouse clicks. By detecting the movement of the gaze and blinks, the user can perform input operations on the electronic device without holding anything in their hands. This can improve the operability of the electronic device.

For example, by providing a plurality of imaging pixels (pixels 237) in the display device 90 of the glasses-type electronic device 150 described in embodiment 5, the plurality of imaging pixels can be used as the gaze detection unit 84. This allows the number of components of the electronic device to be reduced. This allows the electronic device to be made lighter, more productive, and less expensive.

<Example of light-emitting device configuration>
A light-emitting device 61 that can be used in a display device according to one embodiment of the present invention will be described.

As shown in FIG. 41A, the light-emitting device 61 includes an EL layer 175 between a pair of electrodes (conductive layer 171, conductive layer 177). The EL layer 175 can be composed of multiple layers such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can include, for example, a layer including a substance with high electron injection properties (electron injection layer) and a layer including a substance with high electron transport properties (electron transport layer). The light-emitting layer 4411 includes, for example, a light-emitting compound. The layer 4430 can include, for example, a layer including a substance with high hole injection properties (hole injection layer) and a layer including a substance with high hole transport properties (hole transport layer).

A structure including layer 4420, light-emitting layer 4411, and layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and in this specification and elsewhere, the structure in FIG. 41(A) is referred to as a single structure.

Figure 41 (B) is a modified example of the EL layer 175 provided in the light-emitting device 61 shown in Figure 41 (A). Specifically, the light-emitting device 61 shown in Figure 41 (B) includes a layer 4430-1 on the conductive layer 171, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and a conductive layer 177 on the layer 4420-2. For example, when the conductive layer 171 is an anode and the conductive layer 177 is a cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. Alternatively, when the conductive layer 171 is a cathode and the conductive layer 177 is an anode, the layer 4430-1 functions as an electron injection layer, the layer 4430-2 functions as an electron transport layer, the layer 4420-1 functions as a hole transport layer, and the layer 4420-2 functions as a hole injection layer. By using such a layer structure, it is possible to efficiently inject carriers into the light-emitting layer 4411 and increase the efficiency of carrier recombination in the light-emitting layer 4411.

Note that a structure in which multiple light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between layer 4420 and layer 4430 as shown in FIG. 41(C) is also an example of a single structure.

As shown in FIG. 41D, a configuration in which multiple light-emitting units (EL layer 175a, EL layer 175b) are connected in series via an intermediate layer (charge generating layer) 4440 is referred to as a tandem structure or stack structure in this specification. By using a tandem structure, a light-emitting device capable of emitting light with high brightness can be realized.

When the light-emitting device 61 has a tandem structure as shown in FIG. 41(D), the luminescent color of the EL layer 175a and the EL layer 175b may be the same. For example, the luminescent color of the EL layer 175a and the EL layer 175b may both be green.

In addition, a light-emitting device 61 that emits red light (R), a light-emitting device 61 that emits green light (G), and a light-emitting device 61 that emits blue light (B) are used as sub-pixels, and one pixel is formed from these three sub-pixels, thereby realizing full-color display. When the display unit 93 includes three types of sub-pixels, R, G, and B, the light-emitting devices may be in a tandem structure. Specifically, the EL layer 175a and the EL layer 175b of the R sub-pixel each have a material capable of emitting red light, the EL layer 175a and the EL layer 175b of the G sub-pixel each have a material capable of emitting green light, and the EL layer 175a and the EL layer 175b of the B sub-pixel each have a material capable of emitting blue light. In other words, the material of the light-emitting layer 4411 and the light-emitting layer 4412 may be the same. By making the luminous colors of the EL layer 175a and the EL layer 175b the same, the current density per unit luminous brightness can be reduced. This improves the reliability of the light-emitting device 61.

The light emission color of the light emitting device can be red, green, blue, cyan, magenta, yellow, or white, depending on the material that constitutes the EL layer 175. In addition, the color purity can be further improved by providing the light emitting device with a microcavity structure.

The light-emitting layer may contain two or more types of luminescent materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. It is preferable that a light-emitting device that emits white light has a configuration in which the light-emitting layer contains two or more types of luminescent materials. To obtain white light emission, it is sufficient to select luminescent materials that produce white light when the respective emissions of the two or more luminescent materials are mixed. For example, by making the luminescent color of the first luminescent layer and the luminescent color of the second luminescent layer complementary to each other, a light-emitting device that emits white light as a whole can be obtained. The same applies to a light-emitting device having three or more luminescent layers.

The light-emitting layer preferably contains two or more types of luminescent materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more types of luminescent materials, and the light emitted by each of the luminescent materials contains spectral components of two or more colors of R, G, and B. Furthermore, a material that emits near-infrared light can also be used as the luminescent material.

Light-emitting substances include substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), and substances that exhibit thermally activated delayed fluorescence (TADF materials). Light-emitting substances can include not only organic compounds but also inorganic compounds (such as quantum dot materials).

This embodiment and the corresponding drawings, etc. can be implemented by appropriately combining at least a part of them with other embodiments or examples described in this specification. In addition, the multiple configurations shown in this embodiment and the corresponding drawings, etc. can be appropriately combined with each other.

In this example, a transistor was fabricated using a fabrication method according to one embodiment of the present invention, and a cross-sectional STEM (Scanning Transmission Electron Microscope) image was observed.

In this example, a sample having the transistor 200 shown in Figures 8(A) and 8(B) was fabricated using the method shown in Figures 13(A) to 16(C).

First, a glass substrate was prepared, and a silicon nitride film with a thickness of 200 nm was formed on the glass substrate by the PECVD method to obtain the insulating layer 102.

Next, a 100 nm thick ITSO film was formed on the insulating layer 102 by sputtering, and then processed to obtain conductive layer 212a and conductive layer 212b.

Next, an aluminum oxide film with a thickness of 5 nm was formed by sputtering to cover the conductive layer 212a and the conductive layer 212b, obtaining the insulating layer 110a.

Next, a silicon oxynitride film with a thickness of 500 nm was formed on the insulating layer 110a by the PECVD method to obtain the insulating layer 110b.

Furthermore, after the insulating layer 110b was formed, a plasma treatment was performed without exposure to the air. The plasma treatment was performed using N ₂ O gas at a substrate temperature of 350° C. for 240 seconds.

Next, a process was performed to supply oxygen to the insulating layer 110b.

To supply oxygen to the insulating layer 110b, a metal oxide layer 137 with a thickness of 20 nm was first formed on the insulating layer 110b by sputtering at room temperature in a 100% oxygen atmosphere using a sputtering target with an atomic ratio of metal elements of In:Ga:Zn = 1:1:1.

Next, a heat treatment was performed. The heat treatment was performed in a dry air atmosphere at a treatment temperature of 250 degrees for a treatment time of 1 hour.

Then, the metal oxide layer 137 was removed.

Through this series of processes, oxygen was supplied to the insulating layer 110b.

Next, an aluminum oxide film with a thickness of 5 nm was formed on the insulating layer 110b by sputtering to obtain the insulating layer 110c.

Next, the insulating layer 102 and the insulating layer 110 (insulating layers 110a to 110c) were processed by a dry etching method to form recesses 145 in the insulating layer 102 and the insulating layer 110 so as to have areas that overlap with the conductive layers 212a and 212b in a plan view.

Next, a metal oxide film 208f having a thickness of 20 nm was formed on the insulating layer 110 so as to cover the recess 145. The metal oxide film 208f was formed by a sputtering method using a sputtering target with an atomic ratio of metal elements of In:Ga:Zn = 1:1:1. The substrate temperature during the formation was room temperature, and a mixture of oxygen gas and argon gas was used as the film formation gas, with the oxygen flow ratio being 10%.

Next, a positive photoresist 159f having a thickness of 2.5 μm was applied onto the metal oxide film 208f so as to cover the recess 145, and the entire surface of the photoresist 159f was irradiated with light 149 (ultraviolet rays).

Next, the portions of the photoresist 159f that were irradiated with the light 149 (exposed portions) were removed to form a resist mask 159.

Next, the exposed portion of the metal oxide film 208f (the portion not covered by the resist mask 159) was removed by wet etching using an aluminum mixed acid solution to form a semiconductor layer 208 in contact with the sidewalls of the recess 145 (the side of the insulating layer 110, the side of the conductive layer 212a, and the side of the conductive layer 212b). The aluminum mixed acid solution is an aqueous solution containing less than 5% nitric acid, less than 10% acetic acid, and less than 80% phosphoric acid.

Next, the resist mask 159 remaining in the recess 145 was removed.

Next, a plasma treatment was performed using N ₂ O gas at a substrate temperature of 350° C. for 20 seconds.

After the above-mentioned plasma treatment, a silicon oxynitride film with a thickness of 50 nm was then formed by PECVD on the semiconductor layer 208 and the insulating layer 110 without exposure to the atmosphere so as to cover the recess 145, thereby obtaining the insulating layer 106.

Next, a laminated film of a 50 nm-thick titanium film, a 200 nm-thick aluminum film, and a 50 nm-thick titanium film was formed on the insulating layer 106 by sputtering, and the laminated film was processed to have an area that overlaps the recess 145 in a plan view, thereby obtaining a conductive layer 204.

Through the above steps, transistor 200 was produced.

Next, a silicon nitride oxide film with a thickness of 300 nm was formed by PECVD to cover the fabricated transistor 200, obtaining an insulating layer 195.

Next, heat treatment was performed at 300°C for 1 hour in a dry air atmosphere.

Next, a polyimide resin layer with a thickness of 1.5 μm was formed to cover the insulating layer 195.

Then, heat treatment was performed in a nitrogen atmosphere at 250°C for 1 hour.

In this manner, a sample having a transistor 200 was produced.

The cross-sectional STEM images of the above sample are shown in Figures 42(B) and 42(C), 43(A) and 43(B). Here, Figure 42(A) is an optical microscope photograph of the above sample, Figure 42(B) is a cross-sectional STEM image corresponding to the dashed line A-A' in Figure 42(A), and Figure 42(C) is a cross-sectional STEM image corresponding to the dashed line B-B' in Figure 42(A). Also, Figure 43(A) is an enlarged photograph of Figure 42(B), and Figure 43(B) is an enlarged photograph of Figure 42(C). The above sample was photographed using a Hitachi High-Technologies Corporation scanning transmission electron microscope (STEM) (model number: HD-2300) at an accelerating voltage of 200 kV.

As shown in Figures 43(A) and 43(B), it was confirmed that the semiconductor layer 208 was formed in the recess 145 in contact with the side of the insulating layer 110 and the upper surface and side of the conductive layer 212a. It was also confirmed that the material layer 208m was formed on the bottom surface of the recess 145 separately from the semiconductor layer 208. It was also confirmed that the insulating layer 106 was provided covering the semiconductor layer 208 and the material layer 208m, and the conductive layer 204 was provided on the insulating layer 106.

As described above, in this embodiment, it was confirmed that the recesses 145 were formed in the insulating layers 102 and 110 as intended. It was also confirmed that the semiconductor layer 208 was formed separately on the sidewalls of the recesses 145, and the material layer 208m was formed separately on the bottom surface of the recesses 145.

From the above, it was confirmed that the transistor 200 could be manufactured using the manufacturing method of one embodiment of the present invention.

This embodiment can be combined with the embodiment modes as appropriate.

10 Semiconductor device 20A Transistor 20a Transistor 20b Transistor 20 Transistor 21a Semiconductor layer 21b Semiconductor layer 21m Material layer 21 Semiconductor layer 22 Insulating layer 23 Conductive layer 24a Conductive layer 24b Conductive layer 26a Extension portion 26b Extension portion 26c Extension portion 27 Cavity 28a Bent portion 28b Bent portion 29A First area 29B Second area 29C Third area 30 Recess 31 Insulating layer 32 Insulating layer 33 Gate driver circuit 34 Level shifter 35 Amplifying circuit 36 Inspection circuit 37 Video generation circuit 38 Video distribution circuit 39 Section 40 Functional circuit 41 Storage device 42a Color unevenness correction 42b Up-conversion 42 GPU
43 EL correction circuit 44 Timing controller 45 CPU
46 Sensor controller 47 Power supply circuit 48 Temperature sensor 49 Brightness correction circuit 50A Display device 50B Display device 51A Pixel circuit 51B Pixel circuit 51C Pixel circuit 51D Pixel circuit 51E Pixel circuit 51F Pixel circuit 51G Pixel circuit 51H Pixel circuit 51 Pixel circuit 52A Transistor 52B Transistor 52C Transistor 52D Transistor 52 Transistor 53A Capacitor 53 Capacitor 54 Channel formation region 55 Pixel circuit group 59 Section 61 Light emitting device 62 Layer 63 Transistor 64 Channel formation region 65 Drive circuit 66 Source driver circuit 67 Digital-to-analog conversion circuit 71 Element layer 73 Element layer 75 Element layer 77 Wiring layer 80 Input/output circuit 81 Layer 83 Layer 84 Line-of-sight detection unit 85 Communication unit 86 Mounting unit 87 Buffer member 88 Lens 89 Output terminal 90_L Display device 90_R Display device 90A Display device 90B Display device 90 Display device 91 Substrate 92 Substrate 93 Display section 94 Terminal section 95 Sub-display section 97 Sensor 98 Input terminal 99A Earphone 99B Earphone 100A Transistor 100B Transistor 100 Transistor 101 Motion detection section 102 Insulating layer 103 Arithmetic section 104 Conductive layer 105 Housing 106 Insulating layer 107 Adhesive layer 108 Semiconductor layer 110a Insulating layer 110b Insulating layer 110b1 Insulating layer 110b2 Insulating layer 110c Insulating layer 110d1 Insulating layer 110d2 Insulating layer 110 Insulating layer 111 Pixel electrode 112a Conductive layer 112b Conductive layer 112f Conductive film 112s Conductive layer 113a First layer 113b Second layer 113c Third layer 114 Common layer 115 Common electrode 116 Conductive layer 118a Mask layer 119 Substrate 125 Insulating layer 126a Conductive layer 126b Conductive layer 126c Conductive layer 127 Insulating layer 128 Layer 129a Conductive layer 129b Conductive layer 129c Conductive layer 130B Light emitting device 130G Light emitting device 130R Light emitting device 130 Light emitting device 131 Protective layer 137 Metal oxide layer 140 Connection portion 141 Opening 142 Recess 143 Opening 145a Opening 145b Recess 145 Recess 149 Light 150 Electronic device 151 Substrate 152 Substrate 156 Resist mask 158 Resist mask 159f Photoresist 159 Resist mask 162 Display portion 164 Circuit portion 165 Conductive layer 171 Conductive layer 172 FPC
173 IC
175a EL layer 175b EL layer 175 EL layer 177 Conductive layer 182a Conductive layer 182b Conductive layer 182c Conductive layer 195 Insulating layer 200A Transistor 200B Transistor 200C Transistor 200D Transistor 200 Transistor 204 Conductive layer 208f Metal oxide film 208m Material layer 208 Semiconductor layer 210 Pixel 212a Conductive layer 212b Conductive layer 216 Conductive layer 227 Cavity 230B Pixel 230G Pixel 230R Pixel 230X Pixel 230 Pixel 231 First driving circuit section 232 Second driving circuit section 233 Insulating layer 234 Conductive layer 235 Insulating layer 236 Wiring 237 Pixel 238 Wiring 240a Pixel 240b Pixel 240 Pixel 300 Transistor 310 Substrate 312 Element isolation layer 313 Semiconductor region 314 a Low resistance region 314 b Low resistance region 315 Insulating layer 316 Conductive layer 317 Insulating layer 320 Insulating layer 322 Insulating layer 324 Insulating layer 326 Insulating layer 328 Conductive layer 330 Conductive layer 350 Insulating layer 352 Insulating layer 354 Insulating layer 356 Conductive layer 441 Timing controller 442 Input/output circuit 500 Display module 501 Printed wiring board 502 Terminal portion 503 Wire 504 FPC
505 Connection portion 512 Insulating layer 514 Conductive layer 574 Insulating layer 581 Insulating layer 592 Insulating layer 594 Insulating layer 596 Conductive layer 598 Insulating layer 599 Insulating layer 4411 Light-emitting layer 4412 Light-emitting layer 4413 Light-emitting layer 4420-1 Layer 4420-2 Layer 4420 Layer 4430-1 Layer 4430-2 Layer 4430 Layer 4440 Intermediate layer 6500 Electronic device 6501 Housing 6502 Display portion 6503 Power button 6504 Button 6505 Speaker 6506 Microphone 6507 Camera 6508 Light source 6510 Protective member 6511 Display panel 6512 Optical member 6513 Touch sensor panel 6515 FPC
6516 IC
6517 Printed circuit board 6518 Battery 7000 Display unit 7100 Television device 7101 Housing 7103 Stand 7111 Remote control device 7200 Notebook personal computer 7211 Housing 7212 Keyboard 7213 Pointing device 7214 External connection port 7300 Digital signage 7301 Housing 7303 Speaker 7311 Information terminal device 7400 Digital signage 7401 Pillar 7411 Information terminal device 9000 Housing 9001 Display unit 9002 Camera 9003 Speaker 9005 Operation keys 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Icon 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9101 Portable information terminal 9102 Portable information terminal 9103 Tablet terminal 9200 Portable information terminal 9201 Portable information terminal

Claims (9)

a transistor, a first insulating layer, a second insulating layer, and a material layer;
a source electrode and a drain electrode of the transistor are provided in contact with an upper surface of the first insulating layer;
the second insulating layer is provided on the source electrode, the drain electrode, and the first insulating layer, and has an opening in a region overlapping with the source electrode and the drain electrode in a plan view;
the first insulating layer has a recess in a region overlapping with the opening in a plan view,
the source electrode and the drain electrode have an exposed region in a region overlapping with the recess in a plan view,
a sidewall of the recess is located outside an end of the source electrode and an end of the drain electrode in a region overlapping with the source electrode and the drain electrode in a plan view, and is located outside a sidewall of the opening in a region not overlapping with the source electrode and the drain electrode in a plan view;
a semiconductor layer of the transistor has a region in contact with a side surface of the second insulating layer, a side surface of the source electrode, and a side surface of the drain electrode in the opening;
The material layer is provided on a bottom surface of the recess,
a gate insulating layer of the transistor is provided in contact with the semiconductor layer and the material layer;
a gate electrode of the transistor is provided on the gate insulating layer so as to have a region overlapping with the recess in a plan view;
The semiconductor layer and the material layer have the same material and are provided separately from each other.
Semiconductor device. In claim 1,
The semiconductor layer comprises a metal oxide.
Semiconductor device. In claim 1 or 2,
the second insulating layer includes a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer;
The third insulating layer and the fifth insulating layer are one or more of silicon nitride, silicon oxynitride, or aluminum oxide;
The fourth insulating layer is one or more of silicon oxide or silicon oxynitride.
Semiconductor device. In claim 1 or 2,
a side surface of the source electrode and a side surface of the drain electrode protrude beyond a side surface of the second insulating layer within the opening;
Semiconductor device. In claim 1 or 2,
a side surface of the source electrode and a side surface of the drain electrode substantially coincide with a side surface of the second insulating layer within the opening;
Semiconductor device. In claim 1 or 2,
a side surface of the second insulating layer within the opening is perpendicular or approximately perpendicular to an upper surface of the first insulating layer;
Semiconductor device. In claim 1 or 2,
a side surface of the second insulating layer within the opening has a tapered shape with respect to an upper surface of the first insulating layer;
Semiconductor device. In claim 1 or 2,
the second insulating layer includes a third insulating layer, a fourth insulating layer on the third insulating layer, a fifth insulating layer on the fourth insulating layer, a sixth insulating layer on the fifth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer;
the third insulating layer, the fifth insulating layer, the sixth insulating layer, and the eighth insulating layer are one or more of silicon nitride, silicon oxynitride, or aluminum oxide;
The fourth insulating layer and the seventh insulating layer are one or more of silicon oxide or silicon oxynitride,
A conductive layer is provided between the fifth insulating layer and the sixth insulating layer.
Semiconductor device. forming a first insulating layer;
forming a first conductive layer and a second conductive layer on the first insulating layer;
forming a second insulating layer on the first insulating layer, the first conductive layer, and the second conductive layer;
processing the first insulating layer and the second insulating layer to form recesses in the first insulating layer and the second insulating layer so as to have regions overlapping with the first conductive layer and the second conductive layer in a plan view;
forming a metal oxide film on the first insulating layer and the second insulating layer so as to cover the recess;
applying a photoresist onto the metal oxide film so as to fill the recess;
Irradiating the photoresist with light;
removing the irradiated portion of the photoresist to form a resist mask;
removing the exposed portion of the metal oxide film to form a semiconductor layer in contact with a side surface of the second insulating layer, a side surface of the first conductive layer, and a side surface of the second conductive layer in the recess;
removing the resist mask remaining in the recess;
forming a third insulating layer on the semiconductor layer so as to cover the recess;
forming a third conductive layer on the third insulating layer so as to have a region overlapping with the recess in a plan view;
A method for manufacturing a semiconductor device.

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