JP2024143377A - NITRIDE SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - Google Patents

Abstract

To improve heat dissipation of a nitride semiconductor device.SOLUTION: A nitride semiconductor device 10 includes: a semiconductor substrate 12 having a substrate upper surface 12A and a substrate lower surface 12B; a nitride semiconductor layer 50 formed on the substrate upper surface 12A and thinner than the semiconductor substrate 12; an element 51 formed using the nitride semiconductor layer 50; an insulator layer 60 formed on the nitride semiconductor layer 50; and an electrode pad 70 formed on the insulator layer 60 and electrically connected to the element 51. A semiconductor substrate 12 includes a thin portion 81 that is relatively thin, and a thick portion 82 that is relatively thick. In a plan view, the thick portion 82 is disposed between the thin portion 81 and outer peripheral portions 12C, 12D of the semiconductor substrate 12.SELECTED DRAWING: Figure 2

Description

This disclosure relates to nitride semiconductor devices and semiconductor modules.

Currently, high electron mobility transistors (HEMTs) using Group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use two-dimensional electron gas (2DEG) formed near the interface of semiconductor heterojunctions as a conductive path (channel). Power devices using HEMTs are recognized as devices that enable lower on-resistance and faster, higher frequency operation than typical silicon (Si) power devices.

For example, the nitride semiconductor device described in Patent Document 1 includes a semiconductor substrate, and an electron transit layer and an electron supply layer formed on the semiconductor substrate. The electron transit layer is composed of a gallium nitride (GaN) layer. The electron supply layer is composed of an aluminum gallium nitride (AlGaN) layer. A 2DEG is formed in the electron transit layer near the interface of the heterojunction between the electron transit layer and the electron supply layer.

In addition, in the nitride semiconductor device of Patent Document 1, a gate layer (e.g., a p-type GaN layer) containing acceptor-type impurities is provided on the electron transit layer and directly below the gate electrode. In this configuration, in the region directly below the gate layer, the gate layer raises the band energy of the conduction band near the heterojunction interface between the electron transit layer and the electron supply layer, thereby eliminating the channel directly below the gate layer and achieving a normally-off state.

JP 2017-73506 A

As semiconductor devices become more sophisticated and multifunctional, chip-size packages, which are completed as packages at the wafer level, are becoming more and more practical. When applying nitride semiconductor devices, in which a nitride semiconductor layer such as a GaN layer is formed on a semiconductor substrate, to chip-size packages, there is a problem in that it is difficult to improve the heat dissipation performance of elements such as HEMTs that are constructed using the nitride semiconductor layer.

That is, the nitride semiconductor device configured as a chip-size package has electrode pads formed on the nitride semiconductor layer via an insulating layer. The nitride semiconductor device is then mounted on a mounting substrate with the front surface side on which the electrode pads are located facing the mounting substrate. Therefore, heat generated by elements included in the nitride semiconductor device is dissipated from the back surface side on which the semiconductor substrate is located, which is the surface opposite to the front surface on which the electrode pads are located. Therefore, in order to improve the heat dissipation of the nitride semiconductor device, it is conceivable to form the semiconductor substrate thin to reduce the thermal resistance of the semiconductor substrate.

However, in nitride semiconductor devices including elements such as HEMTs that are constructed using nitride semiconductor layers, the thickness of the nitride semiconductor layer is very thin compared to the thickness of the semiconductor substrate, so making the semiconductor substrate thinner makes it difficult to ensure strength. For example, if the thickness of the semiconductor substrate is made too thin, the wafer may crack due to the stress of the nitride semiconductor layer formed on the semiconductor substrate.

A nitride semiconductor layer according to one aspect of the present disclosure includes a semiconductor substrate having a substrate upper surface and a substrate lower surface facing the opposite side to the substrate upper surface, a nitride semiconductor layer formed on the substrate upper surface and thinner than the semiconductor substrate, an element configured using the nitride semiconductor layer, an insulator layer formed on the nitride semiconductor layer, and an electrode pad formed on the insulator layer and electrically connected to the element, the semiconductor substrate includes a thin portion having a relatively thin thickness and a thick portion having a relatively thick thickness, and in a plan view seen in the thickness direction of the semiconductor substrate, the thick portion is disposed between the thin portion and the outer periphery of the semiconductor substrate.

A semiconductor module according to one aspect of the present disclosure includes the nitride semiconductor device and a heat dissipation member attached to the underside of the semiconductor substrate.

The nitride semiconductor device and semiconductor module disclosed herein can improve heat dissipation.

FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device. FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. FIG. 3 is an exemplary schematic plan view of the device. FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. FIG. 5 is a schematic plan view showing the bottom surface of the semiconductor substrate. FIG. 6 is a schematic cross-sectional view of an example of a nitride semiconductor device mounted on a mounting substrate. FIG. 7 is a schematic plan view showing the bottom surface of a semiconductor substrate according to a modified example. FIG. 8 is a schematic plan view showing the bottom surface of a semiconductor substrate according to a modified example. FIG. 9 is a schematic cross-sectional view showing a nitride semiconductor device according to a modified example. FIG. 10 is a schematic plan view showing the bottom surface of a semiconductor substrate according to a modified example. FIG. 11 is a schematic plan view showing the bottom surface of a semiconductor substrate according to a modified example. FIG. 12 is a cross-sectional view taken along line 12-12 of FIG.

Hereinafter, embodiments of a nitride semiconductor device according to the present disclosure will be described with reference to the accompanying drawings.
For simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. The detailed description is merely explanatory in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[Schematic structure of nitride semiconductor device]
Fig. 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to the embodiment, Fig. 2 is a schematic cross-sectional view of the nitride semiconductor device 10, taken along line 2-2 of Fig. 1.

The term "planar view" as used in this disclosure refers to viewing the nitride semiconductor device 10 in the Z-axis direction of the mutually orthogonal XYZ axes shown in FIG. 1. For convenience, in the nitride semiconductor device 10 shown in FIGS. 1 and 2, the +Z direction is defined as up, the -Z direction as down, the +X direction as right, and the -X direction as left. Unless otherwise explicitly stated, "planar view" refers to viewing the nitride semiconductor device 10 from above along the Z-axis.

The nitride semiconductor device 10 is a chip-size package that is completed as a package in the wafer state.
As shown in Figures 1 and 2, the nitride semiconductor device 10 includes a chip surface 10s and a chip back surface 10r. Furthermore, the nitride semiconductor device 10 includes first to fourth chip side surfaces 10A to 10D that connect the chip surface 10s and the chip back surface 10r. The shape of the nitride semiconductor device 10 in a plan view, in other words, the shapes of the chip surface 10s and the chip back surface 10r in a plan view, are rectangular. The first chip side surface 10A and the second chip side surface 10B extend along the X-axis direction and are arranged to face the Y-axis direction. The third chip side surface 10C and the fourth chip side surface 10D extend along the Y-axis direction and are arranged to face the X-axis direction.

As shown in FIG. 2, the nitride semiconductor device 10 includes a semiconductor substrate 12, a nitride semiconductor layer 50 formed on the semiconductor substrate 12, an element 51 constructed using the nitride semiconductor layer 50, an insulator layer 60 formed on the nitride semiconductor layer 50, and an electrode pad 70 formed on the insulator layer 60.

The semiconductor substrate 12 may be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 12 may be a Si substrate. The semiconductor substrate 12 has a substrate upper surface 12A that faces one side in the thickness direction (Z-axis direction) and a substrate lower surface 12B that faces the opposite side to the substrate upper surface 12A. The substrate lower surface 12B of the semiconductor substrate 12 constitutes the chip back surface 10r of the nitride semiconductor device 10. Details of the shape of the semiconductor substrate 12 will be described later.

The nitride semiconductor layer 50 is a layer formed of a nitride semiconductor. The thickness T3 of the nitride semiconductor layer 50 is, for example, 1 μm or more and 10 μm or less. As will be described in detail later, the nitride semiconductor layer 50 includes multiple layers formed of nitride semiconductors. Therefore, the thickness T3 of the nitride semiconductor layer 50 means the overall thickness of the nitride semiconductor layer 50, that is, the total thickness of the multiple layers. The element 51 is a heat generating element that generates heat, and is constructed using the nitride semiconductor layer 50. The nitride semiconductor layer 50 and the element 51 will be described in detail later.

The insulator layer 60 may be made of a material including any one of silicon nitride (SiN), silicon dioxide (SiO ₂ ), silicon oxynitride (SiON), alumina (Al ₂ O ₃ ), AlN, and aluminum oxynitride (AlON). In one example, the insulator layer 60 is made of a material including SiN.

The electrode pad 70 is formed on the upper surface of the insulator layer 60. The electrode pad 70 includes one or more source pads 71, one or more drain pads 72, and one or more gate pads 73. The source pad 71 is electrically connected to a source electrode 28, which will be described later. The drain pad 72 is electrically connected to a drain electrode 30, which will be described later. The gate pad 73 is electrically connected to a gate electrode 24, which will be described later. Each of the electrode pads 70 can be made of any conductive material including at least one of copper (Cu), aluminum (Al), an AlCu alloy, tungsten (W), titanium (Ti), and titanium nitride (TiN).

A bonding material ball 74 for electrical connection to the outside may be formed on the upper surface of each electrode pad 70. The bonding material ball 74 is formed, for example, in a substantially spherical shape using a bonding material such as solder. The number of bonding material balls 74 formed on the upper surface of one electrode pad 70 is not particularly limited. In addition, in one electrode pad 70, the bonding material ball 74 may be formed so as to cover a part of the upper surface of the electrode pad 70, or may be formed so as to cover the entire upper surface.

[Details of nitride semiconductor layer and element]
(Schematic structure of the element)
1, the nitride semiconductor device 10 includes an active region A1 located in the center of a semiconductor substrate 12, and a frame-shaped peripheral region A2 surrounding the active region A1 and located on the outer periphery of the semiconductor substrate 12. The active region A1 is a region in which elements 51 are formed, and the peripheral region A2 is a region in which elements 51 are not formed.

Figure 3 is a schematic plan view of element 51 formed in active region A1. Insulator layer 60 and electrode pad 70 are omitted from Figure 3. Figure 4 is a schematic cross-sectional view of element 51, taken along line 4-4 in Figure 3. In one example, element 51 may be a HEMT using GaN. Below, the cross-sectional structure of element 51 will be described with reference to Figure 4, and then the planar structure of element 51 will be described with reference to Figure 3.

As shown in FIG. 4, the element 51 includes a semiconductor substrate 12 and a nitride semiconductor layer 50 formed on the semiconductor substrate 12. The nitride semiconductor layer 50 includes a buffer layer 14 formed on the semiconductor substrate 12, an electron transit layer 16 formed on the buffer layer 14, and an electron supply layer 18 formed on the electron transit layer 16.

The buffer layer 14 is formed on the substrate upper surface 12A of the semiconductor substrate 12. The buffer layer 14 may be located between the semiconductor substrate 12 and the electron transit layer 16. In one example, the buffer layer 14 may be made of any material that can facilitate epitaxial growth of the electron transit layer 16. The buffer layer 14 may include one or more nitride semiconductor layers.

In one example, the buffer layer 14 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN/GaN superlattice structure, a layer having an AlN/AlGaN superlattice structure, or a layer having an AlN/GaN superlattice structure. In order to suppress leakage current in the buffer layer 14, impurities may be introduced into a portion of the buffer layer 14 to make the buffer layer 14 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the concentration of the impurity may be, for example, 4×10 ¹⁶ cm ⁻³ or more.

The electron travel layer 16 is made of a nitride semiconductor. The electron travel layer 16 is, for example, a GaN layer. The thickness of the electron travel layer 16 is, for example, 0.5 μm or more and 2 μm or less. In order to suppress leakage current in the electron travel layer 16, an impurity may be introduced into a part of the electron travel layer 16 to make the electron travel layer 16 semi-insulating except for the surface layer region. In this case, the impurity is, for example, C, and the peak concentration of the impurity in the electron travel layer 16 is, for example, 1×10 ¹⁹ cm ⁻³ or more.

The electron supply layer 18 is made of a nitride semiconductor having a larger band gap than the electron transit layer 16. The electron supply layer 18 is, for example, an AlGaN layer. In this case, the larger the Al composition, the larger the band gap, so the electron supply layer 18, which is an AlGaN layer, has a larger band gap than the electron transit layer 16, which is a GaN layer. In one example, the electron supply layer 18 is made of Al _x Ga _1-x N, where x is 0.1<x<0.4, and more preferably 0.2<x<0.3. The thickness of the electron supply layer 18 is, for example, 5 nm or more and 20 nm or less.

The electron transit layer 16 and the electron supply layer 18 are made of nitride semiconductors having different lattice constants. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transit layer 16 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 18 form a heterojunction of a lattice mismatch system. The energy level of the conduction band of the electron transit layer 16 near the heterojunction interface is lower than the Fermi level due to spontaneous polarization of the electron transit layer 16 and the electron supply layer 18 and piezoelectric polarization caused by stress applied to the electron supply layer 18 near the heterojunction interface. As a result, a two-dimensional electron gas (2DEG) 20 spreads in the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 (for example, within a range of about several nm from the interface).

The element 51 further includes a gate layer 22 formed on the electron supply layer 18, a gate electrode 24 formed on the gate layer 22, and a passivation layer 26. The passivation layer 26 is formed on the electron supply layer 18, the gate layer 22, and the gate electrode 24, and includes a first opening 26A and a second opening 26B. The element 51 further includes a source electrode 28 that contacts the upper surface 18A of the electron supply layer 18 through the first opening 26A, and a drain electrode 30 that contacts the upper surface 18A of the electron supply layer 18 through the second opening 26B.

The gate layer 22 is located between the first opening 26A and the second opening 26B of the passivation layer 26, and is spaced apart from each of the first opening 26A and the second opening 26B. The gate layer 22 is located closer to the first opening 26A than to the second opening 26B. The detailed structure of the gate layer 22 will be described later.

The gate layer 22 has a smaller band gap than the electron supply layer 18 and is composed of a nitride semiconductor containing acceptor-type impurities. The gate layer 22 can be composed of any material that has a smaller band gap than the electron supply layer 18, which is, for example, an AlGaN layer. In one example, the gate layer 22 is a GaN layer doped with acceptor-type impurities (a p-type GaN layer).

The acceptor-type impurities may include at least one of magnesium (Mg), zinc (Zn), and C. One example of the acceptor-type impurity is Mg. The maximum concentration of the acceptor-type impurities in the gate layer 22 is, for example, 1×10 ¹⁸ cm ⁻³ or more, or 1×10 ¹⁹ cm ⁻³ or more. The maximum concentration of the acceptor-type impurities in the gate layer 22 is, for example, 1×10 ²⁰ cm ⁻³ or less.

As described above, the energy levels of the electron transit layer 16 and the electron supply layer 18 are raised by including acceptor-type impurities in the gate layer 22. Therefore, in the region directly below the gate layer 22, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. Therefore, at zero bias when no voltage is applied to the gate electrode 24, 2DEG 20 is not formed in the electron transit layer 16 in the region directly below the gate layer 22. On the other hand, 2DEG 20 is formed in the electron transit layer 16 in regions other than the region directly below the gate layer 22.

In this way, the presence of the gate layer 22 doped with acceptor-type impurities causes the 2DEG 20 to disappear in the region directly below the gate layer 22. As a result, the transistor operates normally off. When an appropriate on-voltage is applied to the gate electrode 24, a channel is formed by the 2DEG 20 in the electron transit layer 16 in the region directly below the gate electrode 24, providing electrical continuity between the source and drain.

The gate electrode 24 is composed of one or more metal layers. In one example, the gate electrode 24 is a titanium nitride (TiN) layer. Alternatively, the gate electrode 24 may be composed of a first metal layer formed of a material containing Ti and a second metal layer formed of a material containing TiN and stacked on the first metal layer. The gate electrode 24 can form a Schottky junction with the gate layer 22. The gate electrode 24 can be formed in an area smaller than the gate layer 22 in a plan view. The thickness of the gate electrode 24 is, for example, 50 nm or more and 200 nm or less.

The passivation layer 26 is formed on the electron supply layer 18. It can be said that the passivation layer 26 covers the upper surface 18A of the electron supply layer 18. The passivation layer 26 can be made of a material containing any one of silicon nitride (SiN), silicon dioxide (SiO ₂ ), silicon oxynitride (SiON), alumina (Al ₂ O ₃ ), AlN, and aluminum oxynitride (AlON). In one example, the passivation layer 26 is made of a material containing SiN. The portion of the passivation layer 26 covering the gate layer 22 and the gate electrode 24 has a non-flat surface because it is formed along the surfaces of the gate layer 22 and the gate electrode 24. The passivation layer 26 has a thickness of, for example, 200 nm or less. Here, the thickness of the passivation layer 26 may be, for example, the thickness of the portion in contact with the electron supply layer 18, or the thickness of the portion in contact with the upper surface of the gate electrode 24.

The source electrode 28 and the drain electrode 30 are arranged on the upper surface 18A of the electron supply layer 18 so as to sandwich the gate layer 22. In the following, on the upper surface 18A of the electron supply layer 18, the gate layer 22, the source electrode 28, and the drain electrode 30 are aligned in the X-axis direction.

The source electrode 28 and the drain electrode 30 may be composed of one or more metal layers. For example, the source electrode 28 and the drain electrode 30 may be composed of a combination of two or more metal layers selected from a group including a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. At least a portion of the source electrode 28 is filled in the first opening 26A and is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the first opening 26A. Similarly, at least a portion of the drain electrode 30 is filled in the second opening 26B and is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the second opening 26B.

In one example, the source electrode 28 may include a source contact portion 28A filled in the first opening 26A and a source field plate portion 28B formed on the passivation layer 26. The source field plate portion 28B is continuous with the source contact portion 28A and is formed integrally with the source contact portion 28A. The source field plate portion 28B includes an end portion 28C located between the second opening portion 26B and the gate layer 22 in a plan view. The source field plate portion 28B is spaced apart from the drain electrode 30. The source field plate portion 28B plays a role in mitigating electric field concentration near the end portion of the gate electrode 24 and near the end portion of the gate layer 22 when a drain voltage is applied to the drain electrode 30 in a zero bias state in which no gate voltage is applied to the gate electrode 24.

As described above, the source electrode 28 is electrically connected to the source pad 71 via a wiring (not shown) formed in the insulator layer 60. The drain electrode 30 is electrically connected to the drain pad 72 via a wiring (not shown) formed in the insulator layer 60. The gate electrode 24 is electrically connected to the gate pad 73 via a wiring (not shown) formed in the insulator layer 60. The insulator layer 60 is formed on the passivation layer 26, the source electrode 28, and the drain electrode 30. It can be said that the insulator layer 60 covers the passivation layer 26, the source electrode 28, and the drain electrode 30.

(Planar structure of element)
Next, the planar structure of the element 51 will be described with reference to Fig. 3. In Fig. 3, the passivation layer 26 and the source electrode 28 are omitted, and the first opening 26A and the second opening 26B of the passivation layer 26 and the end 28C of the source electrode 28 are depicted by dashed lines.

The element 51 has, within the active area A1, a first active area that contributes to the transistor operation and a second active area (not shown) that does not contribute to the transistor operation. In one example, the first active area and the second active area are arranged alternately in the Y-axis direction.

In the first active region of the element 51, the source electrode 28 (see FIG. 4), the gate electrode 24, and the drain electrode 30 are arranged adjacent to each other in the X-axis direction on the electron supply layer 18 (see FIG. 4). A combination of the source electrode 28, the gate electrode 24, and the drain electrode 30 adjacent to each other in the X-axis direction constitutes one HEMT cell 51HC. In the example of FIG. 3, two HEMT cells 51HC are arranged in the X-direction in the active region. Note that in practice, more HEMT cells 51HC may be arranged in each active region.

(Detailed structure of the gate layer)
An example of the gate layer 22 has a step structure. The gate layer 22 having the step structure will be described in detail below with reference to FIG.

As shown in FIG. 4, the gate layer 22 includes a ridge portion 42 and an extension portion 43 that is thinner than the ridge portion 42. The extension portion 43 extends in the X-axis direction from each of the side surfaces 42C of the ridge portion 42 in the X-axis direction.

The ridge portion 42 corresponds to a relatively thick portion of the gate layer 22. The gate electrode 24 is in contact with the ridge portion 42. The ridge portion 42 may have a rectangular or trapezoidal shape in a cross section along the XZ plane in FIG. 4. The ridge portion 42 may have a thickness T4 of, for example, 100 nm or more and 200 nm or less. The thickness T4 of the ridge portion 42 refers to the distance from the upper surface 42A to the lower surface 42B of the ridge portion 42. The thickness T4 of the ridge portion 42 may be determined taking into account various parameters such as the gate breakdown voltage.

The extension portion 43 includes a source side extension portion 44 and a drain side extension portion 46. The source side extension portion 44 and the drain side extension portion 46 extend in opposite directions in the X-axis direction. In detail, the source side extension portion 44 extends from the ridge portion 42 toward the first opening 26A of the passivation layer 26. The drain side extension portion 46 extends from the ridge portion 42 toward the second opening 26B of the passivation layer 26. The source side extension portion 44 and the drain side extension portion 46 may have the same length or may have different lengths.

The thickness T5 of each of the extensions 43 is, for example, 30 nm or less, 25 nm or less, 20 nm or less, or 15 nm or less. The thickness T5 of the extensions 43 is, for example, 5 nm or more. In one example, the thickness T5A of the source side extension 44 and the thickness T5B of the drain side extension 46 are equal to each other. Here, if the difference between the thickness T5A of the source side extension 44 and the thickness T5B of the drain side extension 46 is, for example, within 10% of the thickness of the source side extension 44, it can be said that the thickness T5A of the source side extension 44 and the thickness T5B of the drain side extension 46 are equal to each other.

The source side extension 44 may have a length L1 of, for example, 100 nm or more in the direction from the ridge 42 toward the first opening 26A. The length L1 of the source side extension 44 is, for example, 200 nm or more and 300 nm or less. The drain side extension 46 may have a length L2 of, for example, 200 nm or more and 600 nm or less in the direction from the ridge 42 toward the second opening 26B. In one example, the length L2 of the drain side extension 46 is longer than the length L1 of the source side extension 44.

The gate layer 22 has an upper surface and a lower surface. The lower surface of the gate layer 22 is the surface of the gate layer 22 that faces the upper surface 18A of the electron supply layer 18. The upper surface of the gate layer 22 is the surface of the gate layer 22 that is located opposite the lower surface. The upper surface of the gate layer 22 having a step structure means a surface that includes the upper surface 42A of the ridge portion 42 and the upper surface of the extension portion 43 (the upper surface 44A of the source side extension portion 44 and the upper surface 46A of the drain side extension portion 46). The lower surface of the gate layer 22 having a step structure means a surface that includes the lower surface 42B of the ridge portion 42, the lower surface 44B of the source side extension portion 44, and the lower surface 46B of the drain side extension portion 46.

The cross-sectional shape of the gate layer 22 having a step structure is not limited to the above shape. For example, the thickness T5 of the source side extension portion 44 and the thickness T5 of the drain side extension portion 46 may be different. In addition, either one of the source side extension portion 44 and the drain side extension portion 46 may be omitted, or both the source side extension portion 44 and the drain side extension portion 46 may be omitted.

[Detailed structure of semiconductor substrate]
Next, a detailed structure of the semiconductor substrate 12 will be described with reference to Figures 2 and 5. Figure 5 is a schematic plan view showing the substrate lower surface 12B of the semiconductor substrate 12.

As shown in Figures 2 and 5, the semiconductor substrate 12 includes a substrate upper surface 12A and a substrate lower surface 12B. Furthermore, the semiconductor substrate 12 includes outer peripheral edges 12C to 12F that connect the substrate upper surface 12A and the substrate lower surface 12B. The shape of the semiconductor substrate 12 in a plan view is rectangular. In other words, the shapes of the substrate upper surface 12A and the substrate lower surface 12B are rectangular with the outer peripheral edges 12C and 12D extending in the X-axis direction (first direction) and the outer peripheral edges 12E and 12F extending in the Y-axis direction (second direction perpendicular to the first direction).

The semiconductor substrate 12 includes a thin portion 81 that is relatively thin, and a thick portion 82 that is relatively thick. In a plan view, the thick portion 82 is disposed between the thin portion 81 and the outer periphery 12C to 12F of the semiconductor substrate 12. Specifically, the thick portion 82 is disposed between the thin portion 81 and the outer periphery 12C of the semiconductor substrate 12, between the thin portion 81 and the outer periphery 12D of the semiconductor substrate 12, between the thin portion 81 and the outer periphery 12E of the semiconductor substrate 12, and between the thin portion 81 and the outer periphery 12F of the semiconductor substrate 12. In a plan view, the thick portion 82 can be said to be disposed in a rectangular frame shape surrounding the thin portion 81.

The thin portion 81 and the thick portion 82 are formed by providing one recess 83 in the substrate lower surface 12B of the flat semiconductor substrate 12. In the semiconductor substrate 12, the recess 83 opens to the substrate lower surface 12B side and is recessed from the substrate lower surface 12B side toward the substrate upper surface 12A side. The recess 83 includes a recess bottom surface 83A and a recess side surface 83B that connects the recess bottom surface 83A and the substrate lower surface 12B. The recess bottom surface 83A is, for example, a surface perpendicular to the thickness direction (Z-axis direction) of the semiconductor substrate 12, and the recess side surface 83B is, for example, a surface parallel to the thickness direction of the semiconductor substrate 12.

In plan view, the thin-walled portion 81 has a rectangular shape extending in the X-axis direction and the Y-axis direction. In other words, the recess bottom surface 83A of the recess 83 has a rectangular shape extending in the X-axis direction and the Y-axis direction. One example of the plan view shape of the thin-walled portion 81 is a shape similar to the substrate underside 12B of the semiconductor substrate 12. In plan view, the area ratio of the thin-walled portion 81 to the entire area of the substrate underside 12B is, for example, 10% or more. The above area ratio is, for example, 40% or less, and preferably 34% or less.

At least a portion of the recess 83 is disposed in a position that overlaps with the active region A1 in a plan view. In other words, at least a portion of the recess 83 is disposed directly below the active region A1. In the example of the recess 83 shown in Figures 2 and 5, the entire recess 83 overlaps with the active region A1.

The thick portion 82 has a width W. The width W of the thick portion 82 means the distance between the thin portion 81 and the outer periphery 12C to 12F of the semiconductor substrate 12 in a plan view. The width W of the thick portion 82 is, for example, 50 μm or more, and preferably 200 μm or more. The width W of the thick portion 82 is, for example, 600 μm or less, and preferably 350 μm or less. The width W of the thick portion 82 may be constant or may vary from portion to portion. If the width W of the thick portion 82 varies from portion to portion, it is preferable that the width W at the narrowest portion of the thick portion 82 is 50 μm or more.

Next, the thickness T1 of the thin portion 81 and the thickness T2 of the thick portion 82 will be described.
2, the thickness T1 of the thin portion 81 means the distance between the substrate upper surface 12A of the semiconductor substrate 12 and the bottom surface 83A of the recess. The thickness T1 of the thin portion 81 is, for example, 250 μm or less, 200 μm or less, or 50 μm or less. The thickness T1 of the thin portion 81 is, for example, 50 μm or more, or 200 μm or more. The thickness T1 of the thin portion 81 may be constant or may vary from portion to portion.

The thickness T2 of the thick portion 82 means the distance between the substrate upper surface 12A and the substrate lower surface 12B of the semiconductor substrate 12. The thickness T2 of the thick portion 82 is, for example, 500 μm or less, or 250 μm or less. The thickness T2 of the thick portion 82 is, for example, 150 μm or more, or 250 μm or more. The ratio (T2/T1) of the thickness T2 of the thick portion 82 to the thickness T1 of the thin portion 81 is, for example, 1.25 or more and 10.0 or less, and preferably 2.5 or more and 5.0 or less. The thickness T2 of the thick portion 82 may be constant or may vary from portion to portion.

Here, the nitride semiconductor layer 50 is thinner than the semiconductor substrate 12. That is, the thickness T3 of the nitride semiconductor layer 50 is thinner than the thickness T2 of the thick portion 82 and thinner than the thickness T1 of the thin portion 81. The ratio (T3/T1) of the thickness T3 of the nitride semiconductor layer 50 to the thickness T1 of the thin portion 81 is, for example, 0.2 or less, and preferably 0.028 or less. The ratio (T3/T1) is, for example, 0.014 or more. The ratio (T3/T2) of the thickness T3 of the nitride semiconductor layer 50 to the thickness T2 of the thick portion 82 is, for example, 0.0056 or more and 0.05 or less. The ratio (T2/T3) of the thickness T2 of the thick portion 82 to the thickness T3 of the nitride semiconductor layer 50 is, for example, 20 or more and 180 or less.

[Semiconductor module and mounting structure]
FIG. 6 is a schematic cross-sectional view showing an exemplary mounting structure of a semiconductor module 100 including the nitride semiconductor device 10. As shown in FIG.

The semiconductor module 100 includes a nitride semiconductor device 10 and a heat dissipation member 101. The heat dissipation member 101 is attached to the chip back surface 10r of the nitride semiconductor device 10, i.e., the substrate lower surface 12B of the semiconductor substrate 12, using a bonding material 102. The heat dissipation member 101 is, for example, a heat dissipation fin. The heat dissipation member 101 is formed of a material with good thermal conductivity. The heat dissipation member 101 is, for example, composed of ceramics and metal. The ceramics contains, for example, alumina (Al ₂ O ₃ ) as a main component. The bonding material 102 may be a metal material such as solder or silver (Ag) paste, or a resin-based material such as a thermosetting resin or a photocurable resin. At least a part of the heat dissipation member 101 is in contact with the portion (recess bottom surface 83A) of the substrate lower surface 12B where the thin-walled portion 81 is located, directly or via the bonding material 102.

The semiconductor module 100 is mounted on the mounting substrate 90 by connecting each bonding ball 74 of each electrode pad 70 to a pad portion (not shown) of the mounting substrate 90 with the chip surface 10s of the nitride semiconductor device 10 facing the mounting substrate 90. The mounting substrate 90 is, for example, a printed wiring board. Note that instead of mounting in the state of the semiconductor module 100, the nitride semiconductor device 10 may be mounted on the mounting substrate 90, and then a heat dissipation member 101 may be attached to the chip back surface 10r of the nitride semiconductor device 10 mounted on the mounting substrate 90.

[Action]
Next, the operation of the nitride semiconductor device 10 of the embodiment will be described.
The nitride semiconductor device 10 configured as a chip size package includes a semiconductor substrate 12 having a substrate upper surface 12A and a substrate lower surface 12B, a nitride semiconductor layer 50, an insulator layer 60, and electrode pads formed on the substrate upper surface 12A, and an element 51 configured using the nitride semiconductor layer 50. In this nitride semiconductor device 10, heat generated from the element 51 is dissipated through a heat dissipation path that dissipates heat from the chip rear surface 10r (substrate lower surface 12B of the semiconductor substrate 12) through the semiconductor substrate 12. In the semiconductor substrate 12, the central portion of the semiconductor substrate 12 in a plan view is mainly used as the heat dissipation path. Therefore, the heat distribution in the semiconductor substrate 12 when the element 51 generates heat is such that the temperature is highest in the central portion in a plan view, and the temperature gradually decreases toward the outer periphery.

Here, the semiconductor substrate 12 used in the nitride semiconductor device 10 includes a thin portion 81 that is relatively thin and a thick portion 82 that is relatively thick. In a plan view, the thick portion 82 is disposed between the thin portion 81 and the outer periphery 12C-12F of the semiconductor substrate 12. In other words, the portion of the semiconductor substrate 12 located at the center, which is a portion that contributes greatly to the heat dissipation path, is formed relatively thin, while the portion located on the outer periphery, which is a portion that does not contribute much to the heat dissipation path, is formed relatively thick. This makes it possible to ensure the strength of the semiconductor substrate 12 while improving the heat dissipation through the semiconductor substrate 12.

In other words, by forming the central portion, which is a portion that contributes greatly to the heat dissipation path, relatively thin, the thermal resistance caused by the semiconductor substrate 12 in the heat dissipation path can be greatly reduced. As a result, the heat dissipation in the heat dissipation path is greatly improved. On the other hand, by forming the thick portion 82 in the portion located on the outer periphery of the semiconductor substrate 12, the strength of the semiconductor substrate 12 can be ensured. As described above, the portion located on the outer periphery of the semiconductor substrate 12 does not contribute much to the heat dissipation path, so even if it is formed thick, the effect on the heat dissipation through the semiconductor substrate 12 is small. Therefore, forming the portion located on the outer periphery of the semiconductor substrate 12 thick does not reduce the heat dissipation through the semiconductor substrate 12. In this way, according to the configuration of the nitride semiconductor device 10 using the semiconductor substrate 12 including the thin portion 81 and the thick portion 82, the heat dissipation through the semiconductor substrate 12 can be improved while ensuring the strength of the semiconductor substrate 12.

[effect]
According to the nitride semiconductor device 10 of the embodiment, the following effects can be obtained.
(1) The nitride semiconductor device 10 includes a semiconductor substrate 12 having a substrate upper surface 12A and a substrate lower surface 12B, a nitride semiconductor layer 50 formed on the substrate upper surface 12A and thinner than the semiconductor substrate 12, an element 51 configured using the nitride semiconductor layer 50, an insulator layer 60 formed on the nitride semiconductor layer 50, and an electrode pad 70 formed on the insulator layer 60 and electrically connected to the element 51. The semiconductor substrate 12 includes a thin portion 81 having a relatively small thickness and a thick portion 82 having a relatively large thickness. In a plan view, the thick portion 82 is disposed between the thin portion 81 and the outer periphery 12C to 12F of the semiconductor substrate 12. This configuration can improve heat dissipation through the semiconductor substrate 12 while ensuring the strength of the semiconductor substrate 12.

(2) The ratio (T2/T1) of the thickness T2 of the thick portion 82 to the thickness T1 of the thin portion 81 is 1.25 or more and 10.0 or less. When the ratio (T2/T1) is 1.25 or more, the effect of the thick portion 82 in increasing the strength of the semiconductor substrate 12 is improved. When the ratio (T2/T1) is 10.0 or less, the thin portion 81 has a significant effect of increasing the heat dissipation of the semiconductor substrate 12.

(3) In a plan view, the semiconductor substrate 12 has a rectangular shape extending in a first direction (X-axis direction) and a second direction (Y-axis direction) perpendicular to the first direction (X-axis direction). The thick portions 82 are disposed both between the thin portions 81 and the outer peripheral edge 12C on one side in the first direction (X-axis direction) and between the thin portions 81 and the outer peripheral edge (12D) on the other side in the first direction (X-axis direction). With this configuration, the thick portions 82 are provided on both sides in the first direction (X-axis direction), thereby improving the effect of increasing the strength of the semiconductor substrate 12 by the thick portions 82.

(4) The thick portions 82 are disposed both between the thin portions 81 and the outer peripheral edge 12E on one side in the second direction (Y-axis direction) and between the thin portions 81 and the outer peripheral edge 12F on the other side in the second direction (Y-axis direction). With this configuration, the thick portions 82 are provided on both sides in the first direction (X-axis direction) and on both sides in the second direction (Y-axis direction), which further improves the effect of increasing the strength of the semiconductor substrate 12 by the thick portions 82.

(5) The ratio (T2/T3) of the thickness T2 of the thick portion 82 to the thickness T3 of the nitride semiconductor layer 50 is 20 or more. This configuration means that the nitride semiconductor layer 50 is formed very thinly with respect to the semiconductor substrate 12. In this case, the proportion of the semiconductor substrate 12 in the heat dissipation path in which heat generated from the element 51 is dissipated from the substrate lower surface 12B of the semiconductor substrate 12 through the semiconductor substrate 12 increases. Therefore, the effect of increasing the heat dissipation property of the semiconductor substrate 12 described above in (1) is more pronounced.

(6) In a plan view, the nitride semiconductor device 10 includes an active region A1 located in the center of the semiconductor substrate 12 and in which the elements 51 are formed, and a frame-shaped peripheral region A2 located on the outer periphery of the semiconductor substrate 12 and surrounding the active region A1. At least a portion of the thin portion 81 overlaps with the active region A1 in a plan view. The portion of the semiconductor substrate 12 that overlaps with the active region A1 is a portion through which heat from the elements 51 provided in the active region A1 is easily transferred. Therefore, by providing the thin portion 81 in this portion, the effect of improving the heat dissipation of the semiconductor substrate 12 described above in (1) can be more significantly achieved.

<Example of change>
The above embodiment can be modified, for example, as follows. The above embodiment and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, the same reference numerals as in the above embodiment are used for the parts common to the above embodiment, and the description thereof will be omitted.

- In the above embodiment, the element 51 is configured as a normally-off type HEMT, but the configuration of the present disclosure is not limited to normally-off type HEMTs and can also be applied to normally-on type HEMTs. For example, the element 51 can be configured as a normally-on type HEMT by omitting the gate layer 22 from the element 51 or by forming the gate layer 22 as a nitride semiconductor layer that does not contain acceptor-type impurities.

- In the above embodiment, the element 51 of the nitride semiconductor device 10 is configured as a nitride semiconductor HEMT, but is not limited to a nitride semiconductor HEMT and may be configured as a nitride semiconductor diode.

- The shape of the thin-walled portion 81 provided on the semiconductor substrate 12 is not limited to a rectangular shape, and can be any shape. For example, the planar shape of the thin-walled portion 81 may be a circle, an ellipse, or a polygon. In addition, the number of thin-walled portions 81 provided on the semiconductor substrate 12 is not particularly limited, and may be more than one.

Figures 7 and 8 are schematic plan views showing the substrate underside 12B of a modified semiconductor substrate 12 in which multiple thin-walled portions 81 are provided. In the modified example shown in Figure 7, four thin-walled portions 81 that are rectangular in plan view are arranged in a 2 x 2 pattern. As shown in Figure 7, the thin-walled portion 81 does not have to be located at the center of the semiconductor substrate 12 in plan view. In addition, in the modified example shown in Figure 8, multiple thin-walled portions 81 that are circular in plan view are provided. These multiple thin-walled portions 81 include those with relatively large diameters and those with small diameters, and are arranged such that the diameter of the thin-walled portions 81 decreases from the center of the semiconductor substrate 12 toward the outer periphery 12C to 12F.

Also, as shown in FIG. 9, the thin-walled portion 81 may have a shape in which the thickness T1 gradually increases from the center of the semiconductor substrate 12 toward the outer periphery 12C-12F. In the example shown in FIG. 9, the thin-walled portion 81 of the above shape is realized by forming the recess side surface 83B of the recess 83 in a stepped shape.

As shown in FIG. 10, the thin portion 81 may have a portion that contacts the outer peripheral edges 12C to 12F of the semiconductor substrate 12 in a plan view. In the example shown in FIG. 10, the thin portion 81 is shaped to contact the outer peripheral edge 12E on one side in the Y-axis direction (second direction) and the outer peripheral edge 12F on the other side in the Y-axis direction (second direction) in a plan view. In this case, the thick portion 82 is formed between the thin portion 81 and the outer peripheral edge 12C on one side in the X-axis direction, and between the thin portion 81 and the outer peripheral edge 12D on the other side in the X-axis direction, in a plan view. On the other hand, the thick portion 82 is not formed between the thin portion 81 and the outer peripheral edge 12E on one side in the Y-axis direction, and between the thin portion 81 and the outer peripheral edge 12F on the other side in the Y-axis direction.

- Figure 11 is a schematic plan view of the substrate underside 12B (chip backside 10r) of a modified nitride semiconductor device 10. Figure 12 is a cross-sectional view taken along line 12-12 of Figure 11. The nitride semiconductor device 10 shown in Figures 11 and 12 includes a plurality of element regions 52 provided at different positions in a plan view within the active region A1. The plurality of element regions 52 are regions in which elements 51 are formed. The elements 51 formed in each of the element regions 52 may be the same or different. The number, arrangement and shape of the element regions 52 are arbitrary and are not limited to a specific number, arrangement and shape.

Among the multiple element regions 52, the region that is likely to become hot due to heat generation from the element 51 is the high temperature element region 52A. The high temperature element region 52A may be one or more. FIGS. 11 and 12 show a case where there is one high temperature element region 52A. The semiconductor substrate 12 of the nitride semiconductor device 10 has a thin portion 81 and a thick portion 82 as in the above embodiment. The thin portion 81 is arranged at a position where at least a part of it overlaps the high temperature element region 52A in a plan view. The portion of the semiconductor substrate 12 that does not overlap the high temperature element region 52A is formed as the thick portion 82. In this way, in a configuration having an element region 52, the thin portion 81 may be arranged only in the element region 52 that needs to have high heat dissipation. In this case, the range in which the thin portion 81 is provided is greatly limited, so that the decrease in strength of the semiconductor substrate 12 caused by providing the thin portion 81 can be suppressed.

The term "on" as used in this disclosure includes both the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, the expression "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be placed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be placed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, the various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this specification being "up" and "down" of the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

The terms "first", "second", "third", etc. in this disclosure are used merely to distinguish objects and do not rank the objects.
<Additional Notes>
The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples for the purpose of aiding understanding, and the components described in each appendix should not be limited to the components indicated by the reference symbols.

[Appendix 1]
a semiconductor substrate (12) having a substrate upper surface (12A) and a substrate lower surface (12B) facing in a direction opposite to the substrate upper surface (12A);
a nitride semiconductor layer (50) formed on the substrate upper surface (12A) and thinner than the semiconductor substrate (12);
An element (51) constructed using the nitride semiconductor layer (50);
an insulator layer (60) formed on the nitride semiconductor layer (50);
an electrode pad (70) formed on the insulator layer (60) and electrically connected to the element (51);
Including,
The semiconductor substrate (12) includes a thin portion (81) having a relatively small thickness and a thick portion (82) having a relatively large thickness,
In a plan view seen in the thickness direction of the semiconductor substrate (12),
The thick portion (82) is disposed between the thin portion (81) and an outer periphery (12C to 12F) of the semiconductor substrate (12).

[Appendix 2]
2. The nitride semiconductor device (10) according to claim 1, wherein a ratio (T2/T1) of a thickness (T2) of the thick portion (82) to a thickness (T1) of the thin portion (81) is 0.1 or more and 0.8 or less.

[Appendix 3]
The thickness (T1) of the thin portion is 50 μm or more and 200 μm or less,
The nitride semiconductor device (10) according to claim 1 or 2, wherein a thickness (T2) of the thick portion is 250 μm or more and 500 μm or less.

[Appendix 4]
The nitride semiconductor device (10) according to any one of appendices 1 to 3, wherein the thin portion (81) is formed by a recess (83) provided in the lower surface (12B) of the substrate.

[Appendix 5]
The semiconductor substrate (12) has a rectangular shape extending in a first direction (X-axis direction) and a second direction (Y-axis direction) perpendicular to the first direction (X-axis direction) in a plan view;
The nitride semiconductor device (10) according to any one of Appendices 1 to 4, wherein the thick portion (82) is arranged both between the thin portion (81) and an outer peripheral edge (12C) on one side in the first direction (X-axis direction) and between the thin portion (81) and an outer peripheral edge (12D) on the other side in the first direction (X-axis direction).

[Appendix 6]
The nitride semiconductor device (10) described in Appendix 5, wherein the thick portion (82) is arranged both between the thin portion (81) and an outer peripheral edge (12E) on one side in the second direction (Y-axis direction) and between the thin portion (81) and an outer peripheral edge (12F) on the other side in the second direction (Y-axis direction).

[Appendix 7]
The nitride semiconductor device (10) according to any one of Appendices 1 to 6, wherein a ratio (T2/T3) of a thickness (T2) of the thick portion (82) to a thickness (T3) of the nitride semiconductor layer (50) is 20 or more and 180 or less.

[Appendix 8]
In a plan view, the semiconductor substrate includes an active region (A1) located in a central portion of the semiconductor substrate (12) and in which the element (51) is formed, and a frame-shaped peripheral region (A2) located on the outer periphery of the semiconductor substrate (12) and surrounding the active region (A1);
The nitride semiconductor device (10) according to any one of appendices 1 to 7, wherein at least a portion of the thin portion (81) overlaps with the active region (A1) in a plan view.

[Appendix 9]
The device includes a plurality of element regions (52) in which the elements (51) are formed,
The nitride semiconductor device (10) according to any one of claims 1 to 8, wherein the thin portion (82) overlaps with at least one of the element regions (52) in a plan view.

[Appendix 10]
The element (51) is
an electron transit layer (16) formed on the semiconductor substrate (12) and made of a nitride semiconductor;
an electron supply layer (18) formed on the electron transit layer (16) and made of a nitride semiconductor having a band gap larger than that of the electron transit layer (16);
a gate layer (22) formed on the electron supply layer (18) and made of a nitride semiconductor containing an acceptor-type impurity;
a gate electrode (24) formed on the gate layer (22);
The nitride semiconductor device (10) according to any one of claims 1 to 9, further comprising a source electrode (28) and a drain electrode (30) formed on the electron supply layer (18).

[Appendix 11]
The nitride semiconductor device (10) according to any one of appendices 1 to 10, wherein the semiconductor substrate (12) is a Si substrate.

[Appendix 12]
The nitride semiconductor device (10) according to any one of appendices 1 to 11, wherein the nitride semiconductor layer is a GaN layer.

[Appendix 13]
A nitride semiconductor device (10) according to any one of appendices 1 to 12;
a heat dissipation member (101) attached to the lower surface (12B) of the semiconductor substrate (12).

A1...active region A2...peripheral region L1, L2...length T1 to T5...thickness T5A...thickness T5B...thickness W...width 10...nitride semiconductor device 10A to 10D...first to fourth chip side surfaces 10HC...HEMT cell 10r...back surface of chip 10s...front surface of chip 11...back surface of chip 12...semiconductor substrate 12A...upper surface of substrate 12B...lower surface of substrate 12C to 12F...periphery 14...buffer layer 16...electron transit layer 18...electron supply layer 18A...upper surface 20...two-dimensional electron gas 22...gate layer 24...gate electrode 26...passivation layer 26A...first opening 26B...second opening 28...source electrode 28A...source contact portion 28B...source field plate portion 28C...end portion 30...drain electrode 42...ridge portion Description of the Related Art 42A...upper surface 42B...lower surface 42C...side surface 43...extension portion 44...source side extension portion 44A...upper surface 44B...lower surface 46...drain side extension portion 46A...upper surface 46B...lower surface 50...nitride semiconductor layer 51...element 51HC...HEMT cell 52...element region 52A...high temperature element region 60...insulator layer 70...electrode pad 71...source pad 72...drain pad 73...gate pad 74...bonding material ball 81...thin portion 82...thick portion 83...recess 83A...recess bottom surface 83B...recess side surface 90...mounting substrate 100...semiconductor module 101...heat dissipation member 102...bonding material

Claims (13)

a semiconductor substrate having a substrate upper surface and a substrate lower surface facing away from the substrate upper surface;
a nitride semiconductor layer formed on an upper surface of the substrate and thinner than the semiconductor substrate;
An element configured using the nitride semiconductor layer;
an insulator layer formed on the nitride semiconductor layer;
an electrode pad formed on the insulating layer and electrically connected to the element;
Including,
the semiconductor substrate includes a thin portion having a relatively small thickness and a thick portion having a relatively large thickness;
In a plan view seen in a thickness direction of the semiconductor substrate,
the thick portion is disposed between the thin portion and an outer periphery of the semiconductor substrate;
Nitride semiconductor devices. The nitride semiconductor device according to claim 1, wherein the ratio (T2/T1) of the thickness (T2) of the thick portion to the thickness (T1) of the thin portion is 0.1 or more and 0.8 or less. The thickness (T1) of the thin portion is 50 μm or more and 200 μm or less,
The nitride semiconductor device according to claim 1 , wherein a thickness (T2) of said thick portion is not less than 250 μm and not more than 500 μm. The nitride semiconductor device according to claim 1, wherein the thin portion is formed by a recess provided on the lower surface of the substrate. the semiconductor substrate has a rectangular shape extending in a first direction and a second direction perpendicular to the first direction in a plan view;
2 . The nitride semiconductor device according to claim 1 , wherein the thick portion is disposed both between the thin portion and an outer circumferential edge on one side in the first direction and between the thin portion and an outer circumferential edge on the other side in the first direction. The nitride semiconductor device according to claim 5, wherein the thick portion is disposed both between the thin portion and the outer periphery on one side in the second direction and between the thin portion and the outer periphery on the other side in the second direction. The nitride semiconductor device according to claim 1, wherein the ratio (T2/T3) of the thickness (T2) of the thick portion to the thickness (T3) of the nitride semiconductor layer is 20 or more and 180 or less. an active region located in a central portion of the semiconductor substrate in a plan view and in which the element is formed, and a frame-shaped peripheral region located on an outer periphery of the semiconductor substrate and surrounding the active region;
The nitride semiconductor device according to claim 1 , wherein at least a portion of said thin portion overlaps with said active region in a plan view. a plurality of element regions in which the elements are formed;
The nitride semiconductor device according to claim 1 , wherein said thin portion overlaps at least one of said element regions in a plan view. The element comprises:
an electron transit layer formed on the semiconductor substrate and made of a nitride semiconductor;
an electron supply layer formed on the electron transit layer and made of a nitride semiconductor having a band gap larger than that of the electron transit layer;
a gate layer formed on the electron supply layer and made of a nitride semiconductor containing an acceptor-type impurity;
a gate electrode formed on the gate layer;
The nitride semiconductor device according to claim 1 , further comprising: a source electrode and a drain electrode formed on said electron supply layer. The nitride semiconductor device according to claim 1, wherein the semiconductor substrate is a Si substrate. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor layer is a GaN layer. A nitride semiconductor device according to any one of claims 1 to 12,
a heat dissipation member attached to a lower surface of the semiconductor substrate.

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