JP2024143148A - Surface emitting semiconductor laser element and method for manufacturing the same - Google Patents

Abstract

To provide a manufacturing method of a surface emission semiconductor laser element having a high quality active layer, a lower threshold, and a higher efficiency, and is capable of enhancing a resonance effect by arranging a vacancy layer and an active layer close to each other, and to provide the surface emission semiconductor laser element.SOLUTION: A hole formation preparation layer is formed on a substrate (a), a hole formation layer is formed by forming, on the hole formation preparation layer, holes two-dimensionally arranged at each of lattice points (b), a surface of the hole formation layer is oxidized to form an oxide film and then the oxide film is removed (c), a first embedded layer is formed by performing facet growth for occluding the holes (d), a guide layer containing a vacancy layer having vacancies corresponding to the holes is formed by performing growth of a second embedded layer for flatly embedding the first embedded layer (e), and performs crystal growth of a semiconductor layer containing an active layer on the guide layer (f).SELECTED DRAWING: Figure 3

Description

The present invention relates to a method for manufacturing a surface-emitting semiconductor laser element having a photonic crystal, and to a surface-emitting semiconductor laser element.

In recent years, the development of photonic crystal surface-emitting lasers (PCSELs) using photonic crystals (PCs) has progressed.

For example, Patent Document 1 proposes a method of embedding holes with a hexagonal column structure with side faces consisting of {10-10} in a group III nitride semiconductor layer using facet selective growth in order to enhance the diffraction effect in the hole layer in a photonic crystal laser and obtain a high resonance effect. It describes how this realizes a photonic crystal laser element equipped with a photonic crystal having a large filling factor and a large optical confinement coefficient.

Patent Document 2 also proposes a method for embedding holes in a group III nitride semiconductor layer in a photonic crystal laser using mass transport. It describes how this results in a photonic crystal laser with a large coupling coefficient for light waves propagating through the photonic crystal layer.

Patent Document 3 also discloses that a photonic crystal layer (hole layer) is formed by performing a first embedding growth in which holes are filled by facet growth and a second embedding growth in which the surface is flattened.

Patent No. 7101370 JP 2020-38892 A WO2018/155710 A1 Publication

However, when the method described in Patent Document 1 is used, a void layer with a sufficient void filling rate can be formed, but the layer thickness for embedding the void layer becomes thick, and the distance between the void layer and the active layer cannot be reduced. Therefore, the resonance effect in the void layer cannot be increased.

The inventors of the present application have also found that when voids are filled using mass transport, a large amount of Si is deposited on the surface where the voids are formed, causing significant surface roughness. This surface roughness hinders the growth of a high-quality active layer with high flatness on the filling layer, and also prevents the void layer and the active layer from being brought sufficiently close to each other, making it difficult to increase the coupling efficiency between the void layer and the active layer.
Furthermore, when high concentration Si is introduced into the GaN film, point defects are likely to be introduced into the film, and from this viewpoint as well, it is preferable to remove the large amount of Si deposited on the surface.

For these reasons, in conventional technology, it was difficult to increase the resonance effect and lower the threshold current while maintaining high output.

The present invention aims to provide a manufacturing method and a surface-emitting semiconductor laser element that can increase the resonance effect by bringing the air hole layer and the active layer close to each other, has a high-quality active layer, and has a low threshold and high efficiency.

A method for manufacturing a surface emitting semiconductor laser device according to one embodiment of the present invention includes the steps of:
(a) forming a hole formation preparation layer on a substrate;
(b) forming holes arranged two-dimensionally at each of the lattice points in the hole formation preparation layer to form a hole formation layer;
(c) oxidizing the surface of the hole formation layer to form an oxide film, and then removing the oxide film;
(d) forming a first burying layer by facet growth to close the hole;
(e) growing a second burying layer that buries the first burying layer flatly to form a first guide layer including a hole layer having holes corresponding to the holes;
(f) A manufacturing method comprising: growing crystals of a semiconductor layer including an active layer on the first guide layer.

A method for manufacturing a surface emitting semiconductor laser device according to another embodiment of the present invention includes the steps of:
A method for manufacturing a surface emitting semiconductor laser device, comprising the steps of:
(a) forming a hole formation preparation layer on a substrate;
(b) forming holes arranged two-dimensionally at each of the lattice points in the hole formation preparation layer to form a hole formation layer;
(c) oxidizing the surface of the hole formation layer to form an oxide film, and then removing the oxide film;
(d) forming a first burying layer by facet growth to close the hole;
(e) growing a second burying layer that buries the first burying layer flatly to form a first guide layer including a hole layer having holes corresponding to the holes;
(f) flattening the surface of the first guide layer by annealing in a hydrogen atmosphere;
(g) A manufacturing method comprising: growing crystals of a semiconductor layer including an active layer on the flat etched first guide layer.

A surface emitting semiconductor laser device according to still another embodiment of the present invention comprises:
An n-type semiconductor layer;
a first guide layer including: a hole layer formed on the n-type semiconductor layer, the hole layer having holes arranged two-dimensionally at each lattice point; and a buried layer formed on the hole layer to close the holes;
a semiconductor layer including an active layer formed on the buried layer;
a second guide layer formed on the semiconductor layer including the active layer;
The distance from the upper surface of the hole in the hole layer to the active layer is 4 to 200 nm.

1 is a cross-sectional view showing a schematic example of a structure of a PCSEL element according to a first embodiment. FIG. 1B is an enlarged cross-sectional view showing a schematic diagram of holes arranged in the hole layer shown in FIG. 1A. FIG. 2 is a plan view showing a schematic top surface of a PCSEL element. 2 is a cross-sectional view that illustrates a cross section taken along a plane parallel to an n-side guide layer. FIG. FIG. 2 is a plan view showing a schematic bottom surface of a PCSEL element. 4 is a flowchart showing a method for manufacturing the PCSEL element according to the first embodiment. 3A to 3C are cross-sectional views each showing a schematic cross section of an n-side guide layer in steps S0 to S3 of forming a buried layer. FIG. 2 is a plan view showing a schematic view of main openings and sub-openings in a resist, and main holes and sub-holes after etching. FIG. 2 is a schematic diagram showing a cross section of the formed air hole layer perpendicular to the central axis CX. 1 shows a SIMS profile in the depth direction of a PCSEL element (EMB) manufactured by carrying out a surface oxidation/oxide film removal process (step S1). 1 shows a SIMS profile in the depth direction of a PCSEL element (CMP) manufactured without performing the surface oxidation/oxide film removal process (step S1). FIG. 11 is a cross-sectional view illustrating an example of the structure of a PCSEL element according to a second embodiment. FIG. 9B is an enlarged cross-sectional view showing a schematic diagram of the hole layer of FIG. 9A and holes arranged in the hole layer. 10 is a flowchart showing a method for manufacturing a PCSEL element according to a second embodiment. FIG. 11 is a cross-sectional view that typically shows a cross section of the n-side guide layer in step S3A. 1 is a SEM image showing a cross section of a substrate on which a buried layer is regrown after surface oxidation/oxide film removal processing, the surface of which is etched by H ₂ annealing. 13A to 13D are diagrams showing AFM images of the surfaces of samples (i) to (iv) shown in FIG. 12. 1 is a graph plotting surface roughness Ra in a 20 μm×20 μm area against thickness DE of the buried layer after etching.

In the following, preferred embodiments of the present invention will be described, but these may be modified and combined as appropriate. In the following description and accompanying drawings, substantially the same or equivalent parts are denoted by the same reference numerals.

[First embodiment]
1. Structure of Photonic Crystal Surface-Emitting Laser Element A photonic crystal surface-emitting laser element (PCSEL element) is a surface-emitting semiconductor laser element that has a resonator layer in a direction parallel to the semiconductor light-emitting structure layers (n-side guide layer, light-emitting layer, p-side guide layer) that constitute the light-emitting element, and emits coherent light in a direction perpendicular to the resonator layer.

In other words, in a PCSEL element, light waves propagating in a plane parallel to the air hole layer (photonic crystal layer) are diffracted by the diffraction effect of the photonic crystal to form a two-dimensional resonance mode, and are also diffracted in a direction perpendicular to the parallel plane. In other words, in a PCSEL element, the light extraction direction is perpendicular to the resonance direction (in the plane parallel to the air hole layer).

Figure 1A is a cross-sectional view showing an example of the structure of a photonic crystal surface-emitting laser element (PCSEL element) 10 according to an embodiment of the present invention. Also, Figure 1B is an enlarged cross-sectional view showing an air hole layer 14P and air hole pairs 14K arranged in the air hole layer 14P in Figure 1A.

2A is a plan view showing the top surface of the PCSEL device 10. FIG. 2B is a cross-sectional view showing the cross section of the hole layer 14P in a plane parallel to the n-side guide layer 14, and FIG. 2C is a plan view showing the bottom surface of the PCSEL device 10.

As shown in FIG. 1A, a semiconductor structure layer 11 is formed on a light-transmitting element substrate 12. The semiconductor layers are stacked perpendicular to the central axis CX of the semiconductor structure layer 11.

The semiconductor structure layer 11 is made of a hexagonal nitride semiconductor. In this embodiment, the semiconductor structure layer 11 is made of, for example, a GaN-based semiconductor.

More specifically, a semiconductor structure layer 11 consisting of multiple semiconductor layers is formed on an element substrate 12, in this order: an n-clad layer (first clad layer of a first conductivity type) 13, an n-side guide layer (first guide layer) 14 which is a guide layer provided on the n-side, a light distribution adjustment layer 23, an active layer (ACT) 15, a p-side guide layer (second guide layer) 16 which is a guide layer provided on the p-side, an electron barrier layer (EBL: Electron Blocking Layer) 17, a p-clad layer (second clad layer of a second conductivity type) 18, and a p-contact layer 19.

Note that, although a case will be described in which the first conductivity type is n-type and the second conductivity type, which is the opposite conductivity type to the first conductivity type, is p-type, the first conductivity type and the second conductivity type may also be p-type and n-type, respectively.

The element substrate 12 is a hexagonal GaN single crystal substrate that has a high transmittance for the light emitted from the active layer 15. More specifically, the element substrate 12 is a hexagonal GaN single crystal substrate whose main surface (crystal growth surface) is a +c plane, which is a {0001} plane in which Ga atoms are arranged on the outermost surface. The back surface (light emission surface) is a -c plane, which is a (000-1) plane in which N atoms are arranged on the outermost surface. The -c plane is suitable as a light emission surface because it is resistant to oxidation, etc.

The element substrate 12 is not limited to this, but is preferably a so-called just substrate, or, for example, a substrate whose main surface is offset by about 1° in the m-axis direction. For example, a substrate offset by about 0.3 to 0.7° in the m-axis direction can obtain mirror-finish growth under a wide range of growth conditions.

The back surface of the substrate opposite the main surface is the light emitting surface, which is the "-c" surface, which is the (000-1) surface on which N atoms are arranged. The -c surface is resistant to oxidation and is therefore suitable as a light extraction surface.

The composition, thickness, and other configurations of each semiconductor layer are described below, but these are merely examples and can be modified as appropriate.

The n-cladding layer 13 is, for example, an n-Al _0.04 Ga _0.96 N layer with an Al composition of 4% and a thickness of 2 μm. The aluminum (Al) composition ratio is set so that the refractive index is smaller than that of the layer adjacent to the active layer 15 side (i.e., the n-side guide layer 14).

The n-side guide layer 14 is composed of a lower guide layer 14A, an air-hole layer 14P, which is a photonic crystal layer (PC layer), and a buried layer 14B. As shown in Fig. 1B, the photonic crystal layer 14P has a layer thickness _dPC , and the buried layer 14B has a layer thickness DE. For example, the layer thickness _dPC of the air-hole layer 14P is 40 to 180 nm.

In this specification, the air hole layer 14P refers to a layer portion extending from the upper end to the lower end of the air hole in the n-side guide layer 14 (see FIG. 1B). Therefore, the layer thickness d _PC of the air hole layer 14P is equal to the height of the air hole.

The lower guide layer 14A is, for example, n-GaN with a layer thickness of 100 to 400 nm. The void layer 14P is n-GaN with a layer thickness (or the height of the void 14K) of 40 to 180 nm.

The buried layer 14B is made of n-GaN or n-InGaN, or undoped GaN or undoped InGaN. Alternatively, it may be a layer in which these semiconductor layers are stacked. The layer thickness DE of the buried layer 14B is, for example, 4 to 200 nm. The buried layer 14B is made of a first buried layer 14B1 and a second buried layer 14B2. In other words, the buried layer 14B is a stacked buried layer in which the second buried layer 14B2 is stacked on the first buried layer 14B1.

On the second buried layer 14B2, which is the surface layer of the buried layer 14B, there is provided a light distribution adjustment layer 23, which is a hetero semiconductor layer (a heterogeneous semiconductor layer) that has a different crystal composition from the second buried layer 14B2 and forms a heterostructure with the second buried layer 14B2.

In addition, the light distribution adjustment layer 23 may be a semiconductor layer of the same conductivity type as the second embedded layer 14B2, or at least one of them may be an i-layer (intrinsic semiconductor layer).

The light distribution adjustment layer 23 is provided between the buried layer 14B and the active layer 15, and has a function of adjusting the coupling efficiency between the light propagating in the hole layer 14P and the hole layer 14P serving as a resonator. Alternatively, the light distribution adjustment layer 23 may have a function as a SCH (Separate Confinement Heterostructure) layer used for the active layer of the bulk structure and the quantum well structure.
In this embodiment, the light distribution adjustment layer 23 is an undoped In _0.03 Ga _0.97 N layer, and has a layer thickness of, for example, 50 nm. The composition or refractive index and layer thickness of the light distribution adjustment layer 23 are selected according to adjustment of coupling efficiency.

The n-side semiconductor layer including the n-side guide layer 14 and the light distribution adjustment layer 23 is also referred to as the first semiconductor layer, but the light distribution adjustment layer 23 does not necessarily have to be provided.

The active layer 15, which is the light-emitting layer, is, for example, a multiple quantum well (MQW) layer having two quantum well layers. The barrier layer and quantum well layer of the MQW are GaN (layer thickness 6.0 nm) and InGaN (layer thickness 4.0 nm), respectively. The central emission wavelength of the active layer 15 is 440 nm.

It is preferable that the active layer 15 is located within 180 nm of the air hole layer 14P (i.e., within the period PK of the air holes). In this case, a high resonance effect is obtained by the air hole layer 14P.

The p-side guide layer 16 is composed of a p-side guide layer (1) 16A which is an undoped In _0.02 Ga _0.98 N layer (layer thickness 70 nm) and a p-side guide layer (2) 16B which is an undoped GaN layer (layer thickness 180 nm).

The p-side guide layer 16 is an undoped layer in consideration of the light absorption by the dopant (Mg: magnesium, etc.), but it may be doped to obtain good electrical conductivity. In addition, the In composition and layer thickness of the p-side guide layer (1) 16A can be appropriately selected to adjust the electric field distribution in the oscillation operation mode.

The electron barrier layer (EBL) 17 is a magnesium (Mg)-doped p-type Al _0.2 Ga _0.8 N layer having a thickness of, for example, 15 nm.

The p-cladding layer 18 is an Mg-doped p-Al _0.06 Ga _0.94 N layer, and has a thickness of, for example, 600 nm. The Al composition of the p-cladding layer 18 is preferably selected so that the refractive index is smaller than that of the p-side guide layer 16. The p-cladding layer 18 functions as a first p-cladding layer.

The p-contact layer 19 is a Mg-doped p-GaN layer, and has a thickness of, for example, 20 nm. The carrier density of the p-contact layer 19 is set to a concentration that allows for ohmic junction with the transparent electrode 29, which is a transparent conductive layer provided on the surface of the p-contact layer 19. Instead of p-type GaN, p-type or undoped InGaN may be used. Alternatively, a layer in which a GaN layer and an InGaN layer are stacked may be used.

The layer consisting of the p-side guide layer 16, the electron barrier layer 17, the p-cladding layer 18 and the p-contact layer 19 is also referred to as the second semiconductor layer.

In this specification, "n-side" and "p-side" do not necessarily mean n-type and p-type. For example, the n-side guide layer means a guide layer provided on the n-side of the active layer, and may be an undoped layer (or an i-layer).

The n-cladding layer 13 may be composed of multiple layers rather than a single layer. In that case, all layers do not need to be n-layers (n-doped layers) and may include undoped layers (i-layers). The same applies to the guide layer 16 and p-cladding layer 18.

In addition, it is not necessary to provide all of the semiconductor layers described above, and it is sufficient to have a configuration having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and an active layer (light-emitting layer) sandwiched between these layers.

In addition, in this embodiment, a case where the vacancy layer 14P (photonic crystal layer) is provided in the first semiconductor layer (n-type semiconductor layer) has been described, but the vacancy layer may be provided in the second semiconductor layer (p-type semiconductor layer).

On the p-contact layer 19, a p-electrode 20B (second electrode) is formed as a translucent electrode/Ag/Au layer in which a translucent electrode 29 (not shown), a silver (Ag) layer, and a gold (Au) layer are laminated in this order. In other words, the p-electrode 20B functions as a light reflecting layer, and the interface between the translucent electrode 29 and the Ag layer of the p-electrode 20B is the reflecting surface SR. The reflecting surface SR is provided parallel to the void layer 14P.

The p-electrode 20B has a circular shape with a diameter RA centered on the central axis CX of the void formation region 14R. Specifically, the transparent electrode 29 has a diameter of, for example, RA = 300 μm when viewed from above (i.e., when viewed from a direction perpendicular to the semiconductor structure layer 11). Note that Pd, Al, Al alloys, etc. may also be used as the p-electrode 20B. A pad electrode, etc. may also be provided on the p-electrode 20B.

The transparent electrode 29 is formed of a transparent conductor, for example, indium tin oxide (ITO). Note that the transparent electrode 29 is not limited to ITO, and other transparent conductors such as zinc tin oxide (ZTO), GZO (ZnO:Ga), and AZO (ZnO:Al) can be used.

The side and upper surfaces of the semiconductor structure layer 11 and the side surfaces of the p-electrode 20B are covered with an insulating film 21 such as SiO _2. The insulating film 21 is formed so as to run onto the p-electrode 20B and cover the edge of the upper surface of the p-electrode 20B.

The insulating film 21 also functions as a protective film, protecting the aluminum (Al)-containing crystal layer constituting the PCSEL element 10 from corrosive gases, etc. It also prevents short circuits caused by adhesions or solder creeping up during mounting, contributing to improved reliability and yield. The material of the insulating film 21 is not limited to _SiO2 , but may be _ZrO2 , _HfO2 , _{TiO2 , Al2O3} , SiNx, Si, etc.

A circular cathode electrode 20A (first electrode) is formed on the back surface of the element substrate 12 (see FIG. 2C). In addition, an anti-reflective (AR) coating layer 27 is formed on the inside of the cathode electrode 20A.

The cathode electrode 20A is made of Ti/Au and is in ohmic contact with the element substrate 12. In addition to Ti/Au, the electrode material can be selected from Ti/Al, Ti/Rh, Ti/Al/Pt/Au, Ti/Pt/Au, etc.

The light emitted from the active layer 15 is diffracted by the air hole layer (PC layer) 14P. The light is diffracted by the air hole layer 14P (diffraction surface WS), and the light emitted directly from the air hole layer 14P (direct diffracted light Ld: first diffracted light) and the light emitted by the diffraction of the air hole layer 14P and reflected by the reflection surface SR (reflected diffracted light Lr: second diffracted light) are emitted to the outside from the light emission region 20L (FIG. 2C) of the rear surface (emission surface) 12R of the element substrate 12.

As shown in FIG. 2B, in the void layer 14P, the voids 14K are arranged periodically within, for example, a rectangular void-forming region 14R. As shown in FIG. 2C, the anode region RA is formed so as to be included within the void-forming region 14R.

The cathode electrode 20A is provided as a ring-shaped electrode on the outside of the p-electrode 20B so as not to overlap with the p-electrode 20B when viewed from a direction perpendicular to the void layer 14P.

The area inside the cathode electrode 20A is the light emission area 20L. In addition, a bonding pad 20C is provided that is electrically connected to the cathode electrode 20 and connects a wire for power supply from an external source.

2. Manufacturing method of the void layer and recrystallization growth
The process of fabricating the hole layer and the recrystallization growth are described below. Metalorganic Vapor Phase Epitaxy (MOVPE) is used as the crystal growth method. Note that the formation method is described below using the case where the hole layer 14P is a double lattice photonic crystal layer as an example, but a single lattice photonic crystal layer and a multiple lattice photonic crystal layer can also be formed in the same manner.

(a) Manufacturing Flow Fig. 3 is a flowchart showing a manufacturing method of the PCSEL device 10. Below, with reference to Fig. 3, a detailed description will be given of the process of manufacturing the PCSEL device 10 by forming air holes in the air hole layer by performing filling growth in the recesses (holes), and then growing the active layer and the p-side guide layer.

Figure 4 is a cross-sectional view that shows a schematic cross section of the n-side guide layer 14 in steps S0 to S3 of forming the buried layer 14B. Note that for ease of explanation and understanding, Figure 4 illustrates the case where the hole layer 14P is a single-lattice photonic crystal layer, but a multiple-lattice photonic crystal layer can also be formed in the same manner.

The buried layer 14B (laminated buried layer) formed on the air-holes by recrystallization growth will be described in detail below with reference to FIGS.
(Step S0) Formation of holes First, an n-type Al _0.04 Ga _0.96 N layer with an Al composition of 4% was grown on the substrate 12 as the n-cladding layer 13. Then, as shown in Fig. 4, a hole formation preparation layer 14E which is an n-type GaN layer was grown on the n-cladding layer 13. This hole formation preparation layer 14E is a preparation layer for forming the lower guide layer 14A and the air hole layer 14P containing air holes. The hole formation preparation layer 14E has a surface (upper surface) consisting of a flat (0001) plane.

After forming the hole formation preparation layer 14E, the substrate was removed from the chamber of the MOVPE device, and fine recesses (holes) were formed on the surface of the growth layer. After obtaining a clean surface by washing, a silicon nitride film (SiN _x ) was formed by plasma CVD. A resist for electron beam lithography was applied thereon, and the substrate was placed in an electron beam lithography device to perform patterning of a two-dimensional periodic structure.

Figure 5 is a plan view showing the main opening K1 and sub-opening K2 of the resist, and the main hole 14H1 and sub-hole 14H2 after etching. As shown in Figure 5, a pattern was performed in which pairs of openings, each consisting of an oval-shaped main opening K1 and a sub-opening K2 that is smaller than the main opening K1, were two-dimensionally arranged in the plane of the resist in a square lattice shape with a period PK. Note that for clarity of the drawing, the openings are shown with hatching.

More specifically, the main openings K1 are arranged two-dimensionally with their centers of gravity CD1 in two mutually orthogonal directions (x direction and y direction) on the lattice points of a square lattice with period PK. Similarly, the sub-openings K2 are arranged two-dimensionally with their centers of gravity CD2 in the x direction and y direction on the lattice points of a square lattice with period PK.

The long axes of the main opening K1 and the sub-opening K2 are parallel to the <11-20> crystal orientation, and the short axes of the main opening K1 and the sub-opening K2 are parallel to the <1-100> crystal orientation.

The center of gravity CD2 of the sub-opening K2 is spaced apart from the center of gravity CD1 of the main opening K1 by Δx and Δy. Here, Δx=Δy. In other words, the center of gravity CD2 of the sub-opening K2 is spaced apart from the center of gravity CD1 of the main opening K1 in the <1-100> direction.

The distances Δx and Δy between the centers of gravity of the main opening K1 and the sub-opening K2 were set to Δx=Δy=0.46PK. After the patterned resist was developed, the SiN _x film was selectively dry etched by an ICP-RIE (Inductive Coupled Plasma - Reactive Ion Etching) device. As a result, the main opening K1 and the sub-opening K2, which were two-dimensionally arranged on the lattice points of the square lattice with the period PK, were formed so as to penetrate the SiN _x film.

The period (hole spacing) PK was set to PK = 177.5 nm in order to set the oscillation wavelength (λ) to 438 nm.

Next, the resist was removed, and recesses (holes) were formed in the GaN surface using the patterned SiN _x film as a hard mask. The GaN was dry-etched in the depth direction using a chlorine-based gas and argon gas in an ICP-RIE apparatus, to form a main hole 14H1 and a sub-hole 14H2, which are oblong cylindrical recesses dug vertically in the GaN surface.

The recesses (holes) dug in the GaN surface by the above etching are simply referred to as holes to distinguish them from the air holes in the air hole layer 14P. In addition, when there is no particular distinction between the main holes 14H1 and the sub-holes 14H2, they may be collectively referred to as holes 14H.

The shape of the hole 14H is not limited to an elongated cylinder, but may be cylindrical, polygonal, etc.

As a result of the above, holes 14H were formed in the hole formation preparation layer 14E, and a hole formation layer 14J was formed (Figure 4, S0).

(Step S1) Surface Oxidation/Oxide Film Removal The substrate in which the holes 14H were formed was degreased and cleaned, and then the _SiNx film was removed using buffered hydrofluoric acid (BHF).

After removing the _SiNx film, UV light (ultraviolet light) was irradiated while flowing _O2 gas at room temperature to activate the _O2 gas, and the surface of the hole-forming layer 14J was oxidized (10 min) by the generated ozone. As a result, _SiO2 (glass) was formed on the upper surface of the hole-forming layer 14J and on the surface inside the hole 14H.

After the ozone treatment, the substrate was immersed in buffered hydrofluoric acid (BHF) to remove the oxide film that had formed on the surface. Through these steps, the Si bonded to Ga was removed.

Finally, the substrate was immersed in a semiconductor cleaning solution (Furuuchi Chemical: SemicoClean23) containing approximately 1% tetramethylammonium hydroxide (TMAH) for 10 minutes, and then rinsed with water.

(Step S2) Hole Closure-First Buried Growth Next, the substrate (FIG. 4) in which the hole 14H was formed (Step S0) and the surface oxidation/oxide film removal process (Step S1) was performed was degreased and cleaned, and then introduced again into the reactor of the MOVPE apparatus to perform recrystallization growth. Specifically, ammonia (NH ₃ ) and trimethylgallium (TMG) were supplied to perform the first buried growth by facet growth, and the opening of the hole 14H was closed.

Specifically, the first embedding growth was performed at a first temperature (920°C) at which the shape of hole 14H was transformed by mass transport into a shape composed of thermally stable surfaces.

More specifically, in this first temperature region, N atoms are attached to the top surface of the growth substrate, so that N-polarity faces are selectively grown. Therefore, as shown in FIG. 4, crystals whose surfaces are {1-101} facets are selectively grown. When the opposing {1-101} facets collide with each other, hole 14H is blocked and filled (facet growth). This type of facet growth results in a first filling growth, and vacancy 14K is formed corresponding to hole 14H.

In addition, in FIG. 4, the hole formation layer 14J (GaN layer) before the buried layer 14B is formed is shown by a dashed line.

(Step S3) Planarization Filling-Second Filling Growth Next, the hole 14H was closed by facet growth, and then the second filling layer 14B2 was grown to a thickness of 50 nm. The second filling layer 14B2 was grown by raising the substrate temperature (growth temperature) to 1050° C. (second filling temperature) and then supplying trimethylgallium (TMG) and NH ₃ . The second filling temperature was higher than the first filling temperature. However, the temperature relationship between the second filling temperature and the first filling temperature may be reversed as long as the growth surface of the second filling layer 14B2 can be grown to be the (0001) plane.

As shown in FIG. 4, a thermal effect causes mass transport, and a second buried growth (flattened buried growth) is performed to form a second buried layer 14B2 with a (0001) surface. The first buried growth and the second buried growth form a buried layer 14B.

For ease of explanation, the layer from the top surface of the void layer 14P (the surface closer to the active layer 15) to the top surface 14JS of the hole-forming layer 14J (including a part of the hole-forming layer 14J) is referred to as the first buried layer 14B1, and the layer from the top surface 14JS of the hole-forming layer 14J to the flat surface formed by the second buried growth is referred to as the second buried layer 14B2 (see FIG. 4, S3).

The entire semiconductor layer from the top surface of the void layer 14P to the top surface of the second buried layer 14B2 (including a portion of the hole-forming layer 14J) is referred to as the buried layer 14B.

Here, the thickness of the first buried layer 14B1 is defined as D1, and the thickness of the second buried layer 14B2 is defined as D2. Therefore, the thickness of the buried layer 14B is given by D=D1+D2.
In this specification, the “upper surface” of each semiconductor layer of the n-side guide layer (first guide layer) 14 refers to the surface on the side closer to the active layer 15 .

In this embodiment, GaN is used for the second buried growth. The second buried layer 14B2 also functions as a light distribution adjustment layer to adjust the coupling efficiency (light field) between the light and the hole layer 14P.

That is, in this embodiment, undoped GaN is used for the first buried growth and the second buried growth. However, the first buried growth and the second buried growth are not limited to GaN, and n-GaN, n-InGaN, undoped GaN, undoped InGaN, or a combination of these semiconductors can be used.

(Step S4) Recrystallization Growth Next, crystal growth of the layer above the light distribution adjustment layer 23 was carried out in a reactor on the substrate on which the etching of the buried layer 14B had been performed.

Specifically, the light distribution-adjusting layer 23 is grown on the second buried layer 14B2. Specifically, the light distribution-adjusting layer 23 is an undoped In _0.03 Ga _0.97 N layer, and is a semiconductor layer (heterogeneous semiconductor layer) having a different crystal composition from the buried layer 14B (GaN layer).

Next, the active layer 15, the p-side guide layer (second guide layer) 16, the electron barrier layer (EBL) 17, the p-cladding layer 18, and the p-contact layer 19 were grown in sequence on the light distribution adjustment layer 23. In this way, the PCSEL element 10 was fabricated.

(b) Hole layer The above-mentioned embedding process formed a double lattice structure hole layer 14P in which hole pairs 14K consisting of a main hole 14K1 and a subhole 14K2 are two-dimensionally arranged at each square lattice point. Here, the subhole 14K2 has a smaller hole diameter and height than the main hole 14K1. In the present invention, the upper surface of the hole in the multi-lattice structure hole layer 14P means the upper surface of the main hole 14K1 or the subhole 14K2 that is closer to the upper layer (active layer) (i.e., a hole having a shallow upper surface). Note that the hole pair 14K may be a single photon structure in which holes of the same size are two-dimensionally arranged at each square lattice point, instead of the main hole 14K1 and the subhole 14K2 having different sizes.

Figure 6 is a schematic diagram showing a cross section of the formed vacancy layer 14P perpendicular to the central axis CX. When filling holes 14H in the group III nitride, the shape of holes 14H is deformed by mass transport into a shape composed of thermally stable surfaces, and vacancies 14K are formed.

That is, in the +c-plane substrate, the inner surface of the hole 14H changes shape to a (1-100) plane (i.e., an m-plane). That is, the shape changes from an oval cylindrical shape to an oval hexagonal prism-shaped hole 14K whose side surface is made up of m-planes.

The main void 14K1 formed had a long hexagonal prism shape with a long diameter of 72.5 nm and a short diameter of 43.5 nm, and a long diameter/short diameter ratio of 1.67. The sub-void 14K2 had a long diameter of 44.6 nm and a short diameter of 38.3 nm, and a long diameter/short diameter ratio of 1.16, and had a long hexagonal prism shape closer to a regular hexagonal prism than the main void 14K1.

The distances Δx and Δy between the centers of gravity of the main hole 14K1 and the subhole 14K2 were 81.6 nm (Δx = Δy = 0.46 PK), and it was confirmed that this had not changed since before the filling. It was also confirmed that the major axes of the main hole 14K1 and the subhole 14K2 were parallel to the <11-20> axis (i.e., the a-axis).

Furthermore, the void filling rates (filling factors) FF1 and FF2 of the main voids 14K1 and the sub-voids 14K2 were calculated to be FF1 = 8.8% and FF2 = 4.2%. Here, the void filling rate is the ratio of the area occupied by each void per unit area in a two-dimensional regular array. Specifically, when the areas of the main voids 14K1 and the sub-voids 14K2 in the void layer 14P are S1 and S2, respectively, the void filling rates FF1 and FF2 of the main voids 14K1 and the sub-voids 14K2 are given by the following formulas.

FF1=S1/ ^PK2 , FF2=S2/ ^PK2
Through the above steps, the formation of the n-side guide layer 14 including the vacancy layer 14P is completed.

3. Effects of surface oxidation/oxide film removal
(a) Reduction of Interface Si Concentration Fig. 7 shows the measurement results (SIMS profile) of SIMS (Secondary Ion Mass Spectroscopy) in the depth direction of the PCSEL element 10 (EMB) manufactured by performing surface oxidation/oxide film removal processing (step S1) on a substrate in which holes 14H are formed. For clarity of the figure, each semiconductor layer is indicated by its reference number. For example, "14B1" indicates the first buried layer 14B1, "14B2" indicates the second buried layer 14B2, and "23" indicates the light distribution adjustment layer 23.

Figure 8 also shows the SIMS profile in the depth direction of a PCSEL element (CMP) manufactured without performing the surface oxidation/oxide film removal process (step S1).

In the PCSEL element (CMP) that did not undergo surface oxidation/oxide film removal, a high concentration of Si of about 1×10 ²⁰ cm ⁻³ was present at the interface between the first buried layer 14B1 and the second buried layer 14B2 and at the interface between the second buried layer 14B2 and the light distribution-adjusting layer 23.

On the other hand, as shown in FIG. 7, by oxidizing the Si on the surface by ozone treatment and removing the oxide film by BHF treatment, the Si concentration at the interface can be reduced to about 2×10 ¹⁹ cm ⁻³ (about ¼ or less).

(b) Flatness of the regrown layer A large amount of Si was deposited on the semiconductor surface where the hole 14H was formed due to the adhesion of the SiNx film, which is a hard mask, and siloxane in the atmosphere. During crystal growth, in a highly reactive nitrogen atmosphere (for example, an atmosphere in which NH ₃ is dissociated at high temperature), Si on the surface reacts with N to form SiN. SiN forms an inversion domain on the GaN surface, which causes the polarity of GaN formed in the region contaminated with SiN on the top surface of the first buried layer by facet growth to be locally inverted, and an inversion domain is formed during the shape change due to mass transport when the second buried layer 14B2 is formed, causing significant surface roughness. In addition, when Si is doped at a level that forms an inversion domain, even if the buried layer can be grown while maintaining surface flatness, point defects are likely to be introduced.

That is, in the conventional technology, it is not possible to obtain a highly flat growth surface, and it is not possible to reduce the oscillation threshold current of the surface-emitting laser element. Also, since the hole layer 14P and the active layer 15 cannot be brought sufficiently close to each other, it is difficult to obtain a surface-emitting laser element having good characteristics and high coupling efficiency between the hole layer 14P and the active layer 15.
Furthermore, a large number of point defects are introduced into the film, which deteriorates the crystallinity, making it difficult to obtain a surface-emitting laser element with good characteristics.

As described above, by performing surface oxidation and oxide film removal processing, the Si concentration at the interface can be significantly reduced and the formation of inversion domains can be suppressed, allowing the growth of a high-quality active layer with high flatness.

This makes it possible to provide a surface-emitting semiconductor laser element with a low threshold and high efficiency.

Second Embodiment
Fig. 9A is a cross-sectional view showing an example of the structure of a photonic crystal surface-emitting laser element (PCSEL element) 30 according to a second embodiment, and Fig. 9B is an enlarged cross-sectional view showing an air hole layer 14P and air holes 14K arranged in the air hole layer 14P in Fig. 9A.

Figure 10 is a flowchart showing a method for manufacturing the PCSEL element 30 of the second embodiment. Note that the same steps as those in the method for manufacturing the PCSEL element 10 of the first embodiment are denoted by the same reference numerals.

Also, FIG. 11 is a cross-sectional view that shows a schematic cross section of the n-side guide layer 14 in step S3A of the manufacturing method.

(a) Manufacturing Method and Structure of PCSEL Device As shown in FIG. 10, in the PCSEL device 30, after performing a surface oxidation and oxide film removal process (step S1), the buried layer 14B is grown (steps S2 and S3), and then the buried layer 14B is etched by H ₂ annealing (step S3A).

More specifically, as shown in FIG. 11, the semiconductor layer on the void layer 14P was etched by TE from the surface of the buried layer 14B (thickness D). The thickness of the remaining buried layer 14B is DE (= D-TE). In other words, the thickness from the top surface of the void 14K to the surface (top surface) of the remaining buried layer 14B is DE.

In other words, a buried layer 14BE (a thinned buried layer, hereinafter also referred to as a thinned buried layer) having a thickness DE was formed by the etching in step S3A.

That is, the PCSEL element 30 differs from the PCSEL element 10 of the first embodiment in that it has a thin-film buried layer 14BE formed by etching, but is otherwise the same as the PCSEL element 10 of the first embodiment.

(b) Thinning of Buried Layer--H ₂ Annealing and Etching The surface morphology of the buried layer 14B (thinned buried layer 14BE) was evaluated when the buried layer 14B was etched from the surface thereof by H ₂ annealing.

Specifically, samples (i) to (iv) were fabricated in which the thickness DE of the thin-film buried layer 14BE (i.e., buried layer 14B after etching) was changed by changing the etching time.

As described above, the Si concentration at the interface is reduced to about 2×10 ¹⁹ cm ⁻³ by the surface oxidation and oxide film removal processes.

FIG. 12 is an SEM image showing a cross section of the surface of the semiconductor layer on which the buried layer 14B is regrown after the surface oxidation/oxide film removal process (step S1) has been performed, the surface being etched by H ₂ annealing.

As shown in FIG. 12, the thickness DE of the thin-film buried layer 14BE was (i) DE = 114 nm, (ii) DE = 66 nm, (iii) DE = 4 nm, and (iv) DE < 1 nm.

In annealing in a _H2 atmosphere, the (0001) plane is a thermally stable plane, and the buried layer 14B can be etched and thinned while maintaining the flatness of the surface. Therefore, a high-quality active layer with high flatness can be grown on the buried layer 14B. The annealing atmosphere may contain group III and group V materials.

More specifically, in the case of a group III nitride semiconductor, high-temperature annealing in an _H2 atmosphere causes the detachment of surface atoms, and the surface is etched. At this time, the surface with the slowest etching rate remains, so that the most thermally stable (0001) surface is formed on the surface. Therefore, when a +c-plane substrate is used, etching can be performed while maintaining the (0001) surface parallel to the substrate. This allows the buried layer 14B to be made thinner, and the interval (distance) between the vacancy layer 14P (vacancy layer) and the active layer 15 to be reduced.

The surface morphology of samples (i) to (iv) was observed using an AFM (atomic force microscope). Figure 13 shows AFM images of the surfaces of samples (i) to (iv).

When the thickness DE of the thin-film buried layer 14BE was (i) DE = 114 nm, (ii) DE = 66 nm, (iii) DE = 4 nm, and (iv) DE < 1 nm, the surface roughness was Ra = 0.633 nm, 0.508 nm, 0.532 nm, and 2.43 nm, respectively, in an area of 20 μm x 20 μm.

It was found that in the cases (i) to (iii), a sufficiently flat surface could be obtained. It was also found that (iii) good flatness could be obtained even when the thickness was made extremely thin, at DE = 4 nm. (iv) When DE < 1 nm, significant surface roughness was observed.

Figure 14 is a graph plotting the surface roughness Ra in a 20 μm x 20 μm area against the thickness DE of the thin-film buried layer 14BE.

As shown in FIG. 14, if DE≧4 nm, a sufficiently flat surface can be obtained. More specifically, if the thickness DE of the thin-film buried layer 14BE is 4 nm or more, the surface roughness Ra in a 20 μm×20 μm area can be obtained as Ra≦0.7 nm.

(c) Distance between the air hole layer and the active layer From the above results, it can be seen that if the distance between the air hole layer 14P and the active layer 15, i.e., the distance between the upper surfaces of the air holes 14K in the air hole layer 14P and the active layer 15, is 4 nm or more, a sufficiently flat active layer 15 can be obtained, and a surface-emitting laser element with good characteristics and high coupling efficiency between the air hole layer 14P and the active layer 15 can be obtained.

In order to obtain high coupling efficiency, it is preferable that the distance between the hole layer 14P and the active layer 15 is 200 nm or less.

Furthermore, by setting the distance between the void layer 14P and the active layer 15 to 4 to 150 nm, a surface-emitting semiconductor laser element with a higher resonance effect, low threshold and high efficiency can be obtained.

When the active layer 15 is an active layer with a quantum well structure, the distance between the upper surface of the void 14K and the active layer 15 refers to the distance between the upper surface of the void 14K and the first quantum well layer (i.e., the quantum well layer closest to the void layer 14P).

In addition, in the past, in order to obtain a high hole filling rate in a hole layer with a multi-lattice structure, a thicker buried layer was sometimes required than in a hole layer with a single lattice structure. According to the present invention, even in such cases, a thin buried layer can be used, and a high coupling efficiency (resonance effect) between the hole layer and the active layer can be obtained.

According to this embodiment, the void layer 14P and the active layer 15 having high flatness can be provided in close proximity to each other. Specifically, as described above, if the thickness of the buried layer 14BE is 4 nm or more, the surface roughness Ra of the buried layer 14BE is Ra≦0.7 nm.

As shown in the SIMS measurement results in FIGS. 7 and 8, in the portion in the first buried layer 14B1 where the Si concentration is flat, the Si concentration is about 4.5×10 ¹⁸ cm ^-3 when the oxide film of the hole formation layer 14J is removed (step S1) (FIG. 7), which is reduced from about 6.0×10 ¹⁸ cm ^-3 when the oxide film is not removed (FIG. 8).

Therefore, it can be seen that by oxidizing the surface of the hole formation layer 14J and removing the oxide film, the Si concentration in the buried layer 14B is reduced, making it possible to re-grow a semiconductor layer with high flatness.

The first and second embodiments have been described above in detail. In the first and second embodiments, the case where the light distribution adjustment layer 23 is provided has been described, but the active layer 15 may be formed directly on the buried layer 14B or the buried layer 14BE without providing the light distribution adjustment layer 23. In this case, the void layer 14P and the active layer 15 having high flatness may be provided in close proximity to each other.

As described above in detail, according to the present invention, it is possible to increase the resonance effect by bringing the air hole layer and the active layer into close proximity, and it is possible to provide a method for manufacturing a surface-emitting semiconductor laser element having a high-quality active layer, a low threshold value, and high efficiency, and a photonic crystal surface-emitting laser element.

Note that, unless otherwise specified, the numerical values in the above-described embodiments are merely examples and can be modified as appropriate. In addition, although a double-lattice structure PCSEL element is illustrated, the present invention can be applied to a single-lattice structure PCSEL element and generally to a multiple-lattice structure PCSEL element.

In addition, the present invention has been exemplified with a photonic crystal layer in which the holes have a hexagonal columnar shape, but it can also be applied to cases in which the holes in the photonic crystal layer have an irregular columnar shape, such as a cylindrical, rectangular, polygonal, or teardrop shape.

10: PCSEL element 12: Element substrate 13: First cladding layer 14: First guide layer 14A: Lower guide layer 14B: Buried layer 14BE: Buried layer 14B1: First buried layer 14B2: Second buried layer 14B2: Second buried layer 14E: Hole formation preparation layer 14J: Hole formation layer 14K: Hole/hole pair 14K1/14K2: Main/secondary hole 14P: Photonic crystal layer (hole layer)
15: Active layer 16: Second guide layer 17: Electron barrier layer 18: Second cladding layer 19: Contact layer 23: Light distribution adjustment layer

Claims (11)

A method for manufacturing a surface emitting semiconductor laser device, comprising the steps of:
(a) forming a hole formation preparation layer on a substrate;
(b) forming holes arranged two-dimensionally at each of the lattice points in the hole formation preparation layer to form a hole formation layer;
(c) oxidizing the surface of the hole formation layer to form an oxide film, and then removing the oxide film;
(d) forming a first burying layer by facet growth to close the hole;
(e) growing a second burying layer that buries the first burying layer flatly to form a first guide layer including a hole layer having holes corresponding to the holes;
(f) growing crystals of a semiconductor layer including an active layer on the first guide layer. A method for manufacturing a surface emitting semiconductor laser device, comprising the steps of:
(a) forming a hole formation preparation layer on a substrate;
(b) forming holes arranged two-dimensionally at each of the lattice points in the hole formation preparation layer to form a hole formation layer;
(c) oxidizing the surface of the hole formation layer to form an oxide film, and then removing the oxide film;
(d) forming a first burying layer by facet growth to close the hole;
(e) growing a second burying layer that buries the first burying layer flatly to form a first guide layer including a hole layer having holes corresponding to the holes;
(f) flattening the surface of the first guide layer by annealing in a hydrogen atmosphere;
(g) growing crystals of a semiconductor layer including an active layer on the flat etched first guide layer. The manufacturing method according to claim 1 or 2, wherein the step of forming the oxide film is a step of oxidizing the surface of the hole-forming layer with ozone. the surface emitting semiconductor laser element is a GaN-based semiconductor laser element,
3. The method according to claim 1, wherein the Si concentration at the interface between the guide layer and the semiconductor layer including the active layer is 2×10 ¹⁹ cm ⁻³ or less. the surface emitting semiconductor laser element is a GaN-based semiconductor laser element,
the crystal growth surface of the substrate is a {0001} surface;
The facet plane of the facet growth is a {1-101} plane.
The method according to claim 1 or 2. The manufacturing method according to claim 1 or 2, wherein the distance from the upper surface of the hole in the hole layer to the active layer is 200 nm or less. The manufacturing method according to claim 2, wherein the thickness of the second buried layer on the upper surface of the hole formation layer after the flattening etching is 4 nm or more. An n-type semiconductor layer;
a first guide layer including: a hole layer formed on the n-type semiconductor layer, the hole layer having holes arranged two-dimensionally at each lattice point; and a buried layer formed on the hole layer to close the holes;
a semiconductor layer including an active layer formed on the buried layer;
a second guide layer formed on the semiconductor layer including the active layer;
a distance from an upper surface of the hole in the hole layer to the active layer is 4 to 200 nm;
Surface-emitting semiconductor laser element. The surface emitting semiconductor laser element according to claim 8, wherein the surface roughness Ra of the buried layer is Ra≦0.7 nm. the active layer has a quantum well structure,
9. The surface emitting semiconductor laser device according to claim 8, wherein the distance to the active layer is the distance between a quantum well closest to the hole layer and an upper surface of the hole. The surface-emitting semiconductor laser element according to claim 8, wherein the semiconductor layer including the active layer is provided between the buried layer and the active layer, and includes a heterogeneous semiconductor layer having a different crystal composition from the buried layer.

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