JP2024140968A - Charge pump circuit and motor driver circuit - Google Patents

Abstract

To reduce a withstand voltage required for a flying capacitor of a charge pump circuit.SOLUTION: A driver circuit 320 generates complementary first and second pulse signals Vp1 and Vp2 in synchronization with a clock signal CLK and applies them to the first and second flying capacitors Cf1 and Cf2. The high levels of the first and second pulse signals Vp1 and Vp2 are a first voltage V1, and their low levels are a second voltage V2 that is lower than the first voltage V1 by a predetermined voltage width ΔV and higher than 0 V.SELECTED DRAWING: Figure 1

Description

This disclosure relates to a charge pump circuit.

When a semiconductor integrated circuit requires a voltage higher than the power supply voltage, a charge pump circuit is used. A charge pump circuit generates a voltage higher than the power supply voltage by repeatedly storing charge in a flying capacitor and transferring the stored charge to an output capacitor.

Patent No. 6208504

If the flying capacitor is an external chip component, the number of components in the application circuit increases, which leads to higher costs. In addition, the semiconductor integrated circuit must be provided with pads and terminals for connecting the flying capacitor, which leads to an increase in the chip area.

When incorporating a flying capacitor into a semiconductor integrated circuit, the capacitor needs to have a high withstand voltage. In this case, it is necessary to adopt a process that can form a high-voltage capacitor.

Alternatively, a lower-voltage capacitor can be connected in series to increase the voltage resistance, but this increases the capacitor area. For example, if a 1pF capacitor is required, two 2pF capacitors must be connected in series, which increases the capacitor area by four times.

This disclosure has been made in consideration of these problems, and one exemplary purpose of one aspect of the disclosure is to provide a charge pump circuit that can reduce the withstand voltage required of a capacitor.

An aspect of the present disclosure relates to a charge pump circuit. The charge pump circuit includes an input line receiving a first voltage, an output line, a first flying capacitor having a first end connected to the input line, a second flying capacitor having a first end connected to the input line, a first transistor having a first electrode connected to the output line, a second electrode connected to the second end of the first flying capacitor, and a control electrode connected to the second end of the second flying capacitor, a second transistor having a first electrode connected to the output line, a second electrode connected to the second end of the second flying capacitor, and a control electrode connected to the second end of the first flying capacitor, and a second transistor having a first electrode connected to the input line, a second electrode connected to the second end of the first flying capacitor, and a control electrode connected to the second end of the first flying capacitor. a third transistor having a first electrode connected to the input line and a control electrode connected to the second end of the second flying capacitor; a fourth transistor having a first electrode connected to the input line and a second electrode connected to the second end of the second flying capacitor and a control electrode connected to the second end of the first flying capacitor; and a driver circuit that applies a first pulse voltage, in which the first voltage is high and a second voltage that is a predetermined voltage width lower than the first voltage is low, to the first end of the first flying capacitor in synchronization with the clock signal, and applies a second pulse voltage, in phase opposite to the first pulse voltage, with the first voltage being high and the second voltage being low, to the first end of the second flying capacitor, and are integrated on a single semiconductor substrate.

In addition, any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or disclosure. Furthermore, the description in this section (Means for solving the problem) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention.

According to certain aspects of the present disclosure, it is possible to reduce the withstand voltage required for flying capacitors.

FIG. 1 is a circuit diagram of a semiconductor integrated circuit including a charge pump circuit according to an embodiment. FIG. 2 is a diagram showing the first state φ1 of the charge pump circuit of FIG. FIG. 3 is a diagram showing the second state φ2 of the charge pump circuit of FIG. FIG. 4 is a circuit diagram showing an example of the configuration of the driver circuit. FIG. 5 is a circuit diagram showing another example of the configuration of the driver circuit. FIG. 6 is a circuit diagram of a motor driver circuit including a charge pump circuit. FIG. 7 is an operational waveform diagram of the motor driver circuit of FIG.

(Overview of the embodiment)
A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be a comprehensive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

A charge pump circuit according to one embodiment includes an input line receiving a first voltage, an output line, a first flying capacitor having a first end connected to the input line, a second flying capacitor having a first end connected to the input line, a first transistor having a first electrode connected to the output line, a second electrode connected to a second end of the first flying capacitor, and a control electrode connected to a second end of the second flying capacitor, a second transistor having a first electrode connected to the output line, a second electrode connected to a second end of the second flying capacitor, and a control electrode connected to the second end of the first flying capacitor, and a first electrode connected to the input line and a second electrode connected to the input line of the first flying capacitor. The third transistor is connected to the second end and has a control electrode connected to the second end of the second flying capacitor; a fourth transistor has a first electrode connected to the input line, a second electrode connected to the second end of the second flying capacitor, and a control electrode connected to the second end of the first flying capacitor; and a driver circuit that applies a first pulse voltage to the first end of the first flying capacitor in synchronization with a clock signal, with the first voltage being high and a second voltage being low that is a predetermined voltage width lower than the first voltage, and applies a second pulse voltage of opposite phase to the first pulse voltage, with the first voltage being high and the second voltage being low, to the first end of the second flying capacitor, and is integrated on a single semiconductor substrate.

With this configuration, a voltage equivalent to a predetermined voltage range is applied across the flying capacitor. Because the predetermined voltage range is smaller than the power supply voltage, the withstand voltage required for the flying capacitor can be reduced.

In one embodiment, the driver circuit may include a voltage source that generates a second voltage that is a predetermined voltage step lower than the first voltage, a first inverter having an upper power supply terminal connected to an input line and a lower power supply terminal connected to an output of the voltage source, and a second inverter having an upper power supply terminal connected to the input line and a lower power supply terminal connected to an output of the voltage source.

In one embodiment, the voltage source may include an output node and a Zener diode provided between the input line and the output node. In this case, the predetermined voltage width can be determined according to the Zener voltage.

In one embodiment, the voltage source may further include a diode connected in series with the Zener diode between the input line and the output node. In this case, the predetermined voltage width can be determined according to a combination of the Zener voltage and the forward voltage of the diode.

In one embodiment, the voltage source may include a linear regulator.

A motor driver circuit according to one embodiment may include a logic circuit that generates a control signal that instructs the high-side transistor to be on or off, and a high-side driver that drives the high-side transistor in response to the control signal. The high-side driver may include any of the above-mentioned charge pump circuits, the output line of which is connected to the gate of the high-side transistor, that generates a boosted voltage in response to a clock signal and supplies the boosted voltage to the gate of the high-side transistor, and a charge control circuit that operates the charge pump circuit in response to the control signal transitioning to an on state that instructs the high-side transistor to be on.

With this configuration, the charge pump circuit operates for a predetermined time after the control signal transitions to the on state, and is stopped for the rest of the time, thereby reducing the switching loss of the charge pump circuit and enabling highly efficient operation.

(Embodiment)
Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and duplicated descriptions will be omitted as appropriate. In addition, the embodiments are illustrative and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

In this specification, "a state in which component A is connected to component B" includes cases in which component A and component B are directly physically connected, and cases in which component A and component B are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect achieved by their combination.

Similarly, "a state in which component C is provided between components A and B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect achieved by their combination.

The vertical and horizontal axes of the waveform diagrams and time charts shown in this specification have been enlarged or reduced as appropriate to facilitate understanding, and each waveform shown has been simplified to facilitate understanding.

FIG. 1 is a circuit diagram of a semiconductor integrated circuit 400 including a charge pump circuit 300 according to an embodiment. The charge pump circuit 300 is integrated on a single semiconductor substrate and is one of the functional blocks of the semiconductor integrated circuit 400.

The semiconductor integrated circuit 400 includes a charge pump circuit 300, an oscillator 410, and a load circuit 420. The oscillator 410 generates a clock signal CLK. The charge pump circuit 300 performs a switching operation in synchronization with the clock signal CLK, boosts a power supply voltage Vcc, and generates an output voltage _VOUT higher than the power supply voltage Vcc. The output voltage _VOUT is supplied to the load circuit 420.

The charge pump circuit 300 includes a clock input node clkin, a reference input node refin, an output node out, an input line 302, an output line 304, a first transistor M11 to a fourth transistor M14, a first flying capacitor Cf1, a second flying capacitor Cf2, and a driver circuit 320.

A clock signal CLK is supplied to a clock input node clkin from an oscillator 410. A power supply voltage V _CC is supplied to a reference input node refin as a first voltage V1. The input line 302 is connected to the reference input node refin. A load circuit 420 is connected to the output line 304 via an output node out. The first flying capacitor Cf1 and the second flying capacitor Cf2 each have a first end and a second end. An output capacitor may be connected to the output line 304.

The first transistor M11 and the second transistor M12 are PMOS (Metal Oxide Semiconductor) transistors. The first transistor M11 has a first electrode (source) connected to the output line 304 and a second electrode (drain) connected to the second end of the first flying capacitor Cf1. The control electrode (gate) of the first transistor M11 is connected to the second end of the second flying capacitor Cf2.

The second transistor M12 has a first electrode (source) connected to the output line 304 and a second electrode (drain) connected to the second end of the second flying capacitor Cf2. The control electrode (gate) of the second transistor M12 is connected to the second end of the first flying capacitor Cf1.

The third transistor M13 and the fourth transistor M14 are NMOS transistors. The third transistor M13 has a first electrode (source) connected to the input line 302 and a second electrode (drain) connected to the second end of the first flying capacitor Cf1. The control electrode (gate) of the third transistor M13 is connected to the second end of the second flying capacitor Cf2.

The fourth transistor M14 has a first electrode (source) connected to the input line 302, a second electrode (drain) connected to the second end of the second flying capacitor Cf2, and a control electrode (gate) connected to the second end of the first flying capacitor Cf1.

The driver circuit 320 applies a first pulse voltage Vp1, in which a first voltage V1 (=Vcc) is high and a second voltage V2 is low, to a first end of the first flying capacitor Cf1 in synchronization with the clock signal CLK. The second voltage V2 is a positive voltage that is lower than the first voltage V1 by a predetermined voltage width ΔV.
V2=V1-ΔV>0
In other words, ΔV<V1 holds true.

In addition, the driver circuit 320 applies a second pulse voltage Vp2, which is in opposite phase to the first pulse voltage Vp1, to the first end of the second flying capacitor Cf2 in synchronization with the clock signal CLK, with the first voltage V1 (=Vcc) set to high and the second voltage V2 set to low.

The driver circuit 320 includes a first inverter 322, a second inverter 324, a voltage source 326, and a level shifter 328.

The voltage source 326 generates a second voltage V2 that is a predetermined voltage step ΔV lower than the first voltage V1 of the input line 302.

The level shifter 328 receives the clock signal CLK and performs level shifting.

The upper power supply terminals of the first inverter 322 and the second inverter 324 are connected to the input line 302 and are supplied with the first voltage V1. The lower power supply terminals of the first inverter 322 and the second inverter 324 are connected to the output of the voltage source 326 and are supplied with the second voltage V2.

The first inverter 322 inverts the level-shifted clock signal CLKa and applies it to the first end of the first flying capacitor Cf1 as the first pulse voltage Vp1. The second inverter 324 inverts the first pulse voltage Vp1, which is the output of the first inverter 322, and applies it to the first end of the second flying capacitor Cf2 as the second pulse voltage Vp2.

The above is the configuration of the semiconductor integrated circuit 400. Next, the operation of the charge pump circuit 300 will be explained.

The charge pump circuit 300 alternates between the first state φ1 and the second state φ2 in response to the clock signal CLK.

Figure 2 is a diagram showing the first state φ1 of the charge pump circuit 300 in Figure 1. In the first state φ1, Vp1 = V1, Vp2 = V2. Also, transistors M11 and M14 are on, and transistors M12 and M13 are off.

Because the fourth transistor M14 is on, the second end of the second flying capacitor Cf2 is connected to the input line 302 via the fourth transistor M14. Therefore, V1-V2=ΔV is applied across the second flying capacitor Cf2, causing it to be charged.

On the other hand, the first flying capacitor Cf1 is charged in the immediately preceding second state φ2, and the voltage across it is ΔV. Since the potential at the first end of the first flying capacitor Cf1 is V1, the potential at the second end of the first flying capacitor Cf1 is V1+ΔV. This voltage V1+ΔV is supplied to the output line 304 via the first transistor M11.

Figure 3 is a diagram showing the second state φ2 of the charge pump circuit 300 in Figure 1. In the second state φ2, Vp1 = V2, Vp2 = V1. Also, transistors M11 and M14 are off, and transistors M12 and M13 are on.

Because the third transistor M13 is on, the second end of the first flying capacitor Cf1 is connected to the input line 302 via the third transistor M13. Therefore, V1-V2=ΔV is applied across the first flying capacitor Cf1, causing it to be charged.

On the other hand, the second flying capacitor Cf2 is charged in the immediately preceding first state φ1, and the voltage across it is ΔV. Since the potential at the first end of the second flying capacitor Cf2 is V1, the potential at the second end of the second flying capacitor Cf2 is V1+ΔV. This voltage V1+ΔV is supplied to the output line 304 via the second transistor M12.

The charge pump circuit 300 generates an output voltage V _OUT =V1+ΔV on the output line 304 by alternately repeating a first state φ1 and a second state φ2.

The above is the operation of the charge pump circuit 300. Next, we will explain its advantages.

The advantages of the charge pump circuit 300 become clear when compared with the comparative technique. In the comparative technique, the lower power supply terminals of the first inverter 322 and the second inverter 324 are grounded. In this case, in the first state φ1 and the second state φ2, the first flying capacitor Cf1 and the second flying capacitor Cf2 are charged with the first voltage V1 (i.e., the power supply voltage V _CC ). Therefore, the withstand voltages of the first flying capacitor Cf1 and the second flying capacitor Cf2 must be determined based on the power supply voltage V _CC . When V _CC =12V, the first flying capacitor Cf1 and the second flying capacitor Cf2 are required to have a withstand voltage of 12V or more.

Returning to the embodiment, in the first state φ1 and the second state φ2, the first flying capacitor Cf1 and the second flying capacitor Cf2 are charged with ΔV, which is the potential difference between the first voltage V1 and the second voltage V2. Therefore, the withstand voltages of the first flying capacitor Cf1 and the second flying capacitor Cf2 may be determined based on a predetermined voltage width ΔV. Since ΔV<V _CC holds, the withstand voltage required of the first flying capacitor Cf1 and the second flying capacitor Cf2 can be made smaller than that of the comparative technology.

4 is a circuit diagram showing a configuration example of the driver circuit 320. The lower power supply terminals of the first inverter 322 and the second inverter 324 are connected to the constant voltage line 306. The voltage source 326 includes a buffer 329, a Zener diode ZD1, and a resistor R1. The Zener diode ZD1 is connected between the input line 302 and the input of the buffer 329. When the Zener voltage of the Zener diode ZD1 is _VZ , a voltage Vx is generated at the node n1.
Vx=V1- _VZ
The buffer 329 is, for example, a voltage follower circuit using an operational amplifier, and has a current sink capability. The buffer 329 keeps the voltage V2 equal to Vx.
V2=Vx=V1-V _Z
That is, the predetermined voltage width ΔV is equal to the Zener voltage V _Z. If the input impedance of the buffer 329 is low, the resistor R1 can be omitted.

If it is desired to make the predetermined voltage step ΔV larger than the Zener voltage _VZ , one or more diodes D1 may be added in series with the Zener diode ZD1. When the number of diodes D1 is n,
ΔV=V _Z +n×Vf
Vf is the forward voltage of the diode D1.

5 is a circuit diagram showing another example of the configuration of the driver circuit 320. In the driver circuit 320 of FIG. 5, the buffer 329 of the driver circuit 320 of FIG. 4 is replaced with a PMOS transistor MP1. The transistor MP1 forms a source follower circuit, and the voltage V2 of the constant voltage line 306 is expressed as follows:
V2=Vn1+Vth(p)
Vth(p) is the gate threshold voltage of the PMOS transistor.

V2=V1- _VZ +Vth(p)
Therefore, the predetermined voltage width ΔV is V _Z -Vth(p).Also in FIG. 5, one or more diodes D1 may be added in series with the Zener diode ZD1.

The voltage source 326 may be a series regulator of other configurations or a shunt regulator.

Next, we will explain the uses of the charge pump circuit 300. The charge pump circuit 300 can be used in a motor driver circuit.

Figure 6 is a circuit diagram of a motor driver circuit 100B that includes a charge pump circuit 300. The number of phases of the motor is not particularly limited and may be single-phase or multi-phase (e.g., three-phase), and the number of legs is designed according to the motor.

The motor driver circuit 100B includes a leg 102 of an inverter circuit, an oscillator 110, a logic circuit 120, a high-side driver 130B, and a low-side driver 140. A coil L of a motor to be driven is connected to an output pin OUT. A power supply voltage _VCC is supplied to a power supply pin VCC, and a ground pin GND is grounded.

Leg 102 includes a high-side transistor M1, which is the upper arm, and a low-side transistor M2, which is the lower arm.

The oscillator 110 generates a clock signal CLK. The clock signal CLK may be a system clock for the motor driver circuit 100B, and is supplied to the logic circuit 120.

The logic circuit 120 generates a control signal CTRLH that instructs the high-side transistor M1 to be on or off in response to the input signal IN. The logic circuit 120 also generates a control signal CTRLL that instructs the low-side transistor M2 to be on or off in response to the input signal IN.

The high-side driver 130B drives the high-side transistor M1 in response to the control signal CTRLH. The low-side driver 140 drives the low-side transistor M2 in response to the control signal CTRLL.

The high-side driver 130B includes a charge pump circuit 132B, a charge control circuit 138, a first switch SW1, a second switch SW2, and a turn-off circuit 136.

The charge pump circuit 132B performs a switching operation in response to a clock signal Vclkin supplied to a clock input node clkin, and generates a boosted voltage _VCP . The boosted voltage _VCP is supplied to the gate of the high-side transistor M1.

The charge pump circuit 132B is the charge pump circuit 300 according to the embodiment.

The first switch SW1 is provided between the clock input node clkin of the charge pump circuit 132B and the output node of the oscillator 110.

The control signal CTRLH includes a high-side on signal HON and a high-side off signal HOFF. The high-side on signal HON is a signal that is asserted (e.g., high) during the on period of the high-side transistor M1, and the low-side on signal LON is a signal that is asserted (e.g., high) during the off period of the high-side transistor M1.

The charging control circuit 138B generates control signals S1 and S2 based on the high side on signal HON to control the first switch SW1 and the third switch SW3. The third switch SW3 is on during the period when the high side on signal HON is asserted.

The first switch SW1 may be kept on while the high-side on signal HON is asserted, or may be turned on only for a certain charging period after the high-side on signal HON is asserted, and turned off after the gate voltage _Vgate of the high-side transistor M1 becomes sufficiently high.

While the first switch SW1 is on, the clock signal CLK is supplied to the clock input node clkin of the charge pump circuit 132, the charge pump circuit 132 is enabled, the boosted voltage _VCP is supplied to the gate of the high-side transistor M1, and the high-side transistor M1 is turned on.

Preferably, the charge control circuit 138B turns on the third switch SW3 immediately when the high-side on signal HON is asserted. The third switch SW3 is maintained on during the on-period of the high-side transistor M1. The charge control circuit 138B turns on the first switch SW1 after a certain delay time T _TIMER1 has elapsed since turning on the third switch SW3, and turns off the first switch SW1 after a predetermined time T _TIMER2 has elapsed since then. The charge control circuit 138B may include a timer circuit that measures the predetermined time T _TIMER1 , and may turn on the first switch SW1 while the timer circuit is performing a timer operation.

The turn-off circuit 136 reduces the voltage Vgate of the _gate of the high-side transistor M1 when the control signal CTRLH instructs the high-side transistor M1 to be turned off. The turn-off circuit 136 includes a second switch SW2 that is turned on during the period when the high-side off signal HOFF is asserted. The second switch SW2 is connected between the gate of the high-side transistor M1 and the ground. During the period when the switch SW2 is on, the charge of the gate capacitance of the high-side transistor M1 is discharged, the gate voltage _Vgate is reduced, and the high-side transistor M1 is turned off.

Figure 7 is an operational waveform diagram of the motor driver circuit 100B in Figure 6.

When the input signal IN goes high at time _t0 , the control signal S2 goes high and the third switch SW3 turns on, causing the power supply voltage V _CC to be supplied to the reference input node refin of the charge pump circuit 132B, and the output voltage V _CP of the charge pump circuit 132B quickly rises to the power supply voltage V _CC .

At time _t1 , a predetermined time _TTIMER1 has elapsed since time _t0 , the control signal S1 goes high, a clock signal Vclkin is supplied to the clock input node clkin of the charge pump circuit 132B, and the charge pump circuit 132B starts a charge pump operation. The charge pump operation causes the output voltage _VCP of the charge pump circuit 132B to rise to a maximum level Vgatemax. Thereafter, at time _t2 , a predetermined time _TTIMER2 has elapsed, the control signal S1 goes off, and the charge pump operation stops.

The above is the operation of the motor driver circuit 100B. According to this motor driver circuit 100B, in the period from time _t0 to _t1 , the gate voltage _Vgate of the high-side transistor M1 is quickly raised to the power supply voltage _Vcc , and then raised to the maximum level _Vgatemax by the charge pump operation. This allows the high-side transistor M1 to be turned on in a short time. In addition, the period during which the charge pump circuit 132B performs the charge pump operation can be shortened, thereby further reducing power consumption.

The use of the charge pump circuit 300 is not limited to a motor driver circuit, but can be used in various driver circuits that drive N-channel high-side transistors. Furthermore, the use of the charge pump circuit 300 is not limited to driving high-side transistors, but can be used in various integrated circuits that require a voltage higher than the power supply voltage V _CC .

(Additional Note)
The present specification discloses the following techniques.

(Item 1)
an input line for receiving a first voltage;
An output line;
a first flying capacitor having a first end and a second end;
a second flying capacitor having a first end and a second end;
a first transistor having a first electrode connected to the output line, a second electrode connected to the second end of the first flying capacitor, and a control electrode connected to the second end of the second flying capacitor;
a second transistor having a first electrode connected to the output line, a second electrode connected to the second end of the second flying capacitor, and a control electrode connected to the second end of the first flying capacitor;
a third transistor having a first electrode connected to the input line, a second electrode connected to the second end of the first flying capacitor, and a control electrode connected to the second end of the second flying capacitor;
a fourth transistor having a first electrode connected to the input line, a second electrode connected to the second end of the second flying capacitor, and a control electrode connected to the second end of the first flying capacitor;
a driver circuit that applies a first pulse voltage, in which the first voltage is set to high and a second voltage that is lower than the first voltage by a predetermined voltage width to low, to the first end of the first flying capacitor in synchronization with a clock signal, and also applies a second pulse voltage, in which the first voltage is set to high and the second voltage is set to low, and which is in opposite phase to the first pulse voltage, to the first end of the second flying capacitor;
and integrated on a single semiconductor substrate.

(Item 2)
The driver circuit includes:
a voltage source that generates a second voltage that is lower than the first voltage by the predetermined voltage width;
a first inverter having an upper power supply terminal connected to the input line and a lower power supply terminal connected to the output of the voltage source;
a second inverter having an upper power supply terminal connected to the input line and a lower power supply terminal connected to the output of the voltage source;
2. The charge pump circuit of claim 1, comprising:

(Item 3)
The voltage source is
An output node;
a Zener diode provided between the input line and the output node;
3. The charge pump circuit of claim 2, comprising:

(Item 4)
4. The charge pump circuit of claim 3, wherein the voltage source further includes a diode connected in series with the Zener diode between the input line and the output node.

(Item 5)
3. The charge pump circuit of claim 2, wherein the voltage source includes a linear regulator.

(Item 6)
a logic circuit that generates a control signal that instructs turning on and off the high-side transistor;
a high-side driver that drives the high-side transistor in response to the control signal;
Equipped with
The high side driver is
The charge pump circuit according to any one of items 1 to 5, wherein the output line is connected to a gate of the high-side transistor, the charge pump circuit generates a boost voltage in response to a clock signal, and supplies the boost voltage to the gate of the high-side transistor;
a charge control circuit that operates the charge pump circuit in response to the control signal transitioning to an on state instructing the high-side transistor to be on;
a turn-off circuit that reduces a voltage of the gate of the high-side transistor when the control signal instructs the high-side transistor to be turned off;
A motor driver circuit comprising:

100 Motor driver circuit M1 High side transistor M2 Low side transistor 110 Oscillator 120 Logic circuit 130 High side driver 132 Charge pump circuit 136 Turn-off circuit 138 Charging control circuit 140 Low side driver SW1 First switch SW2 Second switch SW3 Third switch 300 Charge pump circuit 302 Input line 304 Output line M11 First transistor M12 Second transistor M13 Third transistor M14 Fourth transistor Cf1 First flying capacitor Cf2 Second flying capacitor 320 Driver circuit 322 First inverter 324 Second inverter 326 Voltage source 328 Level shifter 400 Semiconductor integrated circuit 410 Oscillator 420 Load circuit

Claims (6)

an input line for receiving a first voltage;
An output line;
a first flying capacitor having a first end and a second end;
a second flying capacitor having a first end and a second end;
a first transistor having a first electrode connected to the output line, a second electrode connected to the second end of the first flying capacitor, and a control electrode connected to the second end of the second flying capacitor;
a second transistor having a first electrode connected to the output line, a second electrode connected to the second end of the second flying capacitor, and a control electrode connected to the second end of the first flying capacitor;
a third transistor having a first electrode connected to the input line, a second electrode connected to the second end of the first flying capacitor, and a control electrode connected to the second end of the second flying capacitor;
a fourth transistor having a first electrode connected to the input line, a second electrode connected to the second end of the second flying capacitor, and a control electrode connected to the second end of the first flying capacitor;
a driver circuit that applies a first pulse voltage, in which the first voltage is set to high and a second voltage that is lower than the first voltage by a predetermined voltage width to low, to the first end of the first flying capacitor in synchronization with a clock signal, and also applies a second pulse voltage, in which the first voltage is set to high and the second voltage is set to low, and which is in opposite phase to the first pulse voltage, to the first end of the second flying capacitor;
and integrated on a single semiconductor substrate. The driver circuit includes:
a voltage source that generates a second voltage that is lower than the first voltage by the predetermined voltage width;
a first inverter having an upper power supply terminal connected to the input line and a lower power supply terminal connected to the output of the voltage source;
a second inverter having an upper power supply terminal connected to the input line and a lower power supply terminal connected to the output of the voltage source;
2. The charge pump circuit of claim 1, comprising: The voltage source is
An output node;
a Zener diode provided between the input line and the output node;
3. The charge pump circuit of claim 2, comprising: The charge pump circuit of claim 3, wherein the voltage source further includes a diode connected in series with the Zener diode between the input line and the output node. The charge pump circuit of claim 2, wherein the voltage source includes a linear regulator. a logic circuit that generates a control signal that instructs turning on and off the high-side transistor;
a high-side driver that drives the high-side transistor in response to the control signal;
Equipped with
The high side driver is
a charge pump circuit according to any one of claims 1 to 5, wherein the output line is connected to a gate of the high-side transistor, the charge pump circuit generates a boosted voltage in response to a clock signal, and supplies the boosted voltage to the gate of the high-side transistor;
a charge control circuit that operates the charge pump circuit in response to the control signal transitioning to an on state instructing the high-side transistor to be on;
A motor driver circuit comprising:

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