JP2024106734A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

[Problem] To provide a semiconductor device intercalated with a two-dimensional metal. [Solution] The semiconductor device includes GaN with a hexagonal wurtzite structure. At least a part of the GaN includes a specific region. In the specific region, a plurality of Mg sheets parallel to the c-plane of the GaN are arranged. The plurality of Mg sheets are arranged apart from each other in the c-axis direction of the GaN. One or more atomic layers of GaN are arranged between adjacent Mg sheets. [Selected Figure] FIG.

Description

The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the semiconductor device.

Intercalation technology is an important technique for creating artificial layered structures. Related technology is disclosed in Non-Patent Document 1.

M. Rajapakse, B. Karki, U. O. Abu et al. Intercalation as a versatile tool for fabrication, property tuning, and phase transitions in 2D materials. npj 2D Mater Appl 5, 30 (2021).

This specification proposes a semiconductor device and a method for manufacturing the semiconductor device using two-dimensional metal intercalation into the semiconductor.

One aspect of the semiconductor device disclosed in this specification is a semiconductor device comprising GaN with a hexagonal wurtzite structure. At least a portion of the GaN comprises a specific region. In the specific region, multiple Mg sheets parallel to the c-plane of the GaN are arranged. The multiple Mg sheets are arranged spaced apart from each other in the c-axis direction of the GaN. One or more atomic layers of GaN are arranged between adjacent Mg sheets.

The above semiconductor device has a nanostructure in which Mg sheets are intercalated every few GaN atomic layers. This novel nanostructure can improve various semiconductor properties and has a wide range of potential applications, including exfoliation of two-dimensional materials, energy storage, superconductivity, and thermal conductivity control.

GaN has a periodic stacking structure represented by ABAB in the c-axis direction. Mg sheets may be intercalated in the interstitial sites between adjacent AB structures.

Uniaxial compressive strain in the c-axis direction may occur between adjacent Mg sheets in the c-axis direction.

Within the region of GaN sandwiched between adjacent Mg sheets, biaxial tensile strain in the c-plane may occur.

In the specific region, at least two GaN atomic layers that are located on opposite sides of the Mg sheet and are closest to the Mg sheet may have opposite polarities. The opposite polarities may be +c (metal polarity) and -c (nitrogen polarity).

The specific region may be located near one surface of the GaN. The width of the Mg sheet in a direction parallel to the c-plane may decrease in a direction perpendicular to the c-plane.

The GaN may have a p-type region that has been converted to p-type. The semiconductor device may have an electrode in contact with the p-type region. A Mg sheet may be present at the interface between the p-type region and the electrode.

The semiconductor device may include a first semiconductor layer made of GaN. The semiconductor device may include a second semiconductor layer that is disposed in contact with the lower surface of the first semiconductor layer and has a band gap different from that of GaN. The semiconductor device may include a first source electrode disposed above the first semiconductor layer. The semiconductor device may include a first drain electrode disposed above the first semiconductor layer and spaced apart from the first source electrode. The semiconductor device may include a first gate electrode disposed between the first source electrode and the first drain electrode and above the first semiconductor layer, or disposed in contact with the upper surface of the second semiconductor layer. The entire first semiconductor layer may include a specific region.

The semiconductor device may include a first semiconductor layer made of GaN. The semiconductor device may include a second semiconductor layer arranged in contact with the lower surface of the first semiconductor layer and having a band gap different from that of GaN. The semiconductor device may include a third semiconductor layer arranged in contact with the lower surface of the second semiconductor layer and made of GaN. The semiconductor device may include a second source electrode arranged on the upper surface of the second semiconductor layer. The semiconductor device may include a second drain electrode arranged on the upper surface of the second semiconductor layer and spaced apart from the second source electrode. The semiconductor device may include a second gate electrode provided above the first semiconductor layer and between the second source electrode and the second drain electrode. The entire first semiconductor layer may include a specific region.

The semiconductor device may include a first semiconductor layer made of GaN. The semiconductor device may include a second semiconductor layer that is disposed in contact with the lower surface of the first semiconductor layer and has a band gap different from that of GaN. The semiconductor device may include a third semiconductor layer that is disposed in contact with the lower surface of the second semiconductor layer and is made of GaN. The semiconductor device may include a first source electrode that is disposed above the first semiconductor layer. The semiconductor device may include a first drain electrode that is disposed above the first semiconductor layer and spaced apart from the first source electrode. The semiconductor device may include a first gate electrode that is disposed between the first source electrode and the first drain electrode and above the first semiconductor layer, or that is disposed in contact with the upper surface of the second semiconductor layer. The semiconductor device may include a second source electrode that is disposed on the upper surface of the second semiconductor layer. The semiconductor device may include a second drain electrode that is disposed on the upper surface of the second semiconductor layer and spaced apart from the second source electrode. The semiconductor device may include a second gate electrode that is disposed above the first semiconductor layer and between the second source electrode and the second drain electrode. The entire first semiconductor layer may include a specific region.

The semiconductor device may include a first semiconductor layer made of GaN. The semiconductor device may include a fourth semiconductor layer made of InGaN, which is disposed in contact with an upper surface of the first semiconductor layer. The entire first semiconductor layer may include the specific region.

One aspect of the method for manufacturing a semiconductor device disclosed herein includes a first step of preparing a GaN layer having a hexagonal wurtzite structure. The method includes a second step of depositing a thin Mg film on one side of the GaN layer. During or after the second step, the GaN layer is heated at a temperature greater than 500°C and less than 1050°C.

The first step may include a step of forming a GaN layer by epitaxial growth. The first step and the second step may be performed alternately. In the first step performed after the second step, a GaN layer may be formed on one side of the Mg thin film. The thickness of the Mg thin film formed in the second step may be smaller than the thickness of the GaN layer formed in the first step.

In the first and second steps, deposition may be performed by molecular beam epitaxy.

The deposition temperature in the molecular beam epitaxy method may be in the range of 600-700°C.

The method may include a step of forming a first semiconductor layer made of GaN. The method may include a step of forming a second semiconductor layer that is disposed in contact with an upper surface of the first semiconductor layer and has a band gap different from that of GaN. The method may include a step of forming a third semiconductor layer that is disposed in contact with an upper surface of the second semiconductor layer by alternately repeating the first and second steps. The method may include a step of forming a source electrode and a drain electrode above the third semiconductor layer. The method may include a step of forming a gate electrode between the source electrode and the drain electrode and above the third semiconductor layer or at a position on the upper surface of the second semiconductor layer.

1 is a STEM image of a MiGs nanostructure. 1 is an EDS spectrum of the MiGs nanostructure. 13 is an EDS map of the MiGs nanostructure. 1 is a schematic cross-sectional view illustrating the process of forming a MiGs nanostructure on a c-plane. 1 is a STEM image of a MiGs nanostructure formed on the c-plane. 1 is a schematic cross-sectional view illustrating a process of forming an MiGs nanostructure on an m-plane. 1 is a STEM image of a MiGs nanostructure formed on an m-plane. FIG. 1 is a schematic cross-sectional view of a MiGs nanostructure fabricated by a top-down method. FIG. 1 is a schematic cross-sectional view of a MiGs nanostructure fabricated by a bottom-up method. 1 is a table showing the basic material composition of GaN and Mg. FIG. 1 is a schematic diagram of the MiGs nanostructure. Elastic strain mapping performed on the STEM image. 13 is an image of the edge region of the MiGs nanostructure. FIG. 2 is a schematic diagram of an atomic arrangement of GaN. FIG. 1 is a schematic cross-sectional view of a pn junction diode 1 with MiGs nanostructures. 2 is a graph showing the IV characteristics of the pn junction diode 1. 1 is a graph showing the current density-voltage (JV) characteristics and on-resistance of a pn junction diode 1. FIG. 11 is a schematic cross-sectional view of a semiconductor device 2 according to a fourth embodiment. FIG. 11 is a schematic cross-sectional view of a substrate 40 according to a fifth embodiment.

(Overview of MiGs nanostructure)
The outline of the Mg intercalated GaN superlattice nanostructure will be described with reference to Figs. 1 to 3. Hereinafter, "Mg intercalated GaN superlattice" may be abbreviated as MiGs (Mg intercalated GaN superlattices). In Figs. 1(a) to 1(e), the upward direction of the paper is the c-axis direction of GaN with a hexagonal wurtzite structure. Figs. 1(a) to 1(c) are images at different magnifications taken with a high-angle annular dark-field scanning transmission electron microscope (HAADF-STEM). In Figs. 1(a) to 1(c), the dark lines extending in a direction parallel to the c-plane (left-right direction of the paper) are Mg sheets. The bright bands with a thickness of about 6 atoms existing between the Mg sheets are GaN. Fig. 1(d) is an atomic resolution integrated differential phase contrast (iDPC) STEM image showing the relative positions of N, Ga, and Mg atoms. FIG. 1( e ) is a schematic diagram of the repeating unit of the MiGs nanostructure.

Figure 2(a) shows a magnified image of a superlattice in which seven monolayers of GaN are arranged between Mg sheets. The right side of the page is the [0001] direction (c-axis direction). The scale bar is 500 pm. Figure 2(b) shows an atomically resolved EDS spectrum in the area indicated by the arrow in Figure 2(a). The positions of the intensity peaks indicate the relative positions of the atomic planes of the elements Ga, N, and Mg. Figures 3(a) to 3(c) are atomic resolution EDS maps of the same region as Figure 2. Figure 3(a) shows the distribution of Ga, Figure 3(b) shows the distribution of N, and Figure 3(c) shows the distribution of Mg.

As can be seen from Figures 1 to 3, the MiGs nanostructure can be formed in at least a specific region of GaN with a hexagonal wurtzite structure. In the specific region, multiple Mg sheets parallel to the c-plane of GaN are arranged. The multiple Mg sheets are arranged spaced apart from each other in the c-axis direction of GaN. One or more atomic layers of GaN are arranged between adjacent Mg sheets.

Now, let us explain about the Mg sheet. As shown in FIG. 1(e), GaN has a periodic stacking structure represented by ABAB in the c-axis direction. The Mg sheet is intercalated at the C position (interstitial site) between adjacent AB structures. Also, from FIG. 1 to FIG. 3, it can be seen that the Mg sheet has a thickness of one atomic layer. In other words, the Mg sheet has a two-dimensional shape. Since the Mg sheet penetrates between the lattices, it does not replace Ga atoms. Therefore, the Mg that constitutes the Mg sheet does not function as an acceptor. Also, in the MiGs nanostructure, the GaN layer behaves more dominantly than the Mg sheet. Therefore, the MiGs nanostructure functions as a semiconductor.

(Method for manufacturing MiGs nanostructures (top-down method))
A method for forming a MiGs nanostructure by the top-down method will be described. The top-down method is a method for thermally diffusing Mg from the surface of a GaN crystal. First, a GaN layer with a hexagonal wurtzite structure is prepared. Then, an amorphous Mg thin film is formed on one side of the GaN layer. Then, the GaN layer is heated at a temperature higher than 500° C. and lower than 1050° C. This allows spontaneous interdiffusion of Mg into GaN at high temperature and atmospheric pressure. As a result, intercalation of a two-dimensional metal into a semiconductor can be generated.

The process of forming a MiGs nanostructure on the c-plane will be explained using the schematic cross-sectional view of Figure 4. An Mg source 32 is placed on the c-plane of the GaN layer 31. When annealing is started in this state, in the initial stage, Mg diffuses from the surface to the inside of the GaN layer 31 (see Figure 4(a)). In Figure 4(a), Mg atoms are shown as dots. The Mg concentration decreases as you move from the surface of the GaN layer 31 toward the inside.

By continuing the annealing, the multiple Mg sheets 33 are self-organized, spaced apart from each other in the c-axis direction (see FIG. 4(b)). This completes the MiGs nanostructure. At this time, the region in which the MiGs nanostructure is formed is typically pyramidal. The pyramidal shape is such that the width of the Mg sheet 33 in the direction parallel to the c-plane narrows as it progresses in a direction perpendicular to the surface of the GaN layer 31 and toward the inside (i.e., in a direction perpendicular to the c-plane). The pyramidal shape is also such that the multiple Mg sheets 33 are arranged approximately symmetrically with respect to the central axis CA.

The mechanism by which the pyramidal shapes self-organize will be explained. The Mg sheet can be treated as a finite plane of positive charge. The Coulomb field induced by the Mg sheet is weak around the edges of the finite Mg sheet and becomes stronger toward the center. In addition, the Mg concentration decreases from the surface of the GaN layer 31 toward the inside, so the width of the Mg sheet becomes narrower toward the inside. As a result, the pyramidal shapes self-organize to reduce the total energy.

Figure 5 shows an STEM image of the MiGs nanostructure formed on the c-plane. The top of the page is the c-axis direction. Figure 5(a) is an ADF-STEM image. The square on the left side of Figure 5(a) shows the typical pyramid structure shown in Figure 4(b). Figure 5(b) is an HAADF-STEM image that is an enlarged view of the square part on the right side of Figure 5(a). In Figure 5(b), multiple Mg sheets are observed as dark lines. This confirmed that a MiGs nanostructure had been formed.

The process of forming a MiGs nanostructure on the m-plane will be explained using the schematic cross-sectional view of Figure 6. An Mg source 32 is placed on the m-plane of the GaN layer 31. When annealing is started in this state, in the initial stage, Mg diffuses from the surface to the inside of the GaN layer 31 (see Figure 6(a)). By continuing the annealing further, multiple Mg sheets 33 are self-organized, spaced apart from each other in the c-axis direction (see Figure 6(b)). In Figure 6(b), there are also parts where the width of the Mg sheet 33 in the direction parallel to the c-plane narrows as it progresses in the direction perpendicular to the c-plane.

Figure 7 shows an STEM image of the MiGs nanostructure formed on the m-plane. The top of the page is the m-axis direction, and the left side of the page is the c-axis direction. Figure 7(a) is an ADF-STEM image. Figure 7(b) is an HAADF-STEM image that is an enlarged view of the square area on the right side of Figure 7(a). In Figure 7(b), multiple Mg sheets are observed as dark lines. This confirmed that a MiGs nanostructure had been formed.

From the above, it can be seen that whether Mg is diffused from the c-plane or the m-plane, multiple Mg sheets are formed parallel to the GaN c-plane ((0001) plane). Here is the reason why. The (0001) plane is the plane with the highest atomic density for both GaN and Mg. And close-packed planes have higher binding energy and therefore lower surface energy. This is thought to create a strong tendency for Mg atoms to intercalate along the GaN (0001) plane.

(Method for manufacturing MiGs nanostructures (bottom-up method))
A method for forming a MiGs nanostructure by the bottom-up method will be described. The bottom-up method is a method for alternately stacking a GaN layer and an Mg layer. In the bottom-up method, a first step and a second step are alternately performed by molecular beam epitaxy (MBE).

The first step is to form a GaN layer by epitaxial growth. Specifically, the Ga shutter and the nitrogen shutter are opened, and the Mg shutter is closed. The number of layers of one atomic layer of GaN can be controlled by the deposition time. In other words, the average number of one atomic layers of GaN arranged between the Mg sheets can be controlled by time.

The second step is a step of depositing an Mg layer. Specifically, the Ga shutter and the nitrogen shutter are closed, and the Mg shutter is opened. This allows a monoatomic layer of Mg to be deposited. In other words, the thickness of the Mg layer deposited in the second step is smaller than the thickness of the GaN layer deposited in the first step.

In the first step, which is performed after the second step, a GaN layer is formed on the surface of the Mg thin film. Thereafter, by alternately repeating the first and second steps, it is possible to deposit one atomic layer of Mg on several atomic layers of GaN. Then, the film formation temperature (500-900°C) of the molecular beam epitaxy method can cause spontaneous interdiffusion of Mg into GaN. Therefore, it is possible to simultaneously proceed with the formation of the GaN layer and Mg layer and the self-organization of the MiGs nanostructure. The total thickness of the MiGs nanostructure can also be controlled by the number of times the first and second steps are repeated.

The reason for forming the film by molecular beam epitaxy is explained below. If annealing is performed at a temperature higher than 1050°C, Mg atoms will begin to diffuse into the GaN lattice, causing the MiGs nanostructure to decompose. For example, if film formation is performed by MOVPE, the film formation temperature (1000-1100°C) is too high, causing the MiGs nanostructure to decompose. Therefore, by using molecular beam epitaxy, the film can be formed within a thermodynamically favorable range (500-900°C) for the formation of the MiGs nanostructure. This prevents the decomposition of the MiGs nanostructure, and allows annealing to be performed during film formation to self-organize the MiGs nanostructure.

8 and 9 show schematic cross-sectional views of the MiGs nanostructures created by the top-down method and the bottom-up method, respectively. In Figs. 8 and 9, the Mg sheet is indicated by a black line. The MiGs nanostructures formed by the top-down method (Fig. 8) are formed only near the surface of the GaN layer. The MiGs nanostructures are characterized by uneven distribution in the depth direction and large surface roughness. This is thought to be due in part to the random and elementary reaction between the amorphous Mg thin film and bulk GaN during the formation of the MiGs nanostructures. On the other hand, the MiGs nanostructures created by the bottom-up method (Fig. 9) can have a uniform distribution in the depth direction and small surface roughness. In addition, the thickness of the MiGs nanostructure can be set arbitrarily by the number of times the film is formed, so it is possible to form a large-scale MiGs nanostructure in the depth direction.

(Key elements for spontaneous formation of MiGs nanostructures)
The basic material composition of GaN and Mg is shown in the table in Figure 10. GaN and Mg have the same crystal structure (HCP). They also have almost the same lattice constant, with a lattice mismatch of 0.2%, which is within the margin of error. This small lattice mismatch makes it possible to spontaneously form a defect-free superlattice structure, as described above.

In addition, MiGs nanostructures are formed by spontaneous interdiffusion of Mg into GaN at high temperatures and atmospheric pressure. Therefore, MiGs nanostructures are thermodynamically stable under a wide range of conditions.

(Strain control using MiGs nanostructures)
By changing the average number of GaN monolayers between the two-dimensional Mg sheets, strain control to GaN can be applied in the MiGs nanostructure. FIG. 11 shows a schematic diagram of the MiGs nanostructure. The circles indicate Ga atoms, and the triangles indicate Mg atoms. As shown in FIG. 11, a pair of two-dimensional Mg sheets can be intercalated into K atomic layers (K is a natural number of 2 or more) of GaN to narrow the spacing between the atomic layers in the c-axis direction. The smaller K is, the larger the uniaxial compressive strain in the c-axis direction can be inversely proportional to the K. When K is 5 or 6, the uniaxial compressive strain in the c-axis direction can be increased to -10% or more.

Figure 12 shows elastic strain mapping performed on an atomic resolution HAADF-STEM image. It shows the out-of-plane strain (uniaxial strain) of the MiGs nanostructure. The dark atomic layer is the Mg sheet. Six atomic layers of GaN are arranged between the Mg sheets. The elastic strain mapping indicates that the darker the color, the greater the compressive strain. As can be seen from Figure 12, it is possible to generate uniaxial compressive strain in the c-axis direction.

Problems that can be solved by strain control are explained below. In III-nitrides such as GaN, the effective mass of holes is very large due to the strong electron affinity of nitrogen atoms and weak spin-orbit interaction. Therefore, there was a problem that the hole mobility and hole transport in the device were limited. On the other hand, when uniaxial compressive strain in the c-axis direction is generated in the wurtzite GaN lattice, the valence band structure is inverted (the crystal field splitting energy becomes negative), and the split hole band with a light hole effective mass is raised to the valence band maximum (VBM). The presence of many holes in this split-off hole band improves the hole mobility. Specifically, it has been theoretically calculated by rigorous first-principles calculation that when a uniaxial compressive strain of -4.3% is applied to the c-axis direction of wurtzite GaN, a hole mobility of about 200 cm ² /(V·s), which is one order of magnitude higher than conventional methods, can be obtained at room temperature. However, because it has been very difficult to introduce high strain into the GaN lattice, the enhancement of hole mobility by inverting the crystal field splitting energy has long been awaited.

The technology described herein uses a MiGs nanostructure to generate uniaxial compressive strain in the c-axis direction in the wurtzite GaN lattice. This makes it possible to simultaneously achieve high hole mobility and high hole concentration. In addition, by using the bottom-up method described above, a large-scale, uniform MiGs nanostructure can be formed. This makes it possible to form p-type GaN with high hole mobility over a wide area and uniformly.

(Polarity reversal by MiGs nanostructure)
The MiGs nanostructure allows the polarity of GaN to be inverted. Figure 13 shows images of the edge region of the MiGs nanostructure. Figure 13(A) is a HAADF-STEM image. Figure 13(B) is an iDPC-STEM image of the same region as Figure 13(A). Figure 13(C) is a partially enlarged view of the iDPC-STEM image and a schematic diagram of the atomic arrangement. iDPC imaging allows the resolution of nitrogen atoms, which are normally invisible. Thus, the relative atomic positions of Ga and N can be directly revealed, as shown in Figure 13(C).

The 2D Mg sheet inserted into the GaN can be treated as a uniform plane of positive charge. The resulting Coulomb field affects the surroundings by reversing the polarity of the GaN near the Mg sheet. As shown in Figure 13(C), a polarity reversal from N-pole to Ga-pole occurs around region A0, which is a few atoms away laterally (parallel to the c-plane) from the edge of the 2D Mg sheet.

Figure 14 shows a schematic diagram of the atomic arrangement of GaN sandwiched between two-dimensional Mg sheets. In the intermediate region IR of the GaN sandwiched between the Mg sheets, polarity inversion occurs in a direction perpendicular to the c-plane. This polarity inversion can be generated over a distance of about a few atoms. This spatial change in the polarization field induces extra bulk doping of holes in the intermediate region IR. This makes it possible to further increase the hole concentration.

Here, we focus on two GaN atomic layers AL1 and AL2, which are located on opposite sides of the Mg sheet and are the layers closest to the Mg sheet. The GaN atomic layer AL1 is of +c (metal polarity) type, and the GaN atomic layer AL2 is of -c (nitrogen polarity) type. In other words, the GaN atomic layers AL1 and AL2 have opposite polarities.

(Contact Structure with MiGs Nanostructure)
An example of applying the MiGs nanostructure to a contact structure between a semiconductor and a metal electrode will be described. First, a single-crystal GaN layer with a p-type region on its surface was prepared. Next, a thin Mg film was formed on the surface (c-plane) of the p-type region. Then, the MiGs nanostructure was formed on the surface of the p-type region by annealing (top-down method). At this time, two samples were created, each annealed under low-temperature conditions (500°C, 600s) and high-temperature conditions (550°C, 600s). After removing the Mg remaining on the surface of the MiGs nanostructure, an electrode for a TLM (transfer length method) test structure was formed on the surface of the MiGs nanostructure. This completed a structure in which a MiGs nanostructure with an Mg sheet was present at the interface between the p-type region and the electrode. Then, the current density-voltage (J-V) characteristics were evaluated.

In the low-temperature sample, non-ohmic contact characteristics were obtained. On the other hand, in the high-temperature sample, good ohmic contact characteristics with completely linear IV characteristics were obtained. In addition, the contact resistance was very low, on the order of 10 ⁻⁵ Ω·cm ⁻² . From the above, it can be seen that ohmic contact can be realized and the contact resistance can be made very low by disposing a metal electrode via a MiGs nanostructure. It can also be seen that the annealing temperature for enabling ohmic contact has a threshold value between 500° C. and 550° C. In other words, in order to realize ohmic contact using a MiGs nanostructure, annealing at a temperature higher than 500° C. is necessary.

(Diode with MiGs nanostructure)
An example of applying a contact structure having a MiGs nanostructure to a diode will be described. FIG. 15 shows a schematic cross-sectional view of a pn junction diode 1 having a MiGs nanostructure. The pn junction diode 1 has a structure in which a back cathode electrode 10, an n ⁺ -GaN substrate 11, an n ^- -GaN layer 12, a p-GaN layer 13, a MiGs nanostructure layer 14, and an anode electrode 15 are laminated in this order. The lamination direction is the c-axis direction. The n ⁺ -GaN substrate 11 has a thickness of 400 μm and an electron density of up to 10 ¹⁸ cm ^-3 . The n ^- -GaN layer 12 has a thickness of 2.5 μm and a Si concentration of 7×10 ¹⁶ cm ^-3 . The p-GaN layer 13 has a thickness of 280 nm and a Mg concentration of 7×10 ¹⁸ cm ^-3 . The p-GaN layer 13 can be formed by epitaxial growth doped with Mg. After the p-GaN layer 13 is formed, activation annealing at 1000° C. or higher may be performed.

The MiGs nanostructure layer 14 was created using the top-down method described above. Specifically, Mg was deposited on the surface of the p-GaN layer 13. The MiGs nanostructure layer 14 was then formed on the surface of the p-GaN layer 13 by annealing within the range of 500-1050°C.

Figure 16 shows the I-V characteristics of the pn junction diode 1. Curve C0 is the I-V curve of a comparative example diode that does not have a MiGs nanostructure layer. Curve C1 is the I-V curve of the pn junction diode 1 of this embodiment that has a MiGs nanostructure layer. The graph inserted in Figure 16 shows the ideality factor n in the vicinity of the turn-on voltage of the pn junction diode 1 of this embodiment. The ideality factor is a coefficient that evaluates the quality of the pn junction, and is ideally 1, and when the crystallinity is poor, it is a value close to 2. Figure 17 shows the current density-voltage (J-V) characteristics and on-resistance of the pn junction diode 1 of this embodiment. The graph inserted in Figure 17 is the I-V characteristic curve in the vicinity of the turn-on voltage plotted on a linear scale.

It can be seen from Fig. 16 that the forward current is significantly improved by providing the MiGs nanostructure layer. The ideality factor n is 1.3, which is a good value close to 1. It can also be seen from Fig. 17 that the current density is about 1 kA/ ^cm2 at 3.5 V (see region A1), and good characteristics are obtained. The on-resistance also decreases from 1.9 mΩ· ^cm2 to 0.3 mΩ· ^cm2 , and good characteristics are obtained (see region A2).

These improvements in characteristics are believed to be due to enhanced transport of holes in the vertical direction (c-axis direction) through a combination of reduced contact resistance and improved hole density and hole mobility. In addition, the fact that hole transport in the c-axis direction (i.e., the direction perpendicular to the multiple Mg sheets) can be enhanced shows that the presence of the Mg sheets does not impede carrier transport in GaN.

(Mg doping with MiGs nanostructure)
The diffusion of Mg to form the MiGs nanostructure is interstitial, whereas the diffusion of Mg to make GaN p-type is substitutional. Interstitial diffusion has a lower activation energy than substitutional diffusion. Therefore, the most effective temperature range for forming the MiGs nanostructure (550-900°C) is lower than the temperature range for forming p-type GaN (above 1000°C).

When the MiGs nanostructure is annealed at a sufficiently high temperature (1050°C or higher), the aligned Mg atoms begin to move randomly. This promotes substitutional diffusion. The Mg atoms substitute for Ga sites, and the Mg functions as an acceptor, making the GaN p-type.

In the MiGs nanostructure, multiple Mg sheets are arranged at a distance from each other in the c-axis direction. In other words, it is a structure in which a very large amount of Mg atoms are uniformly and widely distributed. This MiGs nanostructure can be used to dope Mg, making high-concentration and uniform doping possible. The MiGs nanostructure can function as an ideal doping source.

The conductivity type of the GaN doped with Mg using the MiGs nanostructure is not particularly limited. It is also possible to convert i-type GaN to p-type, or n-type GaN to p-type.

(CMOS structure with MiGs nanostructure)
An example of applying the MiGs nanostructure to a CMOS structure will be described. Fig. 18 shows a schematic cross-sectional view of a semiconductor device 2. The semiconductor device 2 is a lateral CMOS, and includes a PMOS 3 and an NMOS 4. The PMOS 3 and the NMOS 4 are formed on a common support substrate 20.

The first semiconductor layer 21 is p-type GaN, and the entire layer is composed of a uniform MiGs nanostructure. The first semiconductor layer 21 can be formed by the bottom-up method described above. The second semiconductor layer 22 is disposed in contact with the lower surface of the first semiconductor layer 21. The second semiconductor layer 22 has a band gap different from that of GaN. In this embodiment, the second semiconductor layer 22 is AlGaN. The third semiconductor layer 23 is disposed in contact with the lower surface of the second semiconductor layer 22. The third semiconductor layer 23 is GaN. In this embodiment, the third semiconductor layer 23 is n-type. The support substrate 20 is disposed in contact with the lower surface of the third semiconductor layer 23. The material of the support substrate 20 may be various, and for example, GaN, Si, sapphire, etc. can be used. The PMOS 3 and the NMOS 4 are separated by a separation region 24. The separation region 24 is an insulator, and for example, silicon oxide can be used.

The PMOS3 includes a first source electrode S1, a first drain electrode D1, and a first gate electrode G1. The first source electrode S1 is provided on the upper surface of the first semiconductor layer 21. The first drain electrode D1 is provided on the upper surface of the first semiconductor layer 21 and is disposed away from the first source electrode S1. The first gate electrode G1 is provided between the first source electrode S1 and the first drain electrode D1 and above the first semiconductor layer 21. As a modified example, a first gate electrode G1a shown by a dashed line may be used instead of the first gate electrode G1. The first gate electrode G1a is disposed in contact with the upper surface of the second semiconductor layer 22. The first gate electrode G1a does not have to be disposed between the first source electrode S1 and the first drain electrode D1.

The NMOS 4 includes a second source electrode S2, a second drain electrode D2, and a second gate electrode G2. The second source electrode S2 is disposed on the upper surface of the second semiconductor layer 22. The second drain electrode D2 is disposed on the upper surface of the second semiconductor layer 22, and is disposed apart from the second source electrode S2. The second gate electrode G2 is provided on the upper surface of the first semiconductor layer 21, and is provided between the second source electrode S2 and the second drain electrode D2.

The operation of NMOS4 will now be described. Induced by the heterojunction between the second semiconductor layer 22 and the third semiconductor layer 23, a high-mobility two-dimensional electron gas (2DEG) layer is formed at the heterointerface. This two-dimensional electron gas layer serves as a channel to allow an on-current to flow between the second source electrode S2 and the second drain electrode D2.

The operation of PMOS3 will now be described. Induced by the heterojunction between the first semiconductor layer 21 and the second semiconductor layer 22, a high-mobility two-dimensional hole gas (2DHG) layer is formed at the heterointerface. This two-dimensional hole gas layer serves as a channel to allow an on-current to flow between the first source electrode S1 and the first drain electrode D1.

(Method of Manufacturing Semiconductor Device 2)
First, a support substrate 20 is prepared. A third semiconductor layer 23 made of n-type GaN is epitaxially grown on the surface of the support substrate 20. A second semiconductor layer 22 made of AlGaN is epitaxially grown on the surface of the third semiconductor layer 23. A first semiconductor layer 21 having a MiGs nanostructure formed uniformly over the entire surface is grown on the surface of the second semiconductor layer 22. The first semiconductor layer 21 may be formed using the bottom-up method described above, and therefore a detailed description thereof will be omitted. This completes the substrate.

A trench is formed in the boundary region BR between PMOS3 and NMOS4 using well-known lithography and dry etching techniques. An insulating film is filled into the trench to form an isolation region 24. The first semiconductor layer 21 is removed in the region ER where the source electrode and drain electrode of NMOS4 are to be formed. Then, the first source electrode S1, the first gate electrode G1, the first drain electrode D1, the second drain electrode D2, the second gate electrode G2, and the second source electrode S2 are formed. This completes the semiconductor device 2 shown in FIG. 18.

(effect)
GaN, which is a wide band gap semiconductor, has a large difference in ionization energy between n-type impurities and p-type impurities, making it difficult to achieve the same free carrier concentration in both conductivity types. The characteristic difference between n-type and p-type semiconductors becomes large, which leads to deterioration of the characteristics of complementary CMOS circuits. Therefore, in the technology of this embodiment, the first semiconductor layer 21 can be fabricated using a MiGs nanostructure. By controlling the distortion of the MiGs nanostructure, high hole mobility and high hole concentration can be achieved, so that the same free carrier concentration and mobility can be achieved in both conductivity types. It becomes possible to realize a CMOS structure with good characteristics.

In PMOS3, a structure can be realized in which the first source electrode S1 and the first drain electrode D1 are in contact with the first semiconductor layer 21 having a MiGs nanostructure. Since the contact resistance can be significantly reduced, it is possible to improve the characteristics of PMOS3.

(Substrate for epitaxial growth with MiGs nanostructure)
An example of applying a substrate having a MiGs nanostructure to a substrate for epitaxial growth of InGaN will be described. Fig. 19 shows a schematic cross-sectional view of a substrate 40. The substrate 40 has a structure in which a support substrate 41, a buffer layer 42, a MiGs layer 43, a first InGaN layer 44, and a second InGaN layer 45 are stacked in this order. The stacking direction is the c-axis direction.

The material of the support substrate 41 may be various, for example, GaN, Si, sapphire, etc. can be used. The buffer layer 42 is a layer that relieves distortion due to lattice mismatch. The buffer layer 42 is, for example, GaN epitaxially grown on the support substrate 41. The MiGs layer 43 is GaN, and the entire layer is composed of a uniform MiGs nanostructure. The MiGs layer 43 can be formed by the bottom-up method described above. The first InGaN layer 44 is In _0.2 Ga _0.8 N epitaxially grown on the MiGs layer 43. The second InGaN layer 45 is In _{> 0.2} Ga _{< 0.8} N epitaxially grown on the first InGaN layer 44. The second InGaN layer 45 may have a stepwise higher In composition ratio toward the upper surface side.

When the MiGs nanostructure generates a uniaxial compressive strain in the c-axis direction, a biaxial tensile strain in the c-plane is generated inside the GaN region sandwiched between the Mg sheets. For example, a biaxial strain of +2.21% can be generated along with a uniaxial strain of -12.12%. The MiGs layer 43 having a biaxial strain of +2.2% is lattice-matched to a fully relaxed In _0.2 Ga _0.8 N (first InGaN layer 44). This allows the MiGs layer 43 to be used as an ideal substrate material for epitaxial growth of the first InGaN layer 44. This makes it possible to generate an LED substrate with little variation in In composition and including a quantum well with a high In composition. It is possible to improve the performance of the LED, such as improving the light-emitting efficiency.

The above-mentioned combination of biaxial strain value and In composition ratio is just one example. It is possible to adjust the biaxial strain value (i.e., the number of GaN atomic layers between Mg sheets) appropriately according to the In composition ratio of the InGaN to be epitaxially grown.

Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exert technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of those objectives is itself technically useful.

(Modification)
The thickness of the Mg sheet is not limited to one atomic layer of Mg, but may be two or more atomic layers.

The shape of the region in which the MiGs nanostructure is formed by the top-down method is not limited to a pyramid shape, and may be a variety of shapes. For example, the width of the Mg sheet in the c-plane direction may not change as it moves from the surface to the inside, and the number of Mg atoms may decrease.

In Example 4, an example of applying the MiGs nanostructure to a HEMT was described, but this is not the only possible application. The MiGs nanostructure can be applied to various device structures, such as MOS-FETs, PSJ (Polarization Superjunction)-FETs, and PSJ-SBDs (Schottky Barrier Diodes).

Aspects of the present technology are listed below.
[Aspect 1]
A semiconductor device comprising GaN having a hexagonal wurtzite structure,
At least a portion of the GaN has a specific region,
A plurality of Mg sheets parallel to the c-plane of the GaN are arranged in the specific region,
The Mg sheets are arranged apart from each other in the c-axis direction of the GaN,
One or more atomic layers of the GaN are disposed between the adjacent Mg sheets.
Semiconductor device.
[Aspect 2]
The GaN has a periodic stacking structure represented by ABAB in the c-axis direction,
2. The semiconductor device of claim 1, wherein the Mg sheets are intercalated into interstitial sites between adjacent AB structures.
[Aspect 3]
3. The semiconductor device according to claim 1, wherein a uniaxial compressive strain in the c-axis direction is generated between the Mg sheets adjacent in the c-axis direction.
[Aspect 4]
4. The semiconductor device according to aspect 3, wherein a biaxial tensile strain in a c-plane is generated inside a region of the GaN sandwiched between adjacent Mg sheets.
[Aspect 5]
In the specific region, at least two GaN atomic layers located on opposite sides of the Mg sheet and closest to the Mg sheet have opposite polarities,
The semiconductor device according to any one of Aspects 1 to 4, wherein the opposite polarities include a +c (metal polarity) type and a −c (nitrogen polarity) type.
[Aspect 6]
the specific region is disposed near one surface of the GaN;
The semiconductor device according to any one of aspects 1 to 5, wherein a width of the Mg sheet in a direction parallel to the c-plane decreases in a direction perpendicular to the c-plane.
[Aspect 7]
The GaN has a p-type region that is p-typed,
the semiconductor device includes an electrode in contact with the p-type region;
The semiconductor device according to any one of aspects 1 to 6, wherein the Mg sheet is present at an interface between the p-type region and the electrode.
[Aspect 8]
A first semiconductor layer made of GaN;
a second semiconductor layer disposed in contact with a lower surface of the first semiconductor layer and having a band gap different from that of the GaN;
a first source electrode provided above the first semiconductor layer;
a first drain electrode disposed above the first semiconductor layer and spaced apart from the first source electrode;
a first gate electrode provided between the first source electrode and the first drain electrode and above the first semiconductor layer, or disposed in contact with an upper surface of the second semiconductor layer;
Equipped with
The semiconductor device according to any one of Aspects 1 to 7, wherein the entire first semiconductor layer includes the specific region.
[Aspect 9]
A first semiconductor layer made of GaN;
a second semiconductor layer disposed in contact with a lower surface of the first semiconductor layer and having a band gap different from that of the GaN;
a third semiconductor layer made of GaN, the third semiconductor layer being disposed in contact with a lower surface of the second semiconductor layer;
a second source electrode disposed on an upper surface of the second semiconductor layer;
a second drain electrode disposed on an upper surface of the second semiconductor layer and spaced apart from the second source electrode;
a second gate electrode provided above the first semiconductor layer and between the second source electrode and the second drain electrode;
Equipped with
The semiconductor device according to any one of aspects 1 to 8, wherein the entire first semiconductor layer includes the specific region.
[Aspect 10]
A first semiconductor layer made of GaN;
a second semiconductor layer disposed in contact with a lower surface of the first semiconductor layer and having a band gap different from that of the GaN;
a third semiconductor layer made of GaN, the third semiconductor layer being disposed in contact with a lower surface of the second semiconductor layer;
a first source electrode provided above the first semiconductor layer;
a first drain electrode disposed above the first semiconductor layer and spaced apart from the first source electrode;
a first gate electrode provided between the first source electrode and the first drain electrode and above the first semiconductor layer, or disposed in contact with an upper surface of the second semiconductor layer;
a second source electrode disposed on an upper surface of the second semiconductor layer;
a second drain electrode disposed on an upper surface of the second semiconductor layer and spaced apart from the second source electrode;
a second gate electrode provided above the first semiconductor layer and between the second source electrode and the second drain electrode;
It is equipped with
The semiconductor device according to any one of Aspects 1 to 7, wherein the entire first semiconductor layer includes the specific region.
[Aspect 11]
A first semiconductor layer made of GaN;
a fourth semiconductor layer made of InGaN and disposed in contact with an upper surface of the first semiconductor layer;
Equipped with
The semiconductor device according to any one of Aspects 1 to 7, wherein the entire first semiconductor layer includes the specific region.
[Aspect 12]
A first step of providing a GaN layer having a hexagonal wurtzite structure;
a second step of depositing a thin Mg film on one surface of the GaN layer;
Equipped with
heating the GaN layer at a temperature greater than 500° C. and less than 1050° C. during or after the second step;
A method for manufacturing a semiconductor device.
[Aspect 13]
The first step includes a step of epitaxially growing the GaN layer,
The first step and the second step are performed alternately,
In the first step, which is performed after the second step, the GaN layer is formed on one surface of the Mg thin film;
The thickness of the Mg thin film formed in the second step is smaller than the thickness of the GaN layer formed in the first step.
13. The method according to claim 12.
[Aspect 14]
14. The manufacturing method according to aspect 13, wherein in the first step and the second step, film formation is performed by a molecular beam epitaxy method.
[Aspect 15]
15. The method according to claim 14, wherein the film formation temperature in the molecular beam epitaxy is in the range of 600-700° C.
[Aspect 16]
forming a first semiconductor layer composed of GaN;
forming a second semiconductor layer disposed in contact with a top surface of the first semiconductor layer, the second semiconductor layer having a bandgap different from that of the GaN;
forming a third semiconductor layer disposed in contact with an upper surface of the second semiconductor layer by alternately repeating the first step and the second step;
forming a source electrode and a drain electrode above the third semiconductor layer;
forming a gate electrode between the source electrode and the drain electrode and above the third semiconductor layer or on an upper surface of the second semiconductor layer;
16. The method of any one of Aspects 13-15, comprising:

2: Semiconductor device 3: PMOS 4: NMOS 20: Support substrate 21: First semiconductor layer 22: Second semiconductor layer 23: Third semiconductor layer S1: First source electrode S2: Second source electrode D1: First drain electrode D2: Second drain electrode G1: First gate electrode G2: Second gate electrode

Claims (16)

A semiconductor device comprising GaN having a hexagonal wurtzite structure,
At least a portion of the GaN has a specific region,
A plurality of Mg sheets parallel to the c-plane of the GaN are arranged in the specific region,
The Mg sheets are arranged apart from each other in the c-axis direction of the GaN,
One or more atomic layers of the GaN are disposed between the adjacent Mg sheets.
Semiconductor device. The GaN has a periodic stacking structure represented by ABAB in the c-axis direction,
The semiconductor device according to claim 1 , wherein the Mg sheets are intercalated into interstitial sites between adjacent AB structures. The semiconductor device according to claim 1, wherein uniaxial compressive strain in the c-axis direction occurs between the Mg sheets adjacent in the c-axis direction. The semiconductor device according to claim 3, wherein biaxial tensile strain in the c-plane is generated within the region of the GaN sandwiched between the adjacent Mg sheets. In the specific region, at least two GaN atomic layers located on opposite sides of the Mg sheet and closest to the Mg sheet have opposite polarities;
2. The semiconductor device according to claim 1, wherein the opposite polarities comprise a +c (metal polarity) type and a -c (nitrogen polarity) type. the specific region is disposed near one surface of the GaN;
2. The semiconductor device according to claim 1, wherein the width of said Mg sheet in a direction parallel to the c-plane decreases in a direction perpendicular to the c-plane. The GaN has a p-type region that is p-typed,
the semiconductor device includes an electrode in contact with the p-type region;
The semiconductor device according to claim 1 , wherein the Mg sheet is present at an interface between the p-type region and the electrode. A first semiconductor layer made of GaN;
a second semiconductor layer disposed in contact with a lower surface of the first semiconductor layer and having a band gap different from that of the GaN;
a first source electrode provided above the first semiconductor layer;
a first drain electrode disposed above the first semiconductor layer and spaced apart from the first source electrode;
a first gate electrode provided between the first source electrode and the first drain electrode and above the first semiconductor layer, or disposed in contact with an upper surface of the second semiconductor layer;
Equipped with
The semiconductor device according to claim 1 , wherein the entirety of the first semiconductor layer comprises the specific region. A first semiconductor layer made of GaN;
a second semiconductor layer disposed in contact with a lower surface of the first semiconductor layer and having a band gap different from that of the GaN;
a third semiconductor layer made of GaN, the third semiconductor layer being disposed in contact with a lower surface of the second semiconductor layer;
a second source electrode disposed on an upper surface of the second semiconductor layer;
a second drain electrode disposed on an upper surface of the second semiconductor layer and spaced apart from the second source electrode;
a second gate electrode provided above the first semiconductor layer and between the second source electrode and the second drain electrode;
Equipped with
The semiconductor device according to claim 1 , wherein the entirety of the first semiconductor layer comprises the specific region. A first semiconductor layer made of GaN;
a second semiconductor layer disposed in contact with a lower surface of the first semiconductor layer and having a band gap different from that of the GaN;
a third semiconductor layer made of GaN, the third semiconductor layer being disposed in contact with a lower surface of the second semiconductor layer;
a first source electrode provided above the first semiconductor layer;
a first drain electrode disposed above the first semiconductor layer and spaced apart from the first source electrode;
a first gate electrode provided between the first source electrode and the first drain electrode and above the first semiconductor layer, or disposed in contact with an upper surface of the second semiconductor layer;
a second source electrode disposed on an upper surface of the second semiconductor layer;
a second drain electrode disposed on an upper surface of the second semiconductor layer and spaced apart from the second source electrode;
a second gate electrode provided above the first semiconductor layer and between the second source electrode and the second drain electrode;
Equipped with
The semiconductor device according to claim 1 , wherein the entirety of the first semiconductor layer comprises the specific region. A first semiconductor layer made of GaN;
a fourth semiconductor layer made of InGaN and disposed in contact with an upper surface of the first semiconductor layer;
Equipped with
The semiconductor device according to claim 1 , wherein the entirety of the first semiconductor layer comprises the specific region. A first step of providing a GaN layer having a hexagonal wurtzite structure;
a second step of depositing a thin Mg film on one surface of the GaN layer;
Equipped with
heating the GaN layer at a temperature greater than 500° C. and less than 1050° C. during or after the second step;
A method for manufacturing a semiconductor device. The first step includes a step of epitaxially growing the GaN layer,
The first step and the second step are performed alternately,
In the first step, which is performed after the second step, the GaN layer is formed on one surface of the Mg thin film;
The thickness of the Mg thin film formed in the second step is smaller than the thickness of the GaN layer formed in the first step.
The method of claim 12. The manufacturing method according to claim 13, wherein the first and second steps are performed by molecular beam epitaxy. The manufacturing method according to claim 14, wherein the film formation temperature in the molecular beam epitaxy method is in the range of 600-700°C. forming a first semiconductor layer composed of GaN;
forming a second semiconductor layer disposed in contact with a top surface of the first semiconductor layer, the second semiconductor layer having a bandgap different from that of the GaN;
forming a third semiconductor layer disposed in contact with an upper surface of the second semiconductor layer by alternately repeating the first step and the second step;
forming a source electrode and a drain electrode above the third semiconductor layer;
forming a gate electrode between the source electrode and the drain electrode and above the third semiconductor layer or on an upper surface of the second semiconductor layer;
The method of claim 13, comprising:

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