JP2024073983A - Silicon carbide semiconductor device - Google Patents

Abstract

To provide a SiC semiconductor device in which the deterioration in yield can be suppressed.SOLUTION: An element separation region In includes a deep layer 15 formed in a surface layer part of a first impurity region 13, a base layer 21 formed on the deep layer 15, and a separation structure 40 that electrically separates the base layer 21 existing on a main cell region Rm side and the base layer 21 existing on a sense cell region Rs side. In the deep layer 15 of the element separation region In, a part existing on the main cell region Rm side and a part existing on the sense cell region Rs side are disposed apart from each other by a predetermined distance B3. The predetermined distance B3 is wider than distances B1 and B2 of the deep layer 15 in the cell region. The JFET layer 14 is formed in a region of the cell region 1 that is different from the element separation region In.SELECTED DRAWING: Figure 4

Description

The present invention relates to a silicon carbide (hereinafter also referred to as SiC) semiconductor device having a trench gate structure in which a cell region includes a main cell region and a sense cell region.

Conventionally, a SiC semiconductor device has been proposed in which a cell region is provided with a main cell region and a sense cell region, and the current flowing through the main cell region is detected in the sense cell region (see, for example, Patent Document 1). Specifically, in this SiC semiconductor device, MOSFET elements of the same structure are formed in the main cell region and the sense cell region. In addition, in this SiC semiconductor device, an element isolation region is provided between the main cell region and the sense cell region.

The main cell region and the sense cell region have a trench gate structure, and below the trench gate structure, a p-type deep layer and an n-type JFET layer are formed, extending in one direction as the longitudinal direction. The deep layers and JFET layers are alternately arranged along a direction intersecting the longitudinal direction, so that the JFET layers are arranged between adjacent deep layers.

In the element isolation region, a deep layer and a JFET layer similar to those in the main cell region are formed. The deep layer in the element isolation region is arranged such that the portion on the main cell region side and the portion on the sense cell region side are spaced a predetermined distance apart. In this SiC semiconductor device, the spacing between the deep layers in the element isolation region is narrower than the spacing between the deep layers in the main cell region, thereby improving the breakdown voltage of the element isolation region.

JP 2021-93481 A

However, the inventors conducted a detailed study of the spacing of the deep layers in the element isolation region of the above-mentioned SiC semiconductor device and confirmed the following. That is, it was confirmed that in the above-mentioned SiC semiconductor device, it is preferable to set the spacing of the deep layers in the element isolation region to 0.6 μm or less. In this case, if the deep layers are to be formed by ion implantation, the remaining width of the mask used during ion implantation must be set to 0.6 μm or less to match the spacing of the deep layers. For this reason, in the above-mentioned SiC semiconductor device, mask processing may become unstable, resulting in a deterioration in yield.

In view of the above, the present invention aims to provide a SiC semiconductor device that can suppress deterioration of yield.

Claim 1 for achieving the above object is a SiC semiconductor device in which a semiconductor element having a trench gate structure is formed in a cell region (1) including a main cell region (Rm) and a sense cell region (Rs), and the main cell region and the sense cell region are electrically isolated by an element isolation region (In), the device has a first conductivity type or second conductivity type substrate (11) made of SiC, and a first conductivity type first impurity region (13) formed on the surface of the substrate and having a lower impurity concentration than the substrate, and the main cell region and the sense cell region are formed in the surface layer of the first impurity region. The semiconductor device has a JFET layer (14) made of SiC of a first conductivity type having a higher impurity concentration than the first impurity region, a deep layer (15) made of SiC of a second conductivity type formed in a surface layer portion of the first impurity region and arranged alternately with the JFET layer in the surface direction of the substrate, a base layer (21) made of SiC of the second conductivity type formed on the JFET layer and the deep layer, a gate insulating film (25) formed on the inner wall surface of a trench (24) formed deeper than the base layer and with one direction as the longitudinal direction, and a gate electrode (26) formed on the gate insulating film in the trench. a second impurity region (22) made of SiC of a first conductivity type having a higher impurity concentration than the first impurity region, the second impurity region (22) being formed in contact with the trench gate structure in a surface portion of the base layer, a first electrode (28) provided separately in each of the main cell region and the sense cell region, the first electrode (28) being electrically connected to the second impurity region and the base layer in the main cell region and electrically connected to the second impurity region and the base layer in the sense cell region, and a second electrode (31) being arranged on the back side of the substrate and electrically connected to the substrate, The deep layer is formed in the surface layer of the first impurity region, and a base layer is formed on the deep layer. An isolation structure (40, 41) electrically isolates the base layer located on the main cell region side from the base layer located on the sense cell region side. The deep layer in the element isolation region is arranged such that the portion located on the main cell region side and the portion located on the sense cell region side are spaced apart by a predetermined distance (B3), the predetermined distance being wider than the distance (B1, B2) between the deep layers in the cell region. The JFET layer is formed in a region of the cell region different from the element isolation region.

According to this, a JFET layer having a higher concentration than the first impurity region is not formed in the element isolation region. Therefore, compared to when a JFET layer is formed in the element isolation region, it is easier to suppress the rise of the equipotential lines due to the influence of voltage. Therefore, the distance between the deep layers in the element isolation region can be made equal to or greater than the distance between the deep layers in the cell region. As a result, when forming the deep layers by ion implantation, a mask corresponding to the distance between the deep layers in the element isolation region can be easily arranged, resulting in a SiC semiconductor device in which the deterioration of yield is suppressed.

The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

FIG. 1 is a plan view of a SiC semiconductor device according to a first embodiment. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 11 is a diagram showing the relationship between the width of an element isolation region and the drain-source breakdown voltage. FIG. 11 is a cross-sectional view of an element isolation region in a second embodiment. FIG. 11 is a cross-sectional view of a cell region and an outer periphery region in a third embodiment. FIG. 13 is a perspective view of a cell region and an outer periphery region in a fourth embodiment. FIG. 13 is a cross-sectional view of an element isolation region in a fourth embodiment. FIG. 13 is a cross-sectional view of an element isolation region in a modified example of the fourth embodiment. FIG. 11 is a cross-sectional view of a cell region and an outer periphery region in another embodiment.

The following describes embodiments of the present invention with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals.

First Embodiment
The first embodiment will be described with reference to the drawings. As shown in Fig. 1, the SiC semiconductor device of this embodiment has a cell region 1 and an outer peripheral region 2 surrounding the cell region 1. The cell region 1 has a main cell region Rm in which main cells are provided, a sense cell region Rs in which sense cells are provided, and an element isolation region In disposed between the main cell region Rm and the sense cell region Rs and electrically isolating the main cell region Rm and the sense cell region Rs. In the SiC semiconductor device of this embodiment, the main current flowing in the main cell region Rm is detected based on the sense current flowing in the sense cell region Rs and the area ratio.

In this embodiment, the main cell region Rm and the sense cell region Rs are arranged so that the sense cell region Rs is located within the main cell region Rm. The element isolation region In is arranged in a frame shape so as to surround the sense cell region Rs. Note that in this embodiment, MOSFETs with a trench gate structure having a similar structure are formed in the main cell region Rm and the sense cell region Rs.

As shown in FIG. 2, the peripheral region 2 is configured to have a guard ring portion 2a and a connecting portion 2b that is arranged inside the guard ring portion 2a. In other words, the peripheral region 2 is configured to have a guard ring portion 2a and a connecting portion 2b that is arranged between the cell region 1 and the guard ring portion 2a.

The following describes a SiC semiconductor device having an n-channel MOSFET in the cell region 1 with reference to FIG. 2 and FIG. 3. As described above, MOSFETs of the same structure are formed in the main cell region Rm and the sense cell region Rs. In the following description, one direction in the surface direction of the substrate 11 described later is defined as the X-axis direction, a direction intersecting with the one direction in the surface direction of the substrate is defined as the Y-axis direction, and a direction intersecting with the X-axis direction and the Y-axis direction is defined as the Z-axis direction. In this embodiment, the X-axis direction and the Y-axis direction are perpendicular to each other. In this embodiment, the Z-axis direction corresponds to the thickness direction of the semiconductor substrate 10 described later, and also corresponds to the stacking direction of the substrate 11 and the low concentration layer 13 described later. The Y-axis direction is, for example, the <11-20> direction.

The SiC semiconductor device is configured using a semiconductor substrate 10. Specifically, the SiC semiconductor device includes an n ⁺ type substrate 11 made of SiC. In this embodiment, the substrate 11 has an off angle of 0 to 8° with respect to the (0001) Si surface, an n-type impurity concentration of nitrogen, phosphorus, etc. of 1.0×10 ¹⁹ /cm ³ , and a thickness of about 300 μm. In this embodiment, the substrate 11 constitutes a drain region.

An n-type buffer layer 12 made of SiC is formed on the surface of the substrate 11. The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11. The buffer layer 12 has an n-type impurity concentration between that of the substrate 11 and that of a low concentration layer 13 described below, and has a thickness of about 1 μm.

On the surface of the buffer layer 12, for example, an n ^{-type low concentration layer 13 made of SiC is formed, the n-} type impurity concentration of which is 5.0 to 20.0×10 ¹⁵ /cm ³ and the thickness of which is about 7 to 15 μm. The low concentration layer 13 may have a constant impurity concentration in the Z-axis direction, but it is preferable that the concentration distribution is inclined so that the low concentration layer 13 has a higher concentration on the substrate 11 side than on the side away from the substrate 11. For example, it is preferable that the low concentration layer 13 has an impurity concentration of about 2.0×10 ¹⁵ /cm ³ in a portion about 3 to 5 μm from the surface of the substrate 11 than in other portions. With this configuration, the internal resistance of the low concentration layer 13 can be reduced, and the on-resistance can be reduced. In this embodiment, the low concentration layer 13 corresponds to the first impurity region.

In the surface layer of the low concentration layer 13, a JFET layer 14 and a first deep layer 15 are formed at the connection portion 2b between the cell region 1 and the peripheral region 2. In this embodiment, the JFET layer 14 and the first deep layer 15 each extend along the X-axis direction and have linear portions arranged alternately and repeatedly in the Y-axis direction. In other words, the JFET layer 14 and the first deep layer 15 are stripes extending along the X-axis direction in the normal direction (hereinafter simply referred to as the normal direction) to the surface of the substrate 11, and are arranged alternately along the Y-axis direction. In addition, in the normal direction to the surface of the substrate 11, it can also be said that when viewed from the normal direction to the surface of the substrate 11. In addition, the normal direction to the surface of the substrate 11 is also the direction along the stacking direction of the drift layer 19 and the base layer 21 described later, and is the direction along the Z-axis direction.

The JFET layer 14 is of n-type with a higher impurity concentration than the low concentration layer 13, and has a thickness of 0.3 to 1.5 μm. In this embodiment, the JFET layer 14 has an n-type impurity concentration of about 5.0×10 ¹⁶ to 1.0×10 ¹⁷ /cm ^3. The first deep layer 15 has a p-type impurity concentration of about 2.0×10 ¹⁷ to 2.0×10 ¹⁸ /cm ^3. As will be described later in detail, in this embodiment, the JFET layer 14 is not formed in the element isolation region In of the cell region 1. That is, the JFET layer 14 is formed only in the main cell region Rm and the sense cell region Rs in the cell region 1. In this embodiment, the region in the cell region 1 where the JFET layer 14 is not formed is the element isolation region In.

In addition, the first deep layer 15 in this embodiment is formed shallower than the JFET layer 14. In other words, the first deep layer 15 is formed so that its bottom is located within the JFET layer 14. In other words, the first deep layer 15 is formed so that the JFET layer 14 is located between it and the low concentration layer 13. Note that such a JFET layer 14 and first deep layer 15 are formed by appropriately ion-implanting impurities into the surface layer of the low concentration layer 13.

Here, as described above, the main cell region Rm and the sense cell region Rs have the same configuration, and the perspective views of both are as shown in FIG. 3. However, in this embodiment, the interval B2 between adjacent first deep layers 15 in the sense cell region Rs is narrower than the interval B1 between adjacent first deep layers 15 in the main cell region Rm. For this reason, the diagram of the main cell region Rm and the sense cell region Rs corresponding to FIG. 2 is actually a diagram in which the interval B2 between adjacent first deep layers 15 in the sense cell region Rs is narrower than the interval B1 between adjacent first deep layers 15 in the main cell region Rm. The interval between adjacent first deep layers 15 can also be said to be the interval between the first deep layers 15 arranged along the Y-axis direction. In the following, the interval B1 between adjacent first deep layers 15 in the main cell region Rm is also simply referred to as the interval B1, and the interval B2 between adjacent first deep layers 15 in the sense cell region Rs is also simply referred to as the interval B2.

In addition, a plurality of p-type guard rings 16 are provided in the surface layer of the low concentration layer 13 in the guard ring portion 2a of the peripheral region 2 so as to surround the cell region 1. In this embodiment, the top surface layout of the guard rings 16 is a square or a circle with rounded corners in the normal direction.

A current spreading layer 17, a second deep layer 18, a base layer 21, a source region 22, a contact region 23, etc. are formed on the JFET layer 14 and the first deep layer 15 in the cell region 1.

The current spreading layer 17 is of n-type with a higher impurity concentration than the low concentration layer 13, and is formed so as to be connected to the JFET layer 14. Therefore, in this embodiment, the low concentration layer 13, the JFET layer 14, and the current spreading layer 17 are connected to each other, and form the drift layer 19. The current spreading layer 17 has a thickness of 0.5 to 2.0 μm and an n-type impurity concentration of about 1.0×10 ¹⁷ to 3.0×10 ¹⁷ cm ³ .

The second deep layer 18 is of p-type and has a thickness equal to that of the current spreading layer 17. The second deep layer 18 is formed so as to be connected to the first deep layer 15. The second deep layer 18 of the present embodiment has a p-type impurity concentration of about 2.0×10 ¹⁷ to 2.0×10 ¹⁸ /cm ³ .

The current spreading layer 17 and the second deep layer 18 extend in a direction intersecting the longitudinal direction of the striped portion of the JFET layer 14 and the first deep layer 15. In this embodiment, the current spreading layer 17 and the second deep layer 18 extend in the Y-axis direction as the longitudinal direction, and are arranged in a layout in which multiple layers are arranged alternately in the X-axis direction. The formation pitch of the current spreading layer 17 and the second deep layer 18 is set to match the formation pitch of the trench gate structure described later, and the second deep layer 18 is formed to sandwich the trench 24 described later.

The base layer 21 is of p-type, and is formed on the current spreading layer 17 and the second deep layer 18. Therefore, the first deep layer 15 is connected to the base layer 21 via the second deep layer 18. The base layer 21 has, for example, a p-type impurity concentration of 5.0×10 ¹⁶ to 2.0×10 ¹⁹ /cm ³ and a thickness of about 2.0 μm.

The source region 22 is n ⁺ type and is formed in the surface layer of the base layer 21. The contact region 23 is p ⁺ type and is formed in the surface layer of the base layer 21. Specifically, the source region 22 is formed so as to contact the side of a trench 24 described later, and the contact region 23 is formed on the opposite side of the trench 24 described later across the source region 22. In this embodiment, the source region 22 has an n-type impurity concentration (i.e., surface concentration) in the surface layer of, for example, 1.0×10 ¹⁸ /cm 3 and a thickness of about 0.3 μm. The contact region 23 has a p-type impurity concentration (i.e., surface concentration) in the surface layer of, for example, 1.0×10 ²¹ /cm ³ and a thickness of about 0.3 μm. In this embodiment, the source region 22 corresponds to the second impurity region.

A current spreading layer 17, a second deep layer 18, a base layer 21, a contact region 23, etc. are formed on the low concentration layer 13, the JFET layer 14, the first deep layer 15, and the guard ring 16 in the peripheral region 2. The second deep layer 18 is formed in the connecting portion 2b of the peripheral region 2, and is formed so as to be connected to the first deep layer 15 that extends from the cell region 1 to the peripheral region 2.

The base layer 21 is formed on the second deep layer 18 and extends from the cell region 1. The contact region 23 is formed in the surface layer of the base layer 21 and has a similar configuration to the contact region 23 formed in the cell region 1. In this embodiment, the entire surface of the connecting portion 2b in the outer periphery region 2 is made into the contact region 23.

As described above, in this embodiment, the semiconductor substrate 10 is configured to include the substrate 11, buffer layer 12, low concentration layer 13, JFET layer 14, first deep layer 15, current spreading layer 17, second deep layer 18, base layer 21, source region 22, contact region 23, etc. Since the semiconductor substrate 10 is configured as described above, it can be said that the semiconductor substrate 10 is configured of SiC. In addition, in this embodiment, one surface 10a of the semiconductor substrate 10 is configured of the source region 22 and the contact region 23, and the other surface 10b of the semiconductor substrate 10 is configured of the substrate 11.

In this embodiment, the current spreading layer 17, the second deep layer 18, the base layer 21, the source region 22, and the contact region 23 are formed by ion implantation. Therefore, it can be said that the current spreading layer 17, the second deep layer 18, the base layer 21, the source region 22, and the contact region 23 are formed by ion implantation layers.

In addition, in the semiconductor substrate 10, a trench 24 having a width of, for example, 0.4 to 0.8 μm is formed in the cell region 1, penetrating the source region 22, base layer 21, etc. from the one surface 10a side to reach the current spreading layer 17, and the bottom surface is located within the current spreading layer 17. The trench 24 is formed so as not to reach the JFET layer 14 and the first deep layer 15. In other words, the trench 24 is formed so that the JFET layer 14 and the first deep layer 15 are located below the bottom surface and apart from the trench 24.

The trenches 24 are formed so that multiple trenches 24 extend along the Y-axis direction and are arranged at equal intervals in the X-axis direction to form stripes. In other words, in this embodiment, the trenches 24 are formed so that their longitudinal direction is perpendicular to the longitudinal direction of the first deep layer 15. The trenches 24 are formed so that they are sandwiched between the second deep layers 18 in the Z-axis direction.

A gate insulating film 25 is formed on the inner wall surface of the trench 24, and a gate electrode 26 made of doped Poly-Si or the like is formed on the gate insulating film 25. This forms a trench gate structure. Although not particularly limited, the gate insulating film 25 is formed by thermally oxidizing the inner wall surface of the trench 24 or by carrying out a CVD (short for chemical vapor deposition) method. The gate insulating film 25 has a thickness of about 100 nm on both the side and bottom sides of the trench 24.

The gate insulating film 25 is also formed on surfaces other than the inner wall surface of the trench 24. Specifically, the gate insulating film 25 is formed so as to cover a portion of one surface 10a of the semiconductor substrate 10. More specifically, the gate insulating film 25 is formed so as to cover a portion of the surface of the source region 22 in the cell region 1. In other words, the gate insulating film 25 has contact holes 25a that expose the source region 22 and the contact region 23 in a portion of the cell region 1 different from the portion where the gate electrode 26 is disposed.

The gate insulating film 25 is also formed on the surface of the contact region 23 in the connecting portion 2b. In addition, the gate insulating film 25 has a contact hole 25c formed in the connecting portion 2b of the outer peripheral region 2 to expose the contact region 23. The gate electrode 26 is extended onto the surface of the gate insulating film 25 in the connecting portion 2b. In this embodiment, the contact hole 25c is formed on the guard ring portion 2a side of the gate electrode 26 extended onto the gate insulating film 25 in the connecting portion 2b. In this manner, the trench gate structure of this embodiment is configured.

In addition, in the semiconductor substrate 10, a recess 10c is formed in the guard ring portion 2a of the peripheral region 2 so as to penetrate the base layer 21 and reach the second deep layer 18 and the current spreading layer 17. The SiC semiconductor device of this embodiment has a mesa structure in which the recess 10c is thus formed in the peripheral region 2.

An interlayer insulating film 27 is formed on one surface 10a of the semiconductor substrate 10 so as to cover the gate electrode 26, the gate insulating film 25, etc. The interlayer insulating film 27 is made of BPSG (short for borophosphosilicate glass) or the like.

In the interlayer insulating film 27, a contact hole 27a is formed in the cell region 1, which communicates with the contact hole 25a and exposes the source region 22 and the contact region 23. In addition, a contact hole 27b is formed in the interlayer insulating film 27, which exposes a portion of the gate electrode 26 that extends to the connecting portion 2b. In addition, a contact hole 27c is formed in the interlayer insulating film 27 in the connecting portion 2b of the peripheral region 2, which communicates with the contact hole 25c and exposes the contact region 23. In other words, in the interlayer insulating film 27, the contact hole 27a is formed in the cell region 1, and the contact holes 27b and 27c are formed in the peripheral region 2.

The contact hole 27a formed in the interlayer insulating film 27 of the cell region 1 is formed so as to communicate with the contact hole 25a formed in the gate insulating film 25, and functions together with the contact hole 25a as one contact hole. For this reason, hereinafter, the contact holes 25a and 27a are also collectively referred to as contact holes 25b. The contact hole 27c formed in the interlayer insulating film 27 of the connecting portion 2b is formed so as to communicate with the contact hole 25c formed in the gate insulating film 25, and functions together with the contact hole 25c as one contact hole. For this reason, hereinafter, the contact holes 25c and 27c are also collectively referred to as the connecting portion contact hole 25d. The patterns of the contact holes 25b and the connecting portion contact holes 25d are arbitrary, and examples thereof include a pattern in which a plurality of squares are arranged, a pattern in which rectangular line-shaped objects are arranged, or a pattern in which line-shaped objects are arranged. In this embodiment, the contact hole 25b and the connecting portion contact hole 25d are linear along the longitudinal direction of the trench 24.

An upper electrode 28 is formed on the interlayer insulating film 27, and is electrically connected to the source region 22 and the contact region 23 through the contact hole 25b. The upper electrode 28 in this embodiment is also connected to the contact region 23 formed in the base layer 21 of the peripheral region 2 through the connecting portion contact hole 25d. The upper electrodes 28 are provided separately for the main cell region Rm and the sense cell region Rs in the cell region 1. Each upper electrode 28 can be electrically connected to the outside separately. In this embodiment, the upper electrode 28 corresponds to the first electrode. A gate wiring 29 is formed on the interlayer insulating film 27, and is electrically connected to the gate electrode 26 through the contact hole 27b.

The upper electrode 28 in this embodiment is composed of multiple metals, such as Ni/Al. The portion of the multiple metals that contacts the portion that constitutes the n-type SiC (i.e., the source region 22) is composed of a metal that can make ohmic contact with the n-type SiC. At least the portion of the multiple metals that contacts the p-type SiC (i.e., the contact region 23) is composed of a metal that can make ohmic contact with the p-type SiC. The gate wiring 29 may be composed in the same manner as the upper electrode 28, or may be composed of Al-Si, etc.

Furthermore, a protective film 30 made of polyimide or the like is formed to cover the connecting portion 2b and the guard ring portion 2a. In this embodiment, the protective film 30 is formed from the outer peripheral region 2 to the outer edge of the cell region 1 in order to suppress the occurrence of creeping discharge between the upper electrode 28 and the lower electrode 31 described below. Specifically, the protective film 30 is formed in the cell region 1 so as to cover the portion of the upper electrode 28 on the outer peripheral region 2 side while exposing the portion of the upper electrode 28 on the inner edge side.

A lower electrode 31 that is electrically connected to the substrate 11 is formed on the other surface 10b of the semiconductor substrate 10. In this embodiment, the lower electrode 31 corresponds to the second electrode.

In the SiC semiconductor device of this embodiment, an n-channel type inversion type trench gate structure MOSFET is formed in the main cell region Rm and the sense cell region Rs due to this structure. Next, the configuration of the element isolation region In will be described.

The element isolation region In is formed to surround the sense cell region Rs as described above, and is disposed between the main cell region Rm and the sense cell region Rs. As shown in FIG. 4, the element isolation region In has a structure including a substrate 11, a buffer layer 12, and a low concentration layer 13, similar to the cell region 1.

Only the first deep layer 15 is formed in the surface portion of the low concentration layer 13, and the JFET layer 14 is not formed. In this embodiment, the region between the main cell region Rm and the sense cell region Rs where the JFET layer 14 is not formed is the element isolation region In. In other words, the JFET layer 14 is formed in a region different from the element isolation region In.

The first deep layer 15 is arranged such that the portion on the main cell region Rm side is separated from the portion on the sense cell region Rs side by a distance B3. However, the distance B3 (hereinafter simply referred to as distance B3) of the first deep layer 15 in the element isolation region In is set to be equal to or greater than the distances B1 and B2 in the main cell region Rm and the sense cell region Rs. In this embodiment, for example, the distance B1 is set to 0.9 μm, and the distance B3 is set to 1.0 to 1.4 μm.

A current spreading layer 17, a second deep layer 18, a base layer 21, and a contact region 23 are formed on the first deep layer 15. The second deep layer 18 is arranged such that the portion on the main cell region Rm side is separated from the portion on the sense cell region Rs side by a distance B4. However, the distance B4 of the second deep layer 18 is wider than the distance B3 of the first deep layer 15. The current spreading layer 17 is arranged between the second deep layers 18.

The base layer 21 is disposed on the second deep layer 18, and the contact region 23 is formed in the surface layer of the base layer 21. Note that each component in the element isolation region In has the same impurity concentration as that of the cell region 1.

In addition, in the element isolation region In, an isolation trench 40 is formed as an isolation structure so as to reach the current spreading layer 17 and the second deep layer 18. This electrically isolates the base layer 21 and contact region 23 on the main cell region Rm side from the base layer 21 and contact region 23 on the sense cell region Rs side. In this embodiment, the isolation trench 40 has the same depth as the trench 24, and is formed at the same time as the trench 24 is formed.

In this embodiment, the width Ind of the element isolation region In is set to 7.0 μm or more, as described later. The width Ind of the element isolation region In is the length of the portion located between the main cell region Rm and the sense cell region Rs. In addition, the width 40a of the isolation trench 40 is set to 7.4 μm or more, as described later.

The above is the configuration of the SiC semiconductor device in this embodiment. In this embodiment, n ^- type, n-type, and n ⁺ type correspond to the first conductivity type, and p-type and p ⁺ type correspond to the second conductivity type. Next, the operation of the above-mentioned SiC semiconductor device will be described.

First, in the above-mentioned SiC semiconductor device, in the off state before the gate voltage is applied to the gate electrode 26, no inversion layer is formed in the base layer 21. Therefore, even if a positive voltage, for example, 1600 V, is applied to the lower electrode 31, electrons do not flow from the source region 22 into the base layer 21, and no current flows between the upper electrode 28 and the lower electrode 31.

Furthermore, before the gate voltage is applied to the gate electrode 26, an electric field is applied between the drain and gate, and electric field concentration may occur at the bottom of the gate insulating film 25. However, in the above-mentioned SiC semiconductor device, the first deep layer 15 and the JFET layer 14 are provided at a position deeper than the trench 24. Therefore, the depletion layer formed between the first deep layer 15 and the JFET layer 14 suppresses the rise of the equipotential lines due to the influence of the drain voltage, making it difficult for a high electric field to penetrate the gate insulating film 25. Therefore, in this embodiment, it is possible to suppress the destruction of the gate insulating film 25.

When a predetermined gate voltage, for example, 20 V, is applied to the gate electrode 26, a channel is formed on the surface of the base layer 21 that is in contact with the trench 24. Therefore, electrons injected from the upper electrode 28 pass through the channel formed in the base layer 21 from the source region 22 and then flow to the current spreading layer 17. The electrons that flow into the current spreading layer 17 pass through the JFET layer 14 and flow into the low concentration layer 13, and then pass through the substrate 11 as the drain layer and flow to the lower electrode 31. As a result, a current flows between the upper electrode 28 and the lower electrode 31, and the SiC semiconductor device is turned on. In this embodiment, since the electrons that have passed through the channel pass through the current spreading layer 17, the JFET layer 14, and the low concentration layer 13 and flow to the substrate 11, it can be said that a drift layer 19 having the current spreading layer 17, the JFET layer 14, and the low concentration layer 13 is configured.

In this embodiment, the element isolation region In does not include a JFET layer 14 having a higher concentration than the low concentration layer 13. This further suppresses the rise of the equipotential lines due to the influence of the drain voltage. Therefore, in this embodiment, as described above, the interval B3 can be made equal to or greater than the intervals B1 and B2. This makes it possible to easily position a mask equivalent to the interval B3 when forming the first deep layer 15 by ion implantation, resulting in a SiC semiconductor device in which the deterioration of the yield is suppressed.

Here, the inventors investigated the drain-source breakdown voltage and obtained the results shown in FIG. 5. That is, as shown in FIG. 5, it was confirmed that the drain-source breakdown voltage gradually increases until the width Ind of the element isolation region In becomes 7.0 μm, and remains almost unchanged once it becomes 7.0 μm or more. For this reason, it is preferable that the width Ind of the element isolation region In is 7.0 μm or more.

In this case, in the SiC semiconductor device configured as described above, the breakdown voltage of the cell region 1 is about 1500 V. Therefore, by making the width of the element isolation region In 7.0 μm or more, the breakdown voltage of the element isolation region In can be made higher than the breakdown voltage of the cell region 1. This makes it possible to prevent the element isolation region In, which is likely to have a small area, from breaking down first. However, the element isolation region In becomes an ineffective region through which current does not easily flow. Therefore, it is preferable to make the width Ind of the element isolation region In as narrow as possible within the range of 7.0 μm or more.

In addition, according to the study by the present inventors, it has been confirmed that, taking into consideration the processing accuracy of the mask when forming the first deep layer 15, the width 40a of the isolation trench 40 is preferably derived by the following formula. That is, according to the study by the present inventors, when the SiC semiconductor device is configured with the above-mentioned impurity concentration, it has been confirmed that the maximum of the interval B3 is preferably 1.4 μm. In addition, it has been confirmed that, taking into consideration the misalignment, the difference between the interval B3 and the interval B4 is preferably at least 2.0 μm. Furthermore, it has been confirmed that, taking into consideration the misalignment between the interval B2 and the isolation trench 40, it is preferable to provide a margin of at least 1.0 μm. Therefore, the minimum value of the width 40a of the isolation trench 40 is shown by the following formula 1.

(1.4+2×2.0)+2×1.0=7.4 (μm)...(Formula 1)
For the above reasons, in this embodiment, the width 40a of the isolation trench 40 is set to 7.4 μm or more.

According to the present embodiment described above, the JFET layer 14, which has a higher concentration than the low concentration layer 13, is not formed in the element isolation region In. Therefore, compared to when the JFET layer 14 is formed in the element isolation region In, it is easier to suppress the rise of the equipotential lines due to the influence of the drain voltage. Therefore, in the SiC semiconductor device of this embodiment, the interval B3 can be made equal to or greater than the intervals B1 and B2. As a result, when the first deep layer 15 is formed by ion implantation, a mask equivalent to the interval B3 can be easily arranged, and a SiC semiconductor device in which the deterioration of the yield is suppressed can be obtained.

(1) In this embodiment, the spacing B2 of the sense cell region Rs is narrower than the spacing B1 of the main cell region Rm. This allows the normalized on-resistance of the sense cell region Rs during operation to be equalized, making it easier to improve the linearity of the current value of the main cell region Rm and the current value of the sense cell region Rs.

(2) In this embodiment, the isolation structure is formed by the isolation trench 40. Therefore, the process of forming the trench 24 and the process of forming the isolation trench 40 can be common, and the manufacturing process can be simplified. Also, in the element isolation region In, the isolation trench 40 is formed so as to penetrate the base layer 21 and contact region 23 on the main cell region Rm side and the base layer 21 and contact region 23 on the sense cell region Rs side, so that the base layer 21 and contact region 23 do not need to be patterned in detail. Therefore, in this respect as well, the manufacturing process can be simplified.

(3) In this embodiment, the width 40a of the isolation trench 40 is set to 7.4 μm or more. This allows for adequate response to misalignment and prevents yield degradation.

(4) In this embodiment, the width of the element isolation region In is set to 7.0 μm or more. This allows the withstand voltage between the drain and source in the element isolation region In to be sufficiently high.

Second Embodiment
A second embodiment will be described. In this embodiment, the configuration of the separation structure is changed from that of the first embodiment. As the rest is the same as the first embodiment, the description will be omitted here.

In the SiC semiconductor device of this embodiment, as shown in FIG. 6, an n-type isolation layer 41 is formed in the element isolation region In between the base layer 21 and contact region 23 of the main cell region Rm and the base layer 21 and contact region 23 of the sense cell region Rs. The base layer 21 and contact region 23 of the main cell region Rm and the base layer 21 and contact region 23 of the sense cell region Rs are electrically isolated by the isolation layer 41.

According to the present embodiment described above, the JFET layer 14, which has a higher concentration than the low concentration layer 13, is not formed in the element isolation region In. Therefore, the same effect as in the first embodiment can be obtained.

(1) In this embodiment, the base layer 21 and contact region 23 of the main cell region Rm are electrically isolated from the base layer 21 and contact region 23 of the sense cell region Rs by the isolation layer 41. Therefore, compared to when the isolation structure is configured with an isolation trench 40, surface irregularities are less likely to occur, improving the reliability of the SiC semiconductor device and enabling the SiC semiconductor device to be miniaturized.

Third Embodiment
A third embodiment will be described. In this embodiment, the configuration of the outer circumferential region 2 is changed from that of the first embodiment. As the rest is the same as the first embodiment, a description thereof will be omitted here.

7, in the SiC semiconductor device of this embodiment, an n ⁺ type source region 22 is formed on the side of the connecting portion 2b of the peripheral region 2 opposite to the cell region 1. In other words, the peripheral region 2 has a configuration having a portion in which the contact region 23 and the source region 22 are arranged in this order from the cell region 1 side. In further other words, the surface layer portion of the connecting portion 2b of the peripheral region 2 is not formed only by the contact region 23.

The source region 22 formed in the connecting portion 2b is formed so that the upper electrode 28 formed in the connecting portion 2b is connected to at least the contact region 23 so that the breakdown voltage of the guard ring portion 2a can be maintained. In other words, the connecting portion contact hole 25d formed in the connecting portion 2b is formed so as to expose at least the contact region 23 formed in the connecting portion 2b. In this embodiment, the connecting portion contact hole 25d is formed so as to expose only the contact region 23 formed in the connecting portion 2b.

In the SiC semiconductor device of the first embodiment, the source region 22 and the contact region 23 are formed from ion-implanted layers, and the contact region 23 has a higher impurity concentration than the source region 22.

When manufacturing such a SiC semiconductor device, n-type impurities are ion-implanted from the one surface 10a side of the semiconductor substrate 10, and then p-type impurities are ion-implanted to form the source region 22 and the contact region 23. That is, the contact region 23 is formed by forming a region with a high impurity concentration in the source region 22 with a low impurity concentration. In this case, according to the study by the inventors, it was confirmed that the warping of the semiconductor substrate 10 would be large if the contact region 23 was formed on the entire surface of the joint portion 2b. Therefore, in this embodiment, the source region 22 is formed in the joint portion 2b of the peripheral region 2. In other words, the source region 22 that is not pushed back into the contact region 23 remains in the joint portion 2b of the peripheral region 2.

According to the present embodiment described above, the JFET layer 14, which has a higher concentration than the low concentration layer 13, is not formed in the element isolation region In. Therefore, the same effect as in the first embodiment can be obtained.

(1) In this embodiment, in the connecting portion 2b of the peripheral region 2, the contact region 23 is formed on the cell region 1 side, and the source region 22 is formed on the opposite side to the cell region 1 side. This makes it possible to suppress warping of the SiC semiconductor device (i.e., the semiconductor substrate 10).

Fourth Embodiment
A fourth embodiment will be described. In this embodiment, the configuration of the cell region 1 is changed from that of the first embodiment. As the rest is the same as in the first embodiment, the description will be omitted here.

In the SiC semiconductor device of this embodiment, as shown in FIG. 8, in the cell region 1, the base layer 21 is formed on the JFET layer 14 and the first deep layer 15, and the current spreading layer 17 and the second deep layer 18 are not formed. Therefore, the drift layer 19 is composed of the low concentration layer 13 and the JFET layer 14. The trench 24 is formed so that its bottom surface reaches the JFET layer 14 and the first deep layer 15. Note that in FIG. 8, the interlayer insulating film 27 and the upper electrode 28 located on the one surface 10a side of the semiconductor substrate 10 are omitted.

In addition, a p-type third deep layer 50 is formed below each trench 24 so as to contact the bottom surface of the trench 24. Specifically, the third deep layer 50 is formed along the longitudinal direction of the trench 24. In other words, the third deep layer 50 extends along the Y-axis direction intersecting with the first deep layer 15. The third deep layer 50 may be formed by dividing it into multiple parts along the Y-axis direction. However, the third deep layer 50 is formed so as to be electrically connected to the base layer 21 via the first deep layer 15.

In addition, the third deep layer 50 in this embodiment is formed so that its bottom surface reaches the low concentration layer 13 by penetrating the JFET layer 14 and the first deep layer 15.

The third deep layer 50 is formed by ion implantation after the trench 24 is formed. In this embodiment, the third deep layer 50 has a lower impurity concentration than the first deep layer 15.

In the peripheral region 2, in the connecting portion 2b, a base layer 21 is formed on the JFET layer 14 and the first deep layer 15, and a contact region 23 is formed on the surface layer of the base layer 21. The base layer 21 and the contact region 23 are formed by extending from the cell region 1.

In addition, in this embodiment, no recess 10c is formed in the guard ring portion 2a of the peripheral region 2. In the guard ring portion 2a of the peripheral region 2, one surface 10a of the semiconductor substrate 10 is composed of a low concentration layer 13.

Similarly, in the element isolation region In, as shown in FIG. 9, a base layer 21 is formed on the first deep layer 15, and a contact region 23 is formed in the surface layer of the base layer 21. As in the first embodiment, the interval B3 is greater than or equal to the intervals B1 and B2. As in the first embodiment, the JFET layer 14 is not formed in the element isolation region In.

The isolation structure of this embodiment is composed of an isolation layer 41, as in the second embodiment. The isolation structure may also be composed of an isolation trench 40, as in the first embodiment.

In such a SiC semiconductor device, when the device is in the off state, the third deep layer 50 is formed along the bottom surface of the trench 24, which makes it easier to effectively deplete the periphery of the bottom surface of the trench 24. This further reduces the electric field concentration near the bottom surface of the trench 24.

In addition, in this embodiment, the third deep layer 50 is formed so as to contact the bottom surface of the trench 24. In other words, it is formed so as to contact the gate insulating film 25 arranged on the bottom surface of the trench 24. Therefore, since the third deep layer 50 is preferentially depleted when the device is off, no electric field penetrates into the gate insulating film 25 located at the bottom of the trench 24, and oxide film breakdown is suppressed. In addition, the electrostatic capacitance (i.e., feedback capacitance) between the gate electrode 26 and the lower electrode 31 can be reduced, and the switching speed can be improved.

Furthermore, in this embodiment, the third deep layer 50 is formed so that it penetrates the JFET layer 14 and the first deep layer 15 and its bottom surface reaches the low concentration layer 13. This suppresses the electric field from creeping up to the JFET layer 14 arranged between the third deep layers 50, improving the breakdown voltage. Furthermore, by forming such a third deep layer 50, breakdown is more likely to occur in the third deep layer 50 that protrudes downward when an overvoltage is applied. Therefore, breakdown is more likely to occur in the cell region 1, improving the avalanche resistance.

As described above, even if the current spreading layer 17 and the second deep layer 18 are not provided in the present embodiment, the same effect as in the first embodiment can be obtained because the JFET layer 14, which has a higher concentration than the low concentration layer 13, is not formed in the element isolation region In.

(1) In this embodiment, the third deep layer 50 is formed along the bottom surface of the trench 24, so that the electric field does not penetrate into the gate insulating film 25 located at the bottom of the trench 24, and oxide film breakdown is suppressed.

(2) In this embodiment, the third deep layer 50 is formed so as to contact the bottom surface of the trench 24, so that the electrostatic capacitance (i.e., feedback capacitance) between the gate electrode 26 and the lower electrode 31 can be reduced, and the switching speed can be improved.

(3) In this embodiment, the third deep layer 50 is formed so that it penetrates the JFET layer 14 and the first deep layer 15 and its bottom surface reaches the low concentration layer 13. This suppresses the electric field from creeping up to the JFET layer 14 arranged between the third deep layers 50, improving the breakdown voltage. Furthermore, by forming such a third deep layer 50, breakdown is more likely to occur in the third deep layer 50 that protrudes downward when an overvoltage is applied. Therefore, breakdown is more likely to occur in the cell region 1, improving the avalanche resistance.

(Modification of the fourth embodiment)
A modified example of the fourth embodiment will be described. In the fourth embodiment, as shown in Fig. 10, the source region 22 may be formed in the surface layer of the base layer 21 in the element isolation region In. Although not particularly shown, the source region 22 may also be formed in the surface layer of the base layer 21 in the element isolation region In in the first to third embodiments.

In addition, in the fourth embodiment, the third deep layer 50 may be formed so that its bottom surface is located within the JFET layer 14 and the first deep layer 15. In other words, the third deep layer 50 may be formed so as not to reach the low concentration layer 13. This makes it difficult for the depletion layer to extend from the third deep layer 50, thereby reducing the on-resistance.

Other Embodiments
Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

For example, in each of the above embodiments, an n-channel type trench gate structure MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the SiC semiconductor device may be configured by forming, for example, a p-channel type trench gate structure MOSFET in which the conductivity type of each component is inverted with respect to the n-channel type in the cell region 1. Furthermore, the semiconductor device may be configured to have an IGBT having a similar structure formed therein in addition to the MOSFET. In the case of the IGBT, it is the same as the vertical MOSFET described in each of the above embodiments, except that the n ⁺ type substrate 11 in each of the above embodiments is changed to a p ⁺ type collector layer.

In addition, in each of the above embodiments, the source region 22 may be configured by arranging multiple regions, including a low concentration source region and a high concentration source region having a higher concentration than the low concentration source region, in that order from the substrate 11 side. In this configuration, the high concentration source region corresponds to the high concentration layer, and the low concentration source region corresponds to the low concentration layer.

In each of the above embodiments, the source region 22 may be formed of an epitaxial layer rather than ion implantation. When the source region 22 is formed of an epitaxial layer, no strain stress is generated due to ion implantation, and therefore leakage current between the drain and source due to strain stress can be suppressed. When the source region 22 is formed of multiple regions, the multiple-stage concentration control required when the source region 22 is formed of an epitaxial layer can be eliminated when the source region 22 is formed by ion implantation.

Furthermore, in the first and third embodiments, the depth of the isolation trench 40 may be different from that of the trench 24. Also, the isolation trench 40 may be formed in a process separate from the process of forming the trench 24. Furthermore, the isolation trench 40 may have a width 40a of less than 7.4 μm. Similarly, the element isolation region In may have a width Ind of less than 7.0 μm.

In the first to third embodiments, the recess 10c may not be formed in the outer peripheral region 2, and in the fourth embodiment, the recess 10c may be formed in the outer peripheral region 2.

In the third embodiment, an example was described in which the connecting portion contact hole 25d of the connecting portion 2b is formed to expose only the contact region 23. However, it is sufficient that the connecting portion contact hole 25d is formed to expose at least the contact region 23, and as shown in FIG. 11, it may be formed to expose the contact region 23 and the source region 22.

The above embodiments can also be combined. For example, the second embodiment can be combined with the third embodiment, and the isolation structure can be configured with an isolation layer 41. The third embodiment can be combined with the fourth embodiment, and the source region 22 can remain in the connecting portion 2b. Furthermore, combinations of the above embodiments can also be combined with each other.

When indicating the crystal orientation, a bar (-) should normally be placed above the desired number, but due to limitations on expression based on electronic filing, a bar is placed before the desired number in this specification.

1 Cell region 11 Substrate 13 Low concentration layer (first impurity region)
14 JFET layer 15 Deep layer 21 Base layer 24 Trench 25 Gate insulating film 26 Gate electrode 28 Upper electrode (first electrode)
31 Lower electrode (second electrode)

Claims (10)

A silicon carbide semiconductor device in which a semiconductor element having a trench gate structure is formed in a cell region (1) including a main cell region (Rm) and a sense cell region (Rs), and the main cell region and the sense cell region are electrically isolated by an element isolation region (In),
A substrate (11) of a first conductivity type or a second conductivity type made of silicon carbide;
A first impurity region (13) of a first conductivity type formed on a surface of the substrate and having a lower impurity concentration than the substrate;
The main cell region and the sense cell region are
a JFET layer (14) made of silicon carbide of a first conductivity type formed in a surface layer portion of the first impurity region and having a higher impurity concentration than the first impurity region;
a deep layer (15) made of second conductivity type silicon carbide formed in a surface layer portion of the first impurity region and arranged alternately with the JFET layer in a surface direction of the substrate;
a base layer (21) made of second conductivity type silicon carbide formed on the JFET layer and the deep layer;
a trench gate structure including a gate insulating film (25) formed on an inner wall surface of a trench (24) formed deeper than the base layer and with one direction as a longitudinal direction, and a gate electrode (26) formed on the gate insulating film in the trench;
a second impurity region (22) formed in a surface layer portion of the base layer in contact with the trench gate structure and made of silicon carbide of the first conductivity type having a higher impurity concentration than the first impurity region;
a first electrode (28) provided separately in each of the main cell region and the sense cell region, electrically connected to the second impurity region and the base layer in the main cell region, and electrically connected to the second impurity region and the base layer in the sense cell region;
A second electrode (31) is disposed on the rear side of the substrate and is electrically connected to the substrate,
The element isolation region is
the deep layer formed in a surface layer portion of the first impurity region;
the base layer formed on the deep layer;
an isolation structure (40, 41) that electrically isolates the base layer located on the main cell region side from the base layer located on the sense cell region side;
The deep layer in the element isolation region is arranged such that a portion located on the main cell region side and a portion located on the sense cell region side are spaced apart from each other by a predetermined distance (B3),
The predetermined interval is wider than the interval (B1, B2) of the deep layer in the cell region,
The JFET layer is formed in a region of the cell region different from the element isolation region. The silicon carbide semiconductor device according to claim 1, wherein the spacing (B2) of the deep layers in the sense cell region is narrower than the spacing (B1) of the deep layers in the main cell region. The silicon carbide semiconductor device according to claim 1, wherein the isolation structure is an isolation trench (40) formed between the base layer located on the main cell region side and the base layer located on the sense cell region side. The silicon carbide semiconductor device according to claim 3, wherein the isolation trench has a width (40a) of 7.4 μm or more. The silicon carbide semiconductor device according to claim 1, wherein the isolation structure is a first conductivity type isolation layer (41) disposed between the base layer located on the main cell region side and the base layer located on the sense cell region side. A silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the element isolation region has a width (Ind) of 7.0 μm or more. A peripheral region (2) surrounding the cell region,
the outer periphery region has a portion in which, from the cell region side, a contact region (23) of a second conductivity type having a higher impurity concentration than the second impurity region and the second impurity region are arranged in this order, and an insulating film (25, 27) is arranged on a surface of the outer periphery region;
The silicon carbide semiconductor device according to claim 1 , wherein said insulating film has a contact hole (25 d) formed therein for exposing at least said contact region in said outer periphery region. The silicon carbide semiconductor device according to claim 1, wherein the second impurity region is formed by stacking multiple layers including, from the substrate side, a low concentration layer and a high concentration layer having a higher impurity concentration than the low concentration layer. The silicon carbide semiconductor device according to claim 1, wherein the second impurity region is composed of an ion-implanted layer. The silicon carbide semiconductor device according to claim 1, wherein the second impurity region is formed of an epitaxial layer.

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