JP2024069888A - Semiconductor Device - Google Patents

Abstract

[Problem] To provide a semiconductor element with high breakdown voltage. [Solution] The semiconductor element 1 has first regions 10, 11, 12 made of Si and including a p-type region and an n-type region, second regions 13, 14, 15, 16 made of a gallium oxide-based material and not including a p-type region, formed on one surface of the first regions 10, 11, 12, a first electrode (cathode electrode) 17 provided on the surface of the second regions 13, 14, 15, 16 opposite to the first region side, and a second electrode (anode electrode) 18 provided on the surface of the first region opposite to the second region side. [Selected Figure] Figure 1

Description

This disclosure relates to semiconductor devices.

In recent years, the demand for power saving has increased due to environmental and energy issues, and the development of semiconductor elements (power devices) used for power control has become more active. In particular, gallium oxide (Ga ₂ O ₃ ) has attracted attention as a next-generation power device material with low loss and high voltage resistance.

The static induction transistor (SIT) and static induction thyristor (SIThy) are known as power devices. The SIT has a structure in which n-type source, channel, and drain regions are stacked vertically, and a p-type gate region is embedded in the channel region.

Patent documents 1 and 2 describe static induction transistors (SITs). Patent document 1 describes an SIT in which a p-type gate region is embedded in a high resistivity layer made of n-type Si, and a layer made of a material with a wider band gap than Si is provided between the high resistivity layer and the source electrode.

Furthermore, Patent Document 2 describes an SIT having a first source region made of n ⁺ type GaAs, a second source region made of n-type InGaAs provided on the source region, a channel region made of i-type InGaAs provided on the second source region, a drain region made of n ⁺ type GaAs provided on the channel region, and a gate region formed by diffusing p-type impurities into predetermined regions of the channel region, the first source region, and the second source region.

Publication No. Hei 2-249280 JP 2001-77378 A

To realize a high-voltage SIThy, it is possible to create an SIThy using gallium oxide. However, it is difficult to make gallium oxide p-type, making it difficult to realize an SIThy.

This disclosure was made in consideration of these issues and aims to provide a semiconductor element with high voltage resistance.

One aspect of the present disclosure is
a first region made of Si and including a p-type region and an n-type region;
a second region formed on one surface of the first region, made of a gallium oxide-based material, and not including a p-type region;
a first electrode provided on a surface of the second region opposite to the first region;
a second electrode provided on a surface of the first region opposite to the second region;
The semiconductor element has

In the above semiconductor element, the layer including the p-type region and the n-type region is made of Si, and a layer of gallium oxide-based material that does not include a p-type region is provided on top of that. Therefore, for semiconductor elements that include a p-type region, it is possible to improve the breakdown voltage without requiring a p-type gallium oxide-based material.

As described above, the above aspect makes it possible to provide a semiconductor element with high voltage resistance.

1 is a cross-sectional view parallel to a stacking direction, showing a configuration of a semiconductor element according to a first embodiment. 2 is a cross-sectional view of a portion including a first layer and a first n-type region constituting the semiconductor element of FIG. 1, taken along line II-II of FIG. 1; 3 is a cross-sectional view of a portion including a second layer and a second n-type region constituting the semiconductor element of FIG. 1, taken along line III-III of FIG. 1; 3A to 3C are diagrams illustrating a manufacturing process of the semiconductor element according to the first embodiment. 3A to 3C are diagrams illustrating a manufacturing process of the semiconductor element according to the first embodiment. 4 is a timing chart showing the correspondence between turn-on and turn-off and Vag and Iag. 1A to 1C are diagrams showing a first modified example of the semiconductor element according to the first embodiment. 1A to 1C are diagrams showing a second modified example of the semiconductor element according to the first embodiment. 1 is a band diagram (steady state) taken along a line perpendicular to the substrate and passing through the channel region 21. FIG. FIG. 2 is a band diagram (on state) taken along a line perpendicular to the substrate and passing through the channel region. FIG. 2 is a band diagram taken along a line perpendicular to the substrate and passing through the channel region (off state).

The semiconductor element has a first region made of Si and including a p-type region and an n-type region, a second region made of a gallium oxide-based material formed on one side of the first region and not including a p-type region, a first electrode provided on the surface of the second region opposite the first region side, and a second electrode provided on the surface of the first region opposite the second region side.

The first region is made of p-type Si and has a substrate on one surface of which a second electrode is provided, a first layer made of p-type or i-type Si provided on the other surface of the substrate, and a first n-type region made of n-type Si provided in the first layer so as to sandwich the material of the first layer in the layer extension direction of the first layer. The second region is provided on the surface opposite to the substrate side of the first layer and the first n-type region, and has a second layer made of i-type or n-type gallium oxide-based material, a third layer made of n-type gallium oxide-based material provided on the surface opposite to the first region side of the second layer, and a third electrode connected to the first n-type region and serving as a gate electrode, the first electrode being a cathode electrode, the second electrode being an anode electrode, and the semiconductor element may be a static induction thyristor. A high-voltage static induction thyristor (SIThy) can be realized.

The second layer may also have a second n-type region made of an n-type gallium oxide-based material that is provided in contact with the first n-type region and sandwiches the material of the second layer in the layer extension direction of the second layer. This can improve the switching speed. The width of the second n-type region may be narrower than the width of the first n-type region, and the second n-type region may be formed inside the first n-type region in a plan view that is the stacking direction.

The first layer may be p-type, and the second layer may be i-type.

(Embodiment 1)
1 is a cross-sectional view showing the configuration of a semiconductor device 1 of embodiment 1, taken along a plane parallel to the stacking direction. The semiconductor device 1 of embodiment 1 is a static induction thyristor (SIThy) and has a first region (10, 11, 12), a second region (13, 14, 15, 16), a cathode electrode 17 as a first electrode, an anode electrode 18 as a second electrode, and a gate electrode 19 as a third electrode.

The first region (10, 11, 12) has a substrate 10, a first layer 11, and a first n-type region 12. The second region (13, 14, 15, 16) has a second layer 13, a second n-type region 14, a third layer 15, and a fourth layer 16. Note that in FIG. 1, the conductivity type of each layer is indicated by adding a conductivity type to the reference symbol.

2. Details of each component The substrate 10 is made of high-concentration p-type Si, and its main surface is a (100) surface. The thickness of the substrate 10 is preferably as thin as possible to reduce the thermal resistance and on-resistance of the device, and is, for example, 500 nm to 50 μm. The p-type impurity concentration of the substrate 10 is, for example, 1×10 ¹⁹ to 1×10 ²¹ cm ^-3 .

The first layer 11 is a layer provided on the substrate 10, and is a layer made of low-concentration p-type Si. The p-type impurity concentration of the first layer 11 is, for example, 1×10 ¹⁴ to 1×10 ¹⁶ cm ⁻³ . The thickness of the first layer 11 is, for example, 1 to 10 μm. The first layer 11 may be an i-type layer.

The first n-type region 12 is a region made of high-concentration n-type Si provided in the first layer 11. The first n-type region 12 acts as a gate region. The first n-type region 12 is formed to a predetermined depth from the surface of the first layer 11. The bottom surface of the first n-type region 12 may reach the surface of the substrate 10. In other words, the first layer 11 may or may not be present between the bottom surface of the first n-type region 12 and the substrate 10.

In order to reduce the on-resistance of the semiconductor device 1 of the first embodiment and realize high-speed on/off operation, it is preferable that the first n-type region 12 is thin and has a high n-type impurity concentration. For example, the thickness of the first n-type region 12 is preferably 1 to 2 μm. The n-type impurity concentration of the first n-type region 12 is, for example, 1×10 ¹⁹ to 1×10 ²¹ cm ^-3 .

Figure 2 is a cross-sectional view perpendicular to the stacking direction of the semiconductor element in embodiment 1, and is a cross-section taken along line II-II in Figure 1. As shown in Figure 2, the planar pattern of the first n-type region 12 is formed in a comb shape. The first n-type region 12 has a plurality of strip regions 12A, electrode junctions 12B, and connection portions 12C. The strip regions 12A are formed to a width W1 and are arranged in parallel at a predetermined interval D1. The electrode junctions 12B are arranged in parallel at a distance from the strip region 12A that is arranged at the end of the plurality of strip regions 12A. The electrode junctions 12B are joined to the gate electrode 19. The connection portions 12C connect the strip regions 12A to each other and also connect the strip region 12A to the electrode junctions 12B.

However, it is sufficient that the first n-type region 12 has at least a plurality of strip regions 12A, and that the plurality of strip regions 12A are electrically connected to the gate electrode 19. In short, it is sufficient that the plurality of strip regions 12A are patterned so as to sandwich the material of the first layer 11 in the layer extension direction of the first layer 11. The width W1 is, for example, 1 to 5 μm, and the distance D1 is, for example, 0.5 to 2 μm.

In addition to the comb-like pattern, the first n-type region 12 can also be configured as follows. For example, it may have multiple strip regions 12A and a connection portion 12C that connects the multiple strip regions 12A. In this case, any one of the multiple strip regions 12A or the connection portion 12C is configured to be directly connected to the gate electrode 19. In this case, the electrode junction portion 12B is not necessary.

The first n-type region 12 may also have a plurality of stripe regions 12A arranged independently in a stripe shape without having the electrode junction portion 12B and the connection portion 12C. In this case, each of the plurality of stripe regions 12A is configured to be directly connected to the gate electrode 19.

The second layer 13 is a layer provided on the first layer 11 and the first n-type region 12, and is a layer made of i-type (or non-doped) gallium oxide (Ga ₂ O ₃ ). The crystal structure of gallium oxide is, for example, β-type, and the main surface is a (001) surface or a (100) surface. The second layer 13 may be a low-concentration n-type. However, in order to make it easier to spread the depletion layer in the channel region 21 and to speed up the switching operation, it is preferable that the n-type impurity concentration is as low as possible. For example, it is preferable that it is 1×10 ¹⁵ cm ⁻³ or less, and it is most preferable that it is non-doped or i-type. In addition, when the second layer 13 is made n-type, it may be made the same n-type impurity concentration as the third layer 15.

A buffer layer (not shown) may be provided between the first layer 11 and the first n-type region 12 and the second layer 13. The buffer layer is provided to lattice-match the Si of the first layer 11 and the gallium oxide of the second layer 13 and to improve the crystallinity of the second layer 13.

The second n-type region 14 is a region made of high-concentration n-type gallium oxide provided in the second layer 13. The second n-type region 14 operates as a gate region. The n-type impurity concentration of the second n-type region 14 is, for example, 1×10 ¹⁹ to 1×10 ²¹ cm ⁻³ . The n-type impurity is, for example, Si.

Figure 3 is a cross-sectional view perpendicular to the stacking direction of the semiconductor element in embodiment 1, taken along line III-III in Figure 1. As shown in Figure 3, the second n-type region 14 has a plurality of stripe regions 14A. The plurality of stripe regions 14A correspond to the plurality of stripe regions 12A constituting the first n-type region 12. The planar pattern of the second n-type region 14 is, for example, striped. The plurality of stripe regions 14A of the second n-type region 14 are arranged in the layer extension direction of the second layer 13, sandwiching the material of the second layer 13 therebetween.

The strip regions 14A are formed with a width W2 and are arranged in parallel at a predetermined interval D2. The strip regions 14A are connected to the strip regions 12A of the first n-type region 12. The width W2 of the strip region 14A is narrower than the width W1 of the first n-type region 12, and the second n-type region 14 is formed inside the first n-type region 12 in a plan view. The width W2 is, for example, 1 to 5 μm, and the interval D2 is, for example, 1 to 5 μm. The built-in potential of gallium oxide is approximately four times higher than that of Si, and a wider channel width provides better on-resistance and turn-on characteristics. Therefore, W1>w2 may be used.

The lower surface of the second n-type region 14 is flush with the lower surface of the second layer 13, that is, the second n-type region 14 is located on and in contact with the first n-type region 12. As a result, the second n-type region 14 is connected to the gate electrode 19 via the first n-type region 12. Note that, as long as the second n-type region 14 and the gate electrode 19 are connected, the first n-type region 12 and the second n-type region 14 do not need to be in contact with each other, and the second layer 13 may be present between the first n-type region 12 and the second n-type region 14. The upper surface of the second n-type region 14 is flush with the upper surface of the second layer 13.

The second n-type region 14 is in a stripe shape with multiple band regions 14A arranged independently, but similar to the first n-type region 12, it may be in a comb shape with multiple band regions 14A connected to each other.

The region of the first layer 11 sandwiched between the strip regions 12A of the first n-type region 12 and the region of the second layer 13 sandwiched between the strip regions 14A of the second n-type region 14 are the channel region 21 of the semiconductor element 1 of embodiment 1. Whether the semiconductor element 1 of embodiment 1 operates in a normally-off or normally-on state can be set by the width of the channel region 21 (the spacing D1 between the strip regions 12A of the first n-type region 12 and the spacing D2 between the strip regions 14A of the second n-type region 14).

The third layer 15 is a layer provided on the second layer 13, and is a layer made of low-concentration n-type gallium oxide. In order to improve the breakdown voltage of the element, the third layer 15 is preferably sufficiently thick, for example, 0.5 to 2 times the thickness of the entire Si semiconductor layer (the sum of the thicknesses of the substrate 10 and the first layer 11), and preferably 1 μm or more. In order to improve the breakdown voltage of the element, the n-type impurity concentration of the third layer 15 is preferably sufficiently low, for example, 1×10 ¹² to 1×10 ¹⁵ cm ⁻³ . The third layer 15 may be non-doped or i-type.

The fourth layer 16 is a layer provided on the third layer 15, and is a layer made of high-concentration n-type gallium oxide. The n-type impurity concentration is, for example, 1×10 ¹⁸ to 1×10 ²¹ cm ⁻³ . The thickness of the fourth layer 16 is, for example, 0.5 to 1 μm.

A groove (notch) 20 is provided in a portion of the fourth layer 16, extending from the surface of the fourth layer 16 to the first n-type region 12. The electrode junction 12B of the first n-type region 12 is exposed at the bottom of the groove 20.

Note that the third layer 15 and the fourth layer 16 may be partially or entirely removed except for the area above the channel region 21.

The cathode electrode 17 is provided on the fourth layer 16. The material of the cathode electrode 17 may be any material that can make ohmic contact with the n-type gallium oxide, which is the material of the fourth layer 16, such as Ti/Au/Al.

The anode electrode 18 is provided on the back surface of the substrate 10 (the surface opposite to the first layer 11). The material of the anode electrode 18 may be any material that can make ohmic contact with the p-type Si material of the substrate 10, such as Al.

The gate electrode 19 is provided on the first n-type region 12 exposed at the bottom of the groove 20. The material of the gate electrode 19 may be any material that can make ohmic contact with n-type Si, such as Al.

The depth of the groove 20 may be set to reach the second n-type region 14, the gate electrode 19 may be provided on the second n-type region 14, and the first n-type region 12 may be indirectly connected to the gate electrode 19 via the second n-type region 14. In short, the gate electrode 19 may be provided so as to be directly or indirectly connected to the first n-type region 12. However, in terms of controllability of the gate current, it is preferable to provide the gate electrode 19 directly on the first n-type region 12 as in the first embodiment.

3. Operation of the Semiconductor Device 1 Next, the operation of the semiconductor device 1 of the embodiment 1 will be described. The semiconductor device 1 of the embodiment 1 has a structure in which an n-type gate region is embedded in the p-type region and i-type region of a pin diode, and is a static induction thyristor (SIThy) in which a positive voltage is applied to the anode electrode 18 with respect to the cathode electrode 17 (i.e., a forward bias is applied to the pin formed by the first layer 11, the second layer 13, and the third layer 15), and the current flowing from the anode electrode 18 to the cathode electrode 17 via the channel region 21 is controlled by the gate current.

When the gate voltage is 0V and the device is in the on state (i.e., anode current flows), it is normally on, and when the device is in the off state (i.e., anode current does not flow), it is normally off. From a fail-safe perspective, it is preferable to have the device be normally off. In the semiconductor device 1 of embodiment 1, it is possible to set whether the device is normally off or normally on by setting the distances D1 and D2.

Figure 6 is a timing chart showing the correspondence between turn-on and turn-off and Vag and Iag. Vag is the voltage of the gate electrode 19 relative to the anode electrode 18, and Iag is the current flowing into the gate electrode 19. Additionally, Vak is the voltage of the anode electrode 18 relative to the cathode electrode 17, and Iak is the current flowing into the anode electrode 18.

First, we will explain the normally-on type. In the normally-on type, a positive predetermined value (for example, 15 V) is applied to Vag to set it to the off state. For example, when Vak is 1000 V, Iak is 0.

In the off state, because there is a hole barrier in the channel region 21, the depletion layers extend from the two first n-type regions 12 and the second n-type region 14 to the channel region 21, and the depletion layers from one side of the first n-type region 12 and the second n-type region 14 overlap with the depletion layers from the other side, depleting the entire channel region 21. As a result, even if the anode-cathode is forward biased, if the voltage is below the forward breakdown voltage, the current from the first layer 11 to the third layer 15 is cut off. If the forward bias between the anode and cathode exceeds the forward voltage, the current flows suddenly.

To turn on (transition from the off state to the on state), a negative predetermined value is applied to Vag and a predetermined Iag (for example, -5 A) is passed. In other words, a forward bias is applied to the pn junction of the first layer 11 and the first n-type region 12 to pass a current. This lowers the barrier for holes in the channel region 21, shrinks the depletion layers extending from the first n-type region 12 and the second n-type region 14, and releases the overlap of the depletion layers. In addition, electrons are injected from the first layer 11 and the first n-type region 12 into the channel region 21, and holes are also injected from the substrate 10, so that conductivity modulation occurs and the channel region 21 becomes low resistance. As a result, the element turns on and a current flows from the anode electrode 18 to the cathode electrode 17, and Vak drops significantly. Once the element is turned on, Vag is lowered and Iag is lowered.

In the on state, the semiconductor device 1 of the first embodiment operates in the same manner as a pin diode formed by stacking the substrate 10, the first layer 11, the second layer 13, the third layer 15, and the fourth layer 16, and Iak is, for example, 100 A. The turn-on operation creates an excess of carriers in the channel region 21, causing conductivity modulation, resulting in operation in the same manner as a pin diode. In this way, the semiconductor device 1 of the first embodiment has a low on-resistance in the on state similar to that of a pin diode.

To turn off the element (transition from the on state to the off state), a predetermined positive value is applied to Vag and a predetermined Iag is passed (for example, 30 A). In other words, a reverse bias is applied to the pn junction between the first layer 11 and the first n-type region 12. This turns off the element, the current from the anode electrode 18 to the cathode electrode 17 becomes zero, and Vak returns to its original value (for example, 1000 V). After the element is turned off, Vag is returned to 15 V.

Next, we will explain the normally-off type. In the normally-off type, the device is in the off state when no voltage is applied to Vag.

To turn it on, a predetermined negative value is applied to Vag, and a predetermined Iag is passed from the anode electrode 18 to the gate electrode 19. In other words, a forward bias is applied to the pn junction between the first layer 11 and the first n-type region 12. Iag is made larger than that of the normally-on type, for example -10 A. Iag is made larger than that of the normally-on type because the turn-on switching speed of the normally-off type is slower than that of the normally-on type, and by making Iag larger, the switching speed is increased.

This turns the element on, causing current to flow from the anode electrode 18 to the cathode electrode 17, and Vak drops significantly. Once the element is on, Vag is lowered, and so is Iag. Vag is not set to 0 to prevent noise or the like from being added to Vag, causing the element to turn off. Operation in the on state is the same as that of a normally on type, and is the same as that of a pin diode.

Turning off is the same as for the normally-on type. That is, a predetermined positive value is applied to Vag and a predetermined Iag (for example, 30 A) is passed. Iag may be slightly lower than in the case of the normally-on type. This turns the element off, the current from the anode electrode 18 to the cathode electrode 17 becomes zero, and Vak returns to its original value (for example, 1000 V). After the element is in the off state, Vag is returned to 10 V. Vag is not returned to 0 to prevent noise, etc. from being added to Vag and causing it to turn on erroneously.

Next, the movement of electrons and holes during turn-off will be explained. When a reverse bias is applied to the pn structure of the first layer 11 and the first n-type region 12, the electrons in the channel region 21 are pulled into the first n-type region 12 and the second n-type region 14, and the holes are pulled into the substrate 10. As a result, the conductivity modulation state of the channel region 21 cannot be maintained, and the channel region 21 returns to its original state in which the entire region is depleted. As a result, the current from the first layer 11 to the third layer 15 is also cut off, and the device is turned off.

In this way, in the semiconductor device 1 of embodiment 1, when the device is turned off, electrons in the channel region 21 are rapidly extracted by the first n-type region 12 and the second n-type region 14, so that the channel region 21 is rapidly depleted. Therefore, the semiconductor device 1 of embodiment 1 has a short reverse recovery time. Here, the reverse recovery time is the time from when a gate voltage that turns the device off in the turned-on state is applied until the device actually turns off (the time until the anode current becomes zero).

4. Breakdown Voltage of Semiconductor Element 1 In the semiconductor element 1 of embodiment 1, as described above, n-type gate regions (first n-type region 12, second n-type region 14) are formed in the p-type first layer 11 and the i-type second layer 13. Therefore, all layers above the second layer 13 can be n-type, and gallium oxide can be used. Most of the voltage between the anode and cathode is applied to the high-resistance and thick third layer 15, which is made of gallium oxide, a material with high breakdown voltage. Therefore, the semiconductor element 1 of embodiment 1 has high breakdown voltage.

As described above, in the semiconductor element 1 of the first embodiment, the element structure including the p-type region and the n-type region is made of Si, and a structure made of gallium oxide not including a p-type region is formed on top of that. This makes it possible to improve the breakdown voltage of the semiconductor element 1 including the p-type region without requiring p-type gallium oxide.

9 to 11 show band diagrams along a line perpendicular to the substrate 10 and passing through the channel region 21, with FIG. 9 showing the steady state, FIG. 10 showing the on state, and FIG. 11 showing the off state.

As shown in FIG. 11, in the off state, a depletion layer extends from the gate region because there is a hole barrier (electron well) in the channel region 21, and holes do not flow beyond the channel region 21 to the cathode side. Also, electrons are trapped by the electron well in the channel region 21 and do not flow to the anode side. As a result, no current flows from the anode to the cathode. Also, because the voltage is mainly applied to the third layer 15, which has a high resistance, the band is greatly tilted in the third layer 15.

On the other hand, as shown in Figure 10, in the on state, electrons are injected from the gate region, lowering the hole barrier in the channel region 21, and the holes pass through the barrier and flow to the cathode side. Also, the electron well in the channel region 21 becomes shallower, and electron traps decrease. Therefore, the electrons flow beyond the well to the anode side. As a result, a current flows from the anode to the cathode.

6. Manufacturing Method of Semiconductor Device 1 Next, a manufacturing method of the semiconductor device 1 of the first embodiment will be described with reference to the drawings.

First, a substrate 10 is prepared, and a first layer 11 made of p-type impurity-doped Si is formed on the substrate 10 by a method such as CVD (see FIG. 4(a)).

Next, n-type impurities are ion-implanted into a predetermined region on the surface of the first layer 11, and the first n-type region 12 is formed by thermal diffusion (see FIG. 4(b)).

Next, a second layer 13 made of gallium oxide is formed on the first layer 11 and the first n-type region 12 (see FIG. 4(c)). The second layer 13 can be formed by a HVPE method, a CVD method, a MOCVD method, or the like.

Next, the region of the second layer 13 above the first n-type region 12 is dry etched to form a groove. The depth of the groove is set to reach the first n-type region 12, and the first n-type region 12 is etched as little as possible. Next, high-concentration n-type gallium oxide is grown to fill the groove. The crystal growth method of the gallium oxide is the same as for the second layer 13. This forms the second n-type region 14 (see FIG. 4(d)).

In the first embodiment, the second n-type region 14 is formed by selective growth, but the second n-type region 14 may also be formed by ion implantation of n-type impurities and heat treatment.

Next, the third layer 15 and the fourth layer 16 are formed in this order on the second layer 13 and the second n-type region 14 (see FIG. 5(a)). The crystal growth method for the third layer 15 and the fourth layer 16 is the same as that for the second layer 13.

Next, a predetermined area on the surface of the fourth layer 16 is dry etched to form a groove 20 deep enough to reach the first n-type region 12 (see FIG. 5(b)).

Next, the back surface of the substrate 10 is thinned by grinding, polishing, etching, etc. After that, a cathode electrode 17 is formed on the surface of the fourth layer 16, an anode electrode 18 is formed on the back surface of the substrate 10, and a gate electrode 19 is formed on the first n-type region 12 exposed at the bottom surface of the groove 20. These electrodes are formed using deposition or sputtering, and are patterned using lift-off. In this manner, the semiconductor element 1 of embodiment 1 shown in FIG. 1 is formed.

(First Modification of First Embodiment)
A first modified example of the first embodiment will be described with reference to Fig. 7. As shown in Fig. 7, the second layer 13 may be present between the upper surface of the second n-type region 14 and the upper surface of the second layer 13. The current between the second n-type region 14 and the third layer 15 is suppressed, and the current easily flows through the channel region 21, thereby reducing the on-resistance.

(Modification 2 of embodiment 1)
A second modified example of the first embodiment will be described with reference to Fig. 8. As shown in Fig. 8, the second n-type region 14 does not have to be provided. However, in order to increase the supply of electrons to the channel region 21 and reduce the on-resistance, it is preferable to provide the second n-type region 14 as in the first embodiment.

(Modification)
In the first embodiment, gallium oxide is used as the material of the second layer 13, 213, the second n-type region 14, the third layer 15, 215, and the fourth layer 16, 216, but the material is not limited to this and may be any gallium oxide-based material. In other words, a material in which part of Ga in gallium oxide is replaced with Al or In may be used.

Although the first embodiment is an SIThy, the present disclosure is not limited to these semiconductor elements. For example, it can also be applied to SITs (static induction transistors), bipolar transistors, FETs, diodes, etc.

This disclosure is not limited to the above embodiments, and can be applied to various embodiments without departing from the spirit of the disclosure.

1: Semiconductor element 10: Substrate 11: First layer 12: First n-type region 13: Second layer 14: Second n-type region 15: Third layer 16: Fourth layer 17: Cathode electrode 18: Anode electrode 19: Gate electrode

Claims (5)

a first region made of Si and including a p-type region and an n-type region;
a second region formed on one surface of the first region, made of a gallium oxide-based material, and not including a p-type region;
a first electrode provided on a surface of the second region opposite to the first region;
a second electrode provided on a surface of the first region opposite to the second region;
A semiconductor element comprising: The first region is
a substrate made of p-type Si and having the second electrode provided on one surface;
a first layer formed on the other surface of the substrate and made of p-type or i-type Si;
a first n-type region made of n-type Si provided in the first layer so as to sandwich the material of the first layer in the layer extension direction of the first layer;
The second region is
a second layer made of an i-type or n-type gallium oxide-based material, the second layer being provided on a surface of the first layer and the first n-type region opposite to the substrate;
a third layer made of an n-type gallium oxide based material provided on a surface of the second layer opposite to the first region;
a third electrode serving as a gate electrode connected to the first n-type region;
having
the first electrode is a cathode electrode,
the second electrode is an anode electrode,
The semiconductor device of claim 1 , wherein the semiconductor device is a static induction thyristor. The semiconductor device according to claim 2, further comprising a second n-type region made of an n-type gallium oxide-based material that is provided in the second layer in contact with the first n-type region and sandwiches the material of the second layer in the layer extension direction of the second layer. The semiconductor device according to claim 2 or 3, wherein the first layer is p-type. The semiconductor device according to claim 2 or 3, wherein the second layer is i-type.

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