JP2024007375A - Substrate transfer method, substrate processing apparatus, and program - Google Patents

Abstract

To suppress variations of a transfer state between substrates after exposure by an exposure machine, and suppress variations of patterns formed on substrates by development.SOLUTION: A substrate transfer method using a substrate processing apparatus comprising a transfer machine group of transferring a substrate to a carrier via a module group and an exposure machine, the transfer machine group including a first transfer mechanism of transferring the substrate in order of a pre-stage module, the exposure machine, and a first post-stage module, a second transfer mechanism of transferring the substrate in order of the first post-stage module, a heating module, a development module, and a second post-stage module, and a post-stage transfer mechanism, the method comprises the steps of: acquiring a segment transfer time required for transferring the substrate to a next transfer segment in each transfer segment corresponded to each transfer mechanism performing transfer of the substrate in a transfer path on a post-stage side of the exposure machine; and carrying-in or carrying-out the substrate to/from the exposure machine by the first transfer mechanism on the basis of a maximum segment transfer time which is the longest time among the segment transfer times.SELECTED DRAWING: Figure 5

Description

The present disclosure relates to a substrate transport method, a substrate processing apparatus, and a program.

In manufacturing semiconductor devices, photolithography is performed on semiconductor wafers (hereinafter referred to as wafers). Specifically, after a resist film is exposed along a predetermined pattern in an exposure machine, the wafer is processed in the order of heating and development called PEB (Post Exposure Bake). transported between Patent Document 1 discloses that the wafer is transported such that the time from exposure to PEB is constant.

Japanese Patent Application Publication No. 2008-130857

The present disclosure provides a technique that can suppress variations in the conveyance state between substrates after exposure by an exposure machine, and suppress variations in patterns formed on the substrates by development.

The substrate transport method of the present disclosure includes a transport mechanism group that transports a substrate taken out from a carrier to the carrier via a module group and an exposure machine,
The module group includes a front module for mounting the substrate at a front stage of the exposure machine;
The exposure machine includes first and second rear-stage modules for mounting the substrate at a rear stage of the exposure machine, a heating module, and a developing module,
The transport mechanism group includes a first transport mechanism that transports the substrate in the order of the front module, the exposure machine, and the first rear module, the first rear module, the heating module, the developing module, and the first rear module. A substrate processing apparatus including: a second transport mechanism that transports the substrate in the order of the second rear module; and one or more rear transport mechanisms that transport the substrate from the second rear module to the carrier. In the board transport method that
In the transport path on the downstream side of the exposure machine, for each transport section corresponding to each transport mechanism that transports the substrate, obtain the section transport time required to transport the substrate to the next transport section. process and
a loading/unloading step of loading or unloading the substrate into or out of the exposure machine by the first transport mechanism based on the longest maximum section transport time among the section transport times;
Equipped with

The present disclosure can suppress variations in the transportation state between substrates after exposure by an exposure machine, and suppress variations in patterns formed on the substrates by development.

1 is a plan view of a coating and developing device according to an embodiment of the present disclosure. FIG. 3 is a longitudinal sectional side view of the coating and developing device. FIG. 3 is an explanatory diagram showing a conveyance path in the coating and developing device. It is an explanatory view showing the above-mentioned conveyance path on the rear stage side of an exposure machine. FIG. 3 is an explanatory diagram for showing an overview of first and second transport control performed in the coating and developing device. FIG. 3 is a flow diagram showing the flow of first conveyance control. It is a flowchart which shows the flow of 2nd conveyance control. FIG. 3 is a schematic diagram of a DEV layer in a coating and developing device for illustrating an example of the first transport control. FIG. 3 is a schematic diagram of the DEV layer for illustrating an example of the first transport control. FIG. 3 is a schematic diagram of the DEV layer for illustrating an example of the first transport control. FIG. 3 is a schematic diagram of the DEV layer for illustrating an example of the first transport control. FIG. 3 is a schematic diagram of the DEV layer for illustrating an example of the first transport control. FIG. 7 is an explanatory diagram showing PJ related to the second transport control. FIG. 7 is an explanatory diagram regarding the second transport control. FIG. 7 is an explanatory diagram regarding third conveyance control performed in the coating and developing device. FIG. 7 is an explanatory diagram of the third transport control. FIG. 7 is an explanatory diagram of the third transport control.

[Configuration of coating and developing equipment]
A coating/developing device 1, which is an embodiment of the substrate processing device of the present disclosure, will be described with reference to a plan view in FIG. 1 and a vertical cross-sectional side view in FIG. 2, respectively. The coating/developing device 1 is configured by connecting a carrier block D1, an intermediate block D2, a processing block D3, and an interface block D4 in a line from side to side. An exposure machine D5 is connected to the right side of the interface block D4 (the opposite side to the side where the carrier block D1 is located).

The carrier block D1 includes a stage 10, and a carrier C, which is a transport container called a FOUP (Front Opening Unify Pod), which can store a plurality of wafers W, can be placed on the stage 10. Further, the carrier block D1 includes a transport mechanism 12, and transfers the wafer W to the carrier C on the stage 10.

The intermediate block D2 is provided with a tower T1 in which a large number of modules are stacked. Each module of the tower T1 can be accessed by the above-mentioned transport mechanism 12, the transport mechanism 13 arranged on the rear side of the tower T1, and the above-mentioned transport mechanism 12. The wafer W can be transferred between each layer of the processing block D3 and the carrier C.

The processing block D3 is composed of layers E1 to E6, which perform liquid processing and heat processing on the wafer W, stacked in order from the bottom. In this example, the levels E1 to E3 are configured in the same way, and a resist film is formed by applying a resist as the liquid treatment. Furthermore, the layers E4 to E6 are configured in the same way, and a resist pattern is formed by development as a liquid treatment. At each level E (E1 to E6), wafers W are transferred and processed in parallel.

Hierarchy E6 shown in FIG. 1 will be described as a representative among the layers E1 to E6. A wafer W transport path 14 extending left and right is formed in the center of the front and back of the floor E6. In front of the conveyance path 14, a plurality of developing modules 15 are arranged side by side on the left and right. At the rear of the transport path 14, heating modules for heating the wafer W are stacked, and a large number of stacked heating modules are arranged side by side on the left and right. Examples of this heating module include those that perform PEB and those that perform post-development heat treatment (post-bake). It is assumed here that two types of heating modules, 1A and 1B, are installed, and unless otherwise specified, heating module 1A performs PEB, and heating module 1B performs post-bake.

The transport path 14 is provided with a transport mechanism 36 that transports the wafer W at the level E6. The transport mechanism 36 includes a base that moves along the transport path 14 and two substrate holders that move forward and backward on the base. One substrate holder moves forward and backward to receive the wafer W from the module, and then the other substrate holder enters the module and sends the wafer W, so that the wafer W is exchanged in the module. I can do it. This replacement of modules may be referred to as replacement transportation. Note that the module is a place other than the transport mechanism where the wafer W is placed, and a module that processes the wafer W may be referred to as a processing module.

The floors E1 to E3 will be explained with a focus on the differences from the floor E6.The floors E1 to E3 are equipped with a coating module that supplies resist to the wafer W to form a resist film instead of a development module. The heating modules in the floors E1 to E3 heat the wafer W after the resist film has been formed. Furthermore, the transport mechanisms for each of the floors E1 to E5, which correspond to the transport mechanism 36, are designated as 31 to 35.

Next, the interface block D4 will be explained. The interface block D4 is provided with a tower T2 and transport mechanisms 21 and 22. A large number of modules are stacked on the tower T2 similarly to the tower T1. The transport mechanism 21 is for transport between the modules of the tower T2, and the transport mechanism 22 is for transport between the modules of the tower T2 and the exposure machine D5. Note that, in reality, the interface block D4 is provided with, for example, more modules, towers, and transport mechanisms than shown in the figure, but they are shown in a simplified manner to avoid complicating the explanation. Regarding the processing block D3 described above, explanations and illustrations of some modules are also omitted.

Towers T1 and T2 will be explained. The towers T1 and T2 are provided with a transfer module TRS and a temperature adjustment module SCPL, and these modules are used for carrying in and out of floors E1 to E6 and for transferring wafers W between blocks and between blocks and exposure machine D5. used. The SCPL is a module that adjusts the temperature of the wafer W, and in addition to the above-mentioned loading/unloading and transfer between blocks, it is also used to adjust the temperature of the wafer W while it is being transported through the hierarchy, and to adjust the temperature of the wafer W just before being transported to the exposure machine. This includes one that adjusts the temperature of the wafer W. The SCPL that adjusts the temperature of the wafer W immediately before being transferred to the exposure machine D5 is referred to as ICPL. A plurality of TRSs and SCPLs are provided for each of the above uses. Furthermore, in the following description, as shown in FIG. 2, TRSs and SCPLs may be appropriately numbered to distinguish between TRSs and SCPLs located at different locations.

[About the exposure machine]
Regarding the exposure machine D5, when the wafer W can be carried in, it outputs a signal to that effect (in-ready signal), and when the wafer W can be carried out, it outputs a signal to that effect (out-ready signal). A control unit 4, which will be described later, receives these signals and controls the operation of the transport mechanism 22, so that the wafer W is transferred between the interface block D4 and the exposure machine D5. The interval from when one wafer W is loaded into the exposure machine D5 until the exposure of the wafer W is finished and an out-ready signal is output is defined as the exposure machine cycle time. When wafers W are sequentially transferred to the exposure machine D5, the exposure machine cycle time (sometimes abbreviated as exposure machine CT) is constant or approximately constant. Alternatively, the out-ready signal is output at approximately constant intervals.

[About PJ]
When the carrier C is carried into the coating/developing device 1, a process job (PJ) is set for the wafer W in the carrier C by the control unit 4, which will be described later. PJ is information specifying a processing recipe for the wafer W (including a transfer recipe such as which type of module to transfer to for processing and to which module of the same type to transfer the wafer W) and the wafer W to be transferred. . In this way, the transport route of the wafer W in the coating and developing device 1 is specified by the PJ, and the wafers W in the same PJ undergo the same processing, so the wafers W in the same PJ are wafers W of the same lot.

Note that the processing recipe specified by the PJ includes information for operating each part constituting the module. More specifically, the information includes the time required for the operation of each part in the module, the heating temperature when heating the wafer W, and the supply of each liquid to the wafer W when performing liquid processing on the wafer W. This includes the timing and order. Therefore, by setting PJ, parameters (MSCT, ACT, etc.) for each transport control described later can be calculated.

Furthermore, if there are multiple wafers W in one PJ and multiple wafers W in other PJs, after the wafers W in one PJ are successively carried into the equipment, the wafers W in other PJs are brought into the equipment in succession. The operation of each transport mechanism is controlled by a control unit 4, which will be described later, so that the transport mechanism is transported to That is, after the wafers W of the preceding PJ are collectively carried into the apparatus, the wafers W of the subsequent PJ are collectively carried into the apparatus. Each wafer W is transported along a transport path specified by each PJ, and is processed by each processing module on the transport path according to a processing recipe specified by each PJ. The PJ wafer W that was transported first is returned to the carrier C first. For one PJ, when all the wafers W of the PJ are returned to the carrier C, the PJ ends.

[About layers]
In order to distinguish the transport mechanisms in the apparatus described above from each other, individual names may be given. Specifically, the transport mechanisms 11 and 12 are sometimes described as PRA11 and MPRA12, respectively, the transport mechanisms 31 to 36 are sometimes described as PRA31 to 36, and the transport mechanisms 21 and 22 are sometimes described as IFB21 and IFBS22, respectively. In addition, in the conveyance route, each section in which conveyance is performed by a different conveyance mechanism is referred to as a "layer." Layers corresponding to transport mechanisms other than PRA (PRA31 to PRA36) are shown with the same name as the transport mechanism. Therefore, the respective layers are referred to as a CRA layer, an MPRA layer, an IFB layer, and an IFBS layer. The layer corresponding to PRA31 to PRA33 is a COT layer, and the layer corresponding to PRA34 to PRA36 is a DEV layer. The DEV layer may be simply written as DEV, omitting the word "layer".

Further, it is assumed that a layer including a plurality of sections that perform the same processing on each wafer W is multi-stacked. That is, a layer that is a multi-stack will each include modules that perform the same processing in the same step, and this section will be referred to as a stack. An example will be shown later in which the wafer W is transported along the transport path H1, and in this transport path H1, the COT layer and the DEV layer each form a multi-stack layer. Note that the layers forming this multi-stack will be described as one layer as a whole. In other words, although we have said that the layers E4, E5, and E6 are each configured in the same way, these three layers (stack) do not form three DEV layers each, but instead have layers E4 to E6. This will be explained assuming that it forms one DEV layer. Although the module configuration of the DEV layer is shown in FIG. 4 and the like, only the modules for one layer are shown, not the entire DEV layer.

Regarding the COT layer and the DEV layer, the transport mechanism of each layer repeatedly moves the modules in the layer in order, and performs the above-mentioned exchange of wafers W for each module except for the module at the entrance and the module at the exit of the layer. Therefore, the conveyance mechanism moves around the conveyance path 14. By such an operation of the transport mechanism, the wafers W are sequentially transported one by one from the upstream module to the downstream module. Note that at the time of PJ switching, there is a case where the wafer W is not transferred to the module due to a gap between the transfers of the wafer W to the module. Regarding other layers, for example, when a wafer W is transferred to an upstream module, a transfer mechanism within the layer receives the wafer W and transfers it to a downstream module. Such transport is referred to as asynchronous transport.

[Description of transport route]
One of the transport routes designated by PJ will be explained as H1. FIG. 3 shows a transport path H1 in units of layers. Note that the exposure machine D5 and the carrier C are shown separately from the layers. FIG. 4 shows the transport order of the modules on the transport path H1 from the module immediately before the exposure machine D5 to the exit of the DEV layer (the entrance of the layer next to the DEV layer). This transport route H1 is a route in which the wafer W passes through one of the floors E1 to E3, an exposure machine D5, and one of the floors E4 to E6, and a resist pattern is formed on the wafer W. .

The wafers W discharged from the carrier C by the CRA 12 are transferred to the transfer module TRS1 of the tower T1, and then distributed by the MPRA 13 to the transfer modules TRS2 at each height of the floors E1 to E3 in the tower T1. The wafer W is then received by the PRA 31 to 33 and transported in the order of temperature adjustment module SCPL1→coating module→heating module. The wafer W, which has been transported in this way and has a resist film formed thereon, is transported to the delivery module TRS3 of the tower T2, and transported in the order of IFB 21 → TRS4 of tower T2 → IFB 21 → ICPL → IFBS 22 → exposure machine D5, and then the resist film is formed. is exposed along a predetermined pattern.

The exposed wafer W is transferred in the order of IFBS22→TRS5 of tower T2, and then distributed by IFB21 to the transfer modules TRS6 at each height of floors E4 to E6. Then, the sheets are transported by the PRA 34 to 36 in the order of heating module 1A→SCPL2→developing module 15. Thereby, the resist film is developed and a resist pattern is formed on the wafer W. Thereafter, the wafer W is transferred to the heating module 1B→SCPL3 of the tower T1, and then transferred to the MPRA13→transfer module TRS7→CRA12→carrier C in this order. Therefore, when looking at layers as units, the transport route H1 transports in the order of CRA layer → MPRA layer → COT layer → IFB layer → IFBS layer → exposure device D5 → IFBS layer → IFB layer → DEV layer → MPRA layer → CRA layer. .

By the way, in a layer, the time interval for transporting the wafer W to the next layer on the transport path is defined as the CT (cycle time) of the layer. To be more specific, it is the time required for one cycle of transport in a layer, that is, the time required to transport the wafer W to the subsequent layer once between each module handled by the transport mechanism. Corresponds to the expected time interval. Specifically, in the above transfer route H1, the destination of the wafer W in the DEV layer is the MPRA layer, and the time interval for transferring one wafer W to the MPRA layer is the CT of the DEV layer. Regarding the MPRA layer, the wafer W is transported to each of the COT layer and the CRA layer, and the total time for transporting the wafer W one by one to both of these layers is the CT of the MPRA. Further, as for the DEV layer and the COT layer, the PRA moves circularly between modules as described above, and the CT of the layer corresponds to the time (circular movement time) in which these circular movements are performed once. Specifically, for a DEV layer or a COT layer, PRA circular movement time/number of stacks=CT of the layer. In other words, regarding the CT of the DEV layer, the value obtained by dividing the time from when the PRA accesses the TRS6, which is the entry module, until the PRA next accesses the TRS6, by the number of stacks is the CT of the DEV layer. The number of stacks is the number of sets when the TRS 6 forming the entrance of the DEV layer, the SCPL 3 forming the exit of the DEV layer, the developing module 15, the heating modules 1A, 1B, and PRA are set.

In the above-described transport path H1, the temperature adjustment module ICPL corresponds to a front-stage module on which a substrate is placed before the exposure machine D5, the delivery modules TRS5 and TRS6 correspond to a first rear-stage module, and SCPL3 corresponds to a second rear-stage module. corresponds to The transport mechanisms 21 and 22 are the first transport mechanisms that transport the wafer W between the ICPL and the exposure machines D5, TRSs 5 and 6, the PRAs 34 to 36 are the second transport mechanisms, and the transport mechanisms 11 and 12 are the transport mechanisms that transport the wafer W from the DEV layer to the carrier C. This corresponds to a latter-stage transport mechanism that transports the wafer W.

[About multi-module]
In one layer, a plurality of processing modules that have the same steps (order of transport) as viewed from the carrier C on the transport path and can each perform the same type of processing on the wafer W are referred to as multi-modules. For example, the four heating modules 1A shown in FIG. 4 constitute the same multi-module, and the two temperature adjustment modules SCPL2 constitute the same multi-module. The above-mentioned PJ also specifies how many processing modules to use among the multi-modules. Multi-modules may be distinguished from each other by adding a number after a hyphen.

[About the control unit]
As shown in FIG. 1, the coating and developing device 1 includes a control section 4 configured by a computer. The control unit 4 includes a program 41. The program 41 includes step groups such that the wafer W is transported and the wafer W is processed in each module, which will be described later, and a control signal is output to each module and each wafer W transport mechanism. Each module and transport mechanism operate according to the control signal. The program 41 is stored in a storage medium such as a compact disk, hard disk, or DVD, and installed in the control unit 4. Furthermore, the program 41 can execute each transport control described later by performing various calculations, comparisons, and determinations necessary for performing each transport control. Note that the comparison here also includes cases where numerical values are subtracted from each other.

The control unit 4 is also provided with a setting unit 42 for the user of the device to make various settings, and is configured with a mouse, a keyboard, a touch panel, and the like. The setting unit 42 can perform various settings and selections that can be carried out in selecting each transport control, blocking of modules and/or layers, and performing each transport control, which will be described in detail later. Although not shown, the control unit 4 is provided with a storage unit that stores various parameters necessary for executing each transport control. Further, the control unit 4 is provided with an alarm output unit that outputs an alarm by sound, screen display, or the like. For example, as will be described later, an alarm is output when the wafer W cannot be carried into the exposure machine D5.

[Overview of transport control]
An overview of the conveyance control performed by the control unit 4 will be described below. As shown in the example of the transport path H1, this transport control includes the time from the output of the out-ready signal of the exposure machine D5 to the start of PEB (Post Exposure) when processing the wafer W in each DEV layer after exposure. Delay (PED time) is made constant or approximately constant between wafers W. Note that the PED time is made to fall within a predetermined range not only within the same PJ but also between different PJs. As described above, by suppressing the variation in the PED time between each wafer W, the diffusion of acid generated in the chemically amplified resist by exposure with the exposure machine D5 is uniformed between the wafers W, and the width of the resist pattern is uniform. enhance sexuality.

Furthermore, an overview of transport control will be described. Assume that the wafers W of each PJ are sequentially transported through the apparatus as shown in FIGS. 3 and 4. Here, if the transport of the wafer W is delayed in any layer on the subsequent stage (downstream side) of the exposure machine D5 in the transport path H1, and the wafer W stays, the transport of the wafer W also occurs in the layer on the upstream side. There is a risk that there will be a delay. Therefore, if the interval at which the wafer W is transferred from the exposure machine D5 to the subsequent stage is not controlled, there is a risk that, for example, a situation may arise in which the wafer W has to stay in the TRS of the tower T2, which is the entrance to the DEV layer. As described above, the PRAs 34 to 36 of the DEV layer cyclically move to transport the wafer W. Therefore, once the PRAs 34 to 36 receive one wafer W from the TRS at the entrance of the DEV layer, they cannot receive the next wafer W from the TRS until the rotation is completed. Therefore, the time interval between being transported to the TRS and being received by the PRA 34 to PRA 36 is relatively long, and the transport to the heating module 1A is also delayed, which may cause variations in PED time.

Therefore, in the transport control of this embodiment, the exposure machine D The interval at which wafers W are unloaded from the wafer W is controlled. Note that regarding the final layer (CRA layer) on the transport route, the above-mentioned "next layer" corresponds to carrier C. By controlling the unloading interval from the exposure machine D5 and controlling the amount of wafers W flowing into the DEV layer, the wafer W is prevented from staying at the entrance of the DEV layer, and the PED time is increased. This prevents the PED time from occurring and keeps the PED time within a predetermined range.

As described above, in the transport control of this embodiment, the wafer is transferred to the exposure machine D5 according to not only the transport situation from the exposure machine D5 to the heating module 1A that performs PEB, but also the transport situation on the downstream side of the heating module 1A. This means that the transport of W is controlled. In this way, variations in PED time can be suppressed more reliably by being adapted to the transport situation of each layer. Further, by considering the transport status of each layer in this way, even if blocking of modules is performed, fluctuations in the PED time can be suppressed. Conveyance control for suppressing fluctuations in PED time in this way includes a first conveyance control and a second conveyance control, and either of these is selected and executed by the user of the coating/developing device 1. .

[About parameters used for transport control (MUTCT, MSCT, ACT)]
In giving a more detailed outline of the first and second transport controls, Max Step Cycle Time (MSCT) and Arm Cycle Time (ACT), which are parameters used in these transport controls, will be explained. From the processing recipe specified by PJ, for each module, "wafer W processing time" + "time required before and after processing (OHT: Over Head Time)" = "required stay time of wafer W in the module (MUT: Module Using Time) is calculated. Then, the calculation according to Equation 1 below is performed.
(MUT÷Number of usable modules)×Transport ratio...Formula 1

The number of usable modules in Equation 1 is the number of usable modules in the step where the MUT was calculated, and is the number in one stack, and is the number of modules that can be used to prevent trouble or blocking from occurring based on the number of modules set in PJ. This reduces the number of modules left unused. The transport ratio in the above formula is the number of wafers W transported to one stack divided by the number of wafers W transported to all usable stacks constituting the multi-stack. The calculation of Equation 1 is performed for each stack for a module at an arbitrary step, and the maximum value among the calculated values is taken as the MUT cycle time (MUTCT). In one layer, the above MUTCT is calculated from each module except the inlet module and the outlet module (that is, the module that is also used in another layer).

Specifically, it is assumed that the DEV layer consists of three stacks, all three of which can be used, and the PJ specifies that the wafers W are evenly transferred to these three. Therefore, the transport ratio is 1/3. Under these conditions, assuming that the MUT of this developing module 15 is J seconds and four developing modules can be used in each stack, it is calculated from Equation 1 as J seconds/4 x 1/3 = J/12 seconds. be done. Since the transport ratio is the same between each stack, it is calculated in the same way between each stack, so the maximum value calculated by Equation 1 is J/12 seconds. Therefore, MUTCT (Module Using Time Cycle Time) of the developing module 15 is calculated as J/12 seconds.

In the DEV layer, the MUTCT of each module is similarly calculated for the heating module 1A and the like. As mentioned above, MUTCT is calculated for modules other than the modules forming the entrance and exit of the layer, so for the DEV layer, MUTCT for heating modules 1A, 1B, SCPL 2, and developing module 15 is calculated. be done.

Note that since the processing time of the module used to calculate the MUTCT is set for each PJ, the MUTCT will be calculated for each PJ. Furthermore, in Equation 1, the transport ratio is calculated as 1 for layers other than multi-stack and asynchronous transport layers (in this example, layers other than multi-stack = asynchronous transport layer). The maximum MUTCT obtained from the layer to be obtained (described later) is called Max Step Cycle Time (MSCT).

Next, Arm Cycle Time (ACT) will be explained. The number of steps in which the transfer mechanism (transfer arm) transfers the wafer W from the entrance to the exit of the layer is defined as the number of transfer steps. Concerning the transport path H1, the DEV layer is transported five times in the order of TRS6→heating module 1A→temperature adjustment module SCPL2→developing module 15→heating module 1B→SCPL3, so the number of transport steps is five. To exemplify other layers, the MPRA layer is transported twice, such as from TRS1 to TRS2 and from SCPL3 to TRS7, so the number of transport steps is two.

The set time required for one conveyance process is predetermined, and is, for example, K seconds. Then, ACT=number of transfer steps×set time ÷number of multi-stack capable of transferring wafers W. Regarding the above DEV layer, there are three stacks, and assuming that the wafer W can be transferred to all of them, ACT is calculated as 5×K÷3=5K/3 seconds. Note that for layers other than multi-stack and asynchronous transport layers, the number of multi-stack is calculated as 1. Up to this point, only the transport route H1 has been illustrated in FIGS. 3 and 4 as an example of the transport route, but various transport routes are set by PJ. That is, since the number of conveyance steps differs depending on the PJ, the ACT is also calculated for each PJ.

Note that the cycle time of the layer described above can be set to be longer than the larger of the maximum value of MUTCT and ACT obtained from each module in one layer. The layer cycle time thus obtained from MUTCT and ACT corresponds to the expected transfer time required to transfer the wafer W to the next layer.

[About the outline of the first and second transport control]
As described above, the wafer W is conveyed into the coating and developing device 1 in batches for each PJ. Therefore, when the wafer W of an arbitrary PJ transported on the transport path H1 is transported from the temperature adjustment module ICPL to the exposure machine D5 or unloaded from the exposure machine D5, each layer on the downstream side of the exposure machine D5 on the transport path H1 is , a wafer W in the same PJ as the wafer W, or a wafer W in a PJ that is earlier than the wafer W can be located. The arbitrary PJ obtains MUTCT (Module Using Time Cycle Time) and MSCT (Max Step Cycle Time) as well as ACT (Arm Cycle Time) from each layer that is scheduled to pass through at the subsequent stage of exposure machine D5. The maximum of MSCT and ACT is determined as the maximum cycle time after exposure.

The layer for which the maximum cycle time after exposure (hereinafter sometimes referred to as maximum CT after exposure) is the layer that takes the longest expected time to transport the wafer W to the next layer. This layer is the so-called bottleneck when carrying out subsequent stage conveyance. The maximum CT after exposure is the expected transport time, and in the first transport control and the second transport control, the wafer W is transferred from the exposure machine D5 or the wafer is transferred to the exposure machine D5 based on the maximum CT after exposure. W is transported. In the first transport control, the timing of transporting the wafer W from the exposure machine D5 is controlled, and in the second transport control, the timing of transporting the wafer W to the exposure machine D5 is controlled. Note that since MUTCT and ACT may differ depending on the PJ, these MUTCT and ACT are calculated for each PJ to determine the maximum CT after exposure. For one layer, the larger of the maximum value of MUTCT and ACT corresponds to the section transport time required to transport one wafer W to the next layer. MUTCT and ACT in one layer correspond to the first and second candidates for the section transport time, respectively. Further, the maximum post-exposure CT corresponds to the longest maximum section transport time among the section transport times.

The outlines of the first transport control and the second transport control are shown in the upper and lower parts of FIG. 5, respectively. Further, FIG. 6 shows an outline of the first transport control, and FIG. 7 shows an outline of the second transport control, respectively, in a manner different from that in FIG. 5. In each figure, the maximum CT after exposure is X seconds, and the exposure machine CT is Y seconds. The dotted line arrow in FIG. 5 shows the interval at which the wafers W are carried into the exposure machine D5 and the interval at which the out-ready signal R1 is output. Indicates the unloading interval.

In the first transfer control, the wafers W are sequentially transferred from the ICPL to the exposure machine D5 while the in-ready signal is output (upper stage of FIG. 6). In the exposure machine D5, the wafer W is processed with Y seconds as one cycle. When the out-ready signal R1 for an arbitrary wafer W is output (middle stage in FIG. 6), after Z seconds have passed since the output (that is, after the wafer W has been placed on standby for Z seconds in the exposure machine D5), the IFBS22 receives the wafer W and transports it to the subsequent TRS 5 (lower stage in FIG. 6). This waiting time Z seconds = X seconds - Y seconds.

Due to the transport mode as described above, as shown in FIG. It is transported to the DEV layer. Due to the transport control, the time from unloading from the exposure machine D5 to transporting to the heating module 1A becomes constant or approximately constant among the wafers W, and the PED times of the wafers W become uniform. Note that in this first transport control, the output interval of the out-ready signal R1 is treated as the exposure machine CT. Therefore, in this first transport control, the wafer W is unloaded from the exposure machine D5 based on the unloading interval at which the wafer W can be unloaded from the exposure machine D5 and the maximum CT of the exposure machine.

On the other hand, in the second transfer control, after the in-ready signal R2 is output (upper row of FIG. 7), after Z seconds have elapsed (that is, after the wafer WZ seconds have been placed on standby at the ICPL), the IFBS 22 receives the wafer W from the ICPL and exposes it. Transfer to machine D5 (middle row in Figure 7). Z seconds = X seconds - Y seconds. Since the wafer W is transported after the output of the in-ready signal R2 in this manner, the interval at which the out-of-ready signal R1 is output is X seconds, which is longer than that of the exposure machine CT. Then, as soon as the out-ready signal R1 is output, the IFBS 22 transports the wafer W to the subsequent TRS 5 (lower stage in FIG. 7).

Since the second transport control is in this manner, as shown in FIG. Control is performed so that the wafer W is transferred to the DEV layer. Therefore, the interval from the output of the out-ready signal R1 to the time when the wafers are transferred to the heating module 1A is constant or approximately constant among the wafers W, and the PED times of the wafers W are the same. Note that in this second transfer control, the wafer W is transferred immediately after the out-ready signal is output, so that the time that the exposed wafer W is exposed to air before PEB is performed can be shortened. Therefore, there is an advantage that the deviation from the design value regarding the width of the resist pattern can be suppressed more reliably.

〔blocking〕
By the way, blocking can be performed by the user specifying a stack constituting a module or a layer from the operation section of the control section 4. The wafer W is not transferred to the module or stack where this blocking has been performed. As mentioned above, MSCT and ACT are calculated based on the number of modules used among these multi-modules and the number of stacks used, so when blocking is performed, this MSCT is recalculated and the exposure After that, the maximum CT will be reset. In addition to blocking performed by the user as described above, recalculation is also performed in the same way when an unusable module or unusable stack occurs due to the detection of a trouble. In this way, if the number of modules used or the number of usable stacks changes, the maximum CT after exposure is reset based on the changed number, thereby ensuring that variations in PED time are reduced. suppressed. Note that the user can also perform blocking, which instructs the transport mechanism to stop its operation, from the operation unit of the control unit 4. This stopping of the operation of the transport mechanism is described as arm blocking.

[About the outline of the third transport control]
By the way, the time from the end of PEB to the start of development is called PPD (Post PEB Delay) time. Under the situation where the second transport control is being executed, the user can select whether or not to enable execution of the third transport control for suppressing fluctuations in PPD time within the same PJ. The shape of the pattern on the wafer W may also change due to this variation in PPD time. In particular, when the resist film is composed of a resist containing metal, there is a concern that the change is relatively large, and this third transport control can be particularly effective.

As described above, when transporting each wafer W of the same PJ, the PRA 34 to PRA 36 of the DEV layer operate cyclically, and the wafers W are exchanged and transported. The time corresponding to the time for one round is the CT (cycle time) of the DEV layer. One wafer W is transferred from each stack to the next layer in one round of each of PRA34-36, so as mentioned above, CT of DEV layer = round trip time of PRA34-36/number of stacks. be.

Here, it is assumed that the exposure machine CT is long and becomes a bottleneck in carrying out transportation. In other words, when one PJ passes through the exposure machine D5 and is transported through the DEV layer, each MUTCT (Module Using Time Cycle Time) and ACT (Arm Cycle Time) calculated in the DEV layer are relatively small. shall be taken as a thing. In this way, in the DEV layer, even if each MUTCT and ACT are small, in order to carry out the above-mentioned exchange transport, the CT of the DEV layer becomes the exposure machine CT at least until all the wafers W of the PJ pass through the exposure machine D5. The operations of PRA34 to PRA36 are adjusted accordingly. Therefore, if the exposure machine CT is 50 seconds, the circular movement time of PRA34 to PRA36 is 150 seconds, and the CT of the DEV layer is the same as the exposure machine CT, 50 seconds (150 seconds/number of stacks: 3). It will be adjusted accordingly.

Suppose that after all the wafers W of the PJ have passed through the exposure machine D5 and are transferred to the DEV layer, for example, in order to obtain a high throughput, the alignment of the CT of the DEV layer to the exposure machine CT is canceled. In other words, it is assumed that the rotation speed of the PRA 34 to PRA 36 in the DEV layer is changed so that the CT of the DEV layer becomes the original CT (the time of the larger of the maximum value of MUTCT and ACT in the DEV layer). However, in this case, the wafer W in the latter stage of the PJ, at least the last wafer W in the PJ, is transported within the DEV layer faster than the wafer W in the previous stage of the PJ, so the PPD time between wafers W in the same PJ is will vary.

Regarding the third transfer control, for the wafers W of the same PJ to be transferred to the DEV layer, the relevant The CT of the DEV layer is controlled so as not to change, thereby suppressing variation in PPD time between wafers W of the PJ. Assuming that the DEV layer is a multi-stack as described above, the first wafer W of the PJ to be transferred to one stack is transferred to the stack, and then the last wafer W of the PJ is transferred to the stack. The time for the PRA to circulate in the stack is maintained until it is transported to the exit module.

Note that since the alignment of the CT of the DEV layer with the exposure machine CT is carried out depending on conditions, there may be cases where this alignment is not carried out. In that case as well, the CT of the DEV layer does not change until the last wafer W of the same PJ is transferred to the module at the exit of the stack of DEV layers, and fluctuations in the PPD time are suppressed.

[Explanation of different flows]
Before specific explanation of each transport control, different flows will be explained. Regarding the subsequent steps of exposure machine D5, PJs that satisfy any of the following conditions are considered to have different flows. One case is that the number of steps is different between the starting PJ and the late starting PJ. Specifically, for example, a module that passes through one of the PJs may not pass through the other PJ.

Another case is when different modules are used in the same step. Specifically, the wafer W is transferred to the heating module in the same step in both the first PJ and the second PJ, but 1A is used as the heating module in the first PJ, and 1B is used as the heating module in the second PJ. Another example is where the same multi-module is used in the first PJ and the second PJ, but those with different numbers (that is, those located in different locations) are used. Another example of a different flow is that among the multi-modules, the number of modules set as modules to be used in the first PJ and the second PJ may be different. As described above, PJs with different flows have different transport routes.

Each transport control will be explained in detail below. In the explanation, the wafers W of the first PJ-A and the wafers W of the second PJ-B may be expressed as A1, A2, A3, . . . , B1, B2, B3, . . . , respectively. Alphabetical characters represent PJs, and numbers represent the order of loading into the apparatus in one PJ. Note that, as described later, depending on the PJ, there are cases where the transport route does not pass through the exposure machine D5, but here, each PJ is transported along the transport route H1 that passes through the exposure machine D5 explained in FIGS. 3 and 4. shall be taken as a thing.

[Details of first conveyance control]
The first transport control will be explained in detail below. When performing the first transport control, the maximum CT after exposure is determined, but as described above, the first transport control is a bottleneck on the transport path of the wafer W being unloaded from the exposure machine D5. Accordingly, the timing of unloading from the exposure machine D5 is controlled. Therefore, the project to which the MSCT (Max Step Cycle Time) and ACT (Arm Cycle Time) necessary for determining the maximum CT after exposure are calculated is the PJ to which the project carried out from the exposure machine D5 belongs ( For convenience, it is referred to as a carry-out PJ), or it is a PJ that precedes the carry-out PJ, is not finished, and passes through any layer that the carry-out PJ passes after the exposure machine D5. The starting PJ is not limited to one, but may be multiple.

Furthermore, calculation of MUTCT (Module Using Time Cycle Time) and ACT, which are the basis of MSCT, will be described. Regarding the layers, for the purpose of carrying out transport according to the bottleneck described above, the layer through which the above-mentioned carry-out PJ passes after the exposure machine D5 is the calculation target. Therefore, the target layers are the IFBS layer, IFB layer, DEV layer, MPRA layer, and CRA layer. The wafer W of the PJ to be calculated exists, and MUTCT and ACT are calculated from the layer to be calculated. Then, the maximum value of MSCT, which is the maximum value of MUTCT obtained from each layer, and the maximum value of ACT obtained from each layer, is determined as the maximum CT after exposure. When the out-ready signal is output from the exposure machine D5, the maximum CT after exposure is determined and the exposure machine CT is obtained from the out-ready signal.

Regarding the exposure machine CT, the interval between the timing at which the out-ready signal R1 is output and the timing at which the out-ready signal R1 is output immediately before that is obtained by regarding the exposure machine CT as the exposure machine CT. Then, the exposure machine CT is compared with the maximum post-exposure CT, and it is determined whether or not to suppress the wafer W from being carried out from the exposure machine D5. When carrying out the restraint, the waiting time in the exposure machine D5 is determined from the time when the out-ready signal R1 is output until the time when the exposure machine D5 carries out the transport. This waiting time corresponds to Z seconds explained in FIG. 6, and is a time corresponding to the difference between the exposure machine CT and the post-exposure maximum CT.

FIG. 8 shows a state in which the wafers W of PJ-A are sequentially passed through the exposure machine D5 and loaded into the DEV layer. Then, it is assumed that an out-ready signal R1 is outputted from the exposure machine D5, and the wafer A9 is carried out from the exposure machine D5. Assuming that the interval from when the out-ready signal R1 is output to when the immediately preceding out-ready signal is output (that is, the interval at which each out-ready signal is output for wafers A8 and A9) is 20 seconds. 20 seconds is considered as exposure machine CT. It is assumed that the maximum post-exposure CT obtained is 22 seconds at the time when the out-ready signal R1 for wafer A9 is issued.

In other words, the situation shown in FIG. 8 is that the maximum CT after exposure>the exposure machine CT. When the post-exposure maximum CT and the exposure machine CT have such a relationship, it is determined to suppress the wafer W from being carried out from the exposure machine D5. Furthermore, it is determined that the wafer A9 is to be unloaded from the exposure machine D5 when the time equal to the difference between the exposure machine CT and the maximum post-exposure CT has elapsed from the output of the out-ready signal R1 for the wafer A9. Specifically, in the situation shown in FIG. 8, the operation of the IFBS 22 is controlled so that the wafer A9 is unloaded from the exposure machine D5 22 seconds-20 seconds=2 seconds after the out-ready signal R1 is output.

In the situation shown in FIG. 8, as described above, among the layers in the latter stage of the exposure machine D5, there is a layer that requires 22 seconds, which is longer than the 20 seconds of the exposure machine CT, to transport one wafer W to the next layer. It means that there is. If the wafer A9 is immediately unloaded from the exposure machine D5 after the out-ready signal R1 is output, there is a risk that the wafer A9 will remain in the path before being conveyed to the DEV layer heating module 1A. Delay the removal of

FIG. 9 differs from the situation described in FIG. 8 in that the exposure machine CT is 22 seconds and the maximum post-exposure CT obtained is 20 seconds. Therefore, in FIG. 9, the maximum CT after exposure is smaller than the exposure machine CT. In such a relationship, as soon as the out-ready signal R1 is output, the IFBS 22 receives the wafer A9 and transports it to the subsequent TRS. In other words, the suppression of unloading of the wafer W from the exposure machine D5 after the output of the out-ready signal R1 described in FIG. 8 is not performed. This is because the exposure machine D5 is the bottleneck for transportation, and the stagnation of the wafer W at a stage subsequent to the exposure machine D5 is suppressed. Based on the same principle, even when the maximum CT after exposure is the exposure machine CT, the removal from the exposure machine D5 is not suppressed.

10 differs from the state described in FIG. 8 in that the maximum cycle time after exposure changes from 22 seconds to 24 seconds due to blocking of the heating module 1A-1. Since recalculation was performed due to blocking, there is a change in the maximum CT after exposure compared to the state shown in FIG. In the state of FIG. 10, as in the state of FIG. 8, since the maximum CT after exposure>the exposure machine CT, the wafer W is suppressed from being carried out from the exposure machine D5, and the maximum CT after exposure - from the output of the out-ready signal R1. After the exposure machine CT time has elapsed, the wafer W is unloaded from the exposure machine D5. Specifically, the wafer W is unloaded from the exposure machine D5 24 seconds-20 seconds=4 seconds after the out-ready signal R1 is output.

FIG. 11 shows a state in which PJ-A and PJ-B are each being transferred in one stack of the same DEV layer, and wafer B7 is being transferred from exposure machine D5, and exposure machine CT is transferred in 20 seconds. be. Since PJ-A and PJ-B are transported by the same transport route H1, the ACT (Arm Cycle Time) of the DEV layer is the same, but the MUTCT (Module Cycle Time) of the DEV layer between PJ-A and PJ-B is the same. The maximum value of ``Using Time Cycle Time'' is different. The maximum time among the MUTCT and ACT of the DEV layer for PJ-A is 22 seconds, and the maximum time of the MUTCT and ACT of the DEV layer for PJ-B is 19 seconds. Note that the MUTCT and ACT acquired from each layer other than the DEV layer at the subsequent stage of the exposure device D5 are both smaller than 19 seconds.

In this case, the maximum CT after exposure is determined to be 22 seconds calculated from PJ-A according to the rules described above. Then, since the maximum CT after exposure is greater than the exposure machine CT, the removal of the wafer B7 from the exposure machine D5 is suppressed, and after 22 seconds - 20 seconds = 2 seconds after the out-ready signal R1 is output, the wafer WB7 is exposed. Unloading from machine D5 is performed. In this way, when a plurality of PJs (that is, wafers W of a plurality of lots) are located in one layer, the MUTCT is calculated for each PJ, and the maximum CT after exposure is determined.

FIG. 12 shows a state in which PJ-A and PJ-B have different flows from each other, and PJ-A is passing through exposure machine D5 and is conveying each layer downstream of exposure machine D5, including the DEV layer. In this case, the PJ-B is not transported to the exposure machine D5, but waits in a module on the front stage of the exposure machine D5. That is, each wafer W of PJ-B is transported to ICPL, which is a module immediately before exposure machine D5, but is not transported to exposure machine D5. When all the wafers W of PJ-A are stored in the carrier C and PJ-A is completed, each wafer W of PJ-B is sequentially transferred to the exposure machine D5 and the subsequent stage, as explained above. Conveyance control is performed.

If PJs with different flows coexist in the subsequent stage of exposure machine D5, there is a risk that relatively large fluctuations in PED time may occur due to changes in the transport operation of each transport mechanism when PJs are switched. In order to prevent this variation, when the earlier PJ (first lot) and the later PJ (second lot) have different flow relationships, the exposure machine D5 of the later PJ is transferred until the earlier PJ is finished. transportation.

[Details of second transport control]
Next, the second transport control will be explained in detail. The maximum CT after exposure is also determined when performing the second transport control. As described above, the second transport control, like the first transport control, controls the transport interval from the exposure machine D5 in accordance with the bottleneck in the transport path of the wafer W after the exposure machine D5. Therefore, the project target for calculating the MUTCT (Module Using Time Cycle Time) and ACT (Arm Cycle Time) necessary for determining the maximum CT after exposure is a wafer W that meets the following conditions α or β. . Note that the number of PJs that meet the condition β is not limited to one, as in the case of the first conveyance control. FIG. 13 shows the PJs set on the wafer W as A, B, C, and D in order from the first one, and shows the correspondence between these PJs A to D and conditions α and β. Those that meet condition α are PJ-D, and those that meet condition β are PJ-A to PJ-C.
Condition α: PJ to which the next project scheduled to be delivered to exposure machine D5 belongs (for convenience of explanation, it will be referred to as delivery PJ)
Condition β: A PJ that is earlier than the carried-in PJ, is not finished, and passes through any layer that the carried-in PJ passes after exposure machine D5.

Furthermore, regarding the calculation of MUTCT and ACT in terms of layers, for the purpose of carrying out transportation according to the bottleneck described above, the layers that the above-mentioned carry-in PJ passes after the exposure machine D5 are to be calculated. In the second transport control, as in the first transport control, there is a wafer W of PJ to be calculated, and MUTCT and ACT are calculated from the layer to be calculated, and the maximum value of them is determined as the maximum CT after exposure. That will happen.

To explain this determination in more detail, all of PJ-A to PJ-D shown in FIG. It has become. In other words, the wafer W of this PJ-D corresponds to the wafer W scheduled to be carried into the exposure machine D5 next, and the IFBS layer, DEV layer, MPRA layer, and CRA layer, which are the transfer destinations of the wafer W of this PJ-D, are This is the layer to be calculated. If wafers W of PJ-A to PJ-D are located in the IFBS layer, DEV layer, and MPRA layer among them, and none of the wafers W is located in the CRA layer, the MUTCT from the IFBS layer, DEV layer, and MPRA layer is , ACT are calculated, and the maximum CT after exposure is determined. Note that the determination of the post-exposure maximum CT described above is the same in the first transport control.

Then, with the exposure machine D5 outputting an in-ready signal and the wafer W being placed on the ICPL, the above-described maximum CT after exposure is calculated. Then, if the time elapsed since the wafer W was transferred to the exposure machine D5 immediately before is G1, and the time required to transfer the wafer W from the ICPL to the exposure machine D5 is G2, the total time of G1 and G2 is calculated, A comparison is made between the total time (G1+G2) and the maximum CT after exposure. As a result of the comparison, if the maximum post-exposure CT>time G1+time G2 (the case shown in the upper part of FIG. 14), it is determined that the wafer W at the ICPL is to be kept on standby at the ICPL. Note that the parameters for calculating the time G2 (the time required for the transport mechanism 22 to move between the exposure machine D5 and ICPL, and the movement of the wafer W to each of the exposure machine D5 and ICPL due to the movement of the substrate holding section of the transport mechanism 22) The time required for the delivery of the data) is stored in the control unit 4, so that the time G2 can be calculated. It is also assumed that the control unit 4 stores the time when the in-ready signal is output, and can also acquire the time G1.

If it is determined to wait the wafer W at the ICPL, the waiting time at the ICPL is calculated as the maximum CT after exposure - time G1 - time G2. That is, the wafer W is kept on standby in the ICPL for a time corresponding to the difference between the maximum CT after exposure and the total time of times G1 and G2. Note that the standby time calculated in this way corresponds to Z seconds explained with reference to FIG. By calculating the waiting time as the time based on the maximum CT after exposure in this way, the interval at which the wafer W is unloaded from the exposure machine D5 can be adjusted as in the case of performing the first transfer control, and the interval before PEB is performed. This prevents the wafer W from staying in the area.

On the other hand, if it is determined that the maximum post-exposure CT≦time G1+time G2, the wafer W transferred to the ICPL is transferred to the exposure machine D5 without waiting at the ICPL. The example shown in the lower part of FIG. 14 shows a case where the ICPL standby is not performed because the maximum CT after exposure<time G1+time G2. The reason for not waiting in this way is that the exposure machine D5 is the bottleneck for transport (that is, the stage downstream from the exposure machine D5 is not the bottleneck for transport). This is because it is expected that there will be no stagnation in the transfer of the wafer W until it reaches the heating module 1A for PEB.

[Conditions for stopping transport to exposure machine]
During execution of the second conveyance control, as well as during execution of the first conveyance control, in order to more reliably suppress fluctuations in PED time, if the first PJ and the subsequent PJ have different flow relationships, the first PJ The subsequent PJ is not transferred to the exposure machine D5 until all the wafers W are transferred to the carrier C and the PJ is completed. Therefore, as shown in FIG. 12, PJ-A and PJ-B have different flows from each other, and while PJ-A passes through exposure machine D5 and is being transported to the downstream stage of exposure machine D5 containing the DEV layer, PJ-A and PJ-B have different flows. -B is transported to ICPL, which is the module immediately before exposure machine D5, but is not transported to exposure machine D5. After PJ-A ends, PJ-B is sequentially conveyed to exposure machine D5.

Further, during execution of the second transfer control, if the wafer W located in the ICPL is a step and/or layer that passes after the exposure machine D5 and satisfies any of the following conditions 1 to 4, the wafer W is not transported to the exposure machine D5. Condition 1 is that arm blocking is instructed to the transport mechanisms of all stacks in the multi-stack. Specifically, as described above, this is a case where arm blocking is instructed to all of the PRAs 34 to 36 of the three DEV layer stacks. Condition 2 is that arm blocking is not specified, but all modules in the same layer and step are disabled. Specifically, when the wafer W is transported and processed through the transport path H1, all the development modules 15 in the DEV layer (that is, the development modules 15 in all three stacks) are unusable. do. In that case, condition 2 is met.

Before explaining conditions 3 and 4, the bypass target module and inspection module will be explained. A module that is set so that when a module becomes unusable, the wafer W can be transferred to a module following the module without going through that module is a module to be bypassed. do. Modules that cannot be transported in this manner are designated as non-bypass modules. In other words, the bypass target module is a module that is allowed not to transport the wafer W to the module, but all the modules on the above-mentioned transport path H1 are assumed to be bypass target modules. Further, the coating/developing device 1 may be equipped with an inspection module for imaging the wafer W on an arbitrary layer such as the DEV layer and performing a predetermined inspection. Since the purpose is to perform such an inspection, transportation to the inspection module can be omitted. Condition 3 is a case in which module blocking is not instructed in the subsequent stage of the exposure machine D5, and all modules that are not subject to bypass in a certain step are unusable. Condition 4 is a case where all modules other than the inspection module that are not subject to bypass at a certain step in the subsequent stage of the exposure machine D5 cannot be transported.

In this way, conditions 1 to 4 mean that the wafer W located in the ICPL cannot be transported to the layer it is scheduled to pass through and/or the module it is scheduled to pass through, and if it is transported to the exposure machine D5, it will not be transferred to the subsequent stage of the exposure machine D5. It is set so that when the state is such that the conveyance must be stopped, the conveyance to the exposure machine D5 is stopped. That is, if the wafer W cannot be transferred between one module in the downstream stage of the exposure machine and another module in the downstream stage of the one module, the wafer W is not transported to the exposure machine D5. Then, when none of the above conditions 1 to 4 apply and the situation in which the transport must be stopped is resolved, the wafer W is transported from the ICPL to the exposure machine D5.

[Supplementary explanation of the layer targeted for parameter calculation]
In performing the second conveyance control, it has been described that if the first PJ has a different flow from the later PJ, the later PJ is not conveyed to the exposure machine D5. However, the user can select whether or not to stop the conveyance to the exposure machine D5 due to the existence of such a different flow. More specifically, even if the first PJ and the second PJ pass through different layers and/or modules, it is possible to set the second PJ to be transported to the exposure machine D5 before the first PJ ends. be. This setting is set as a different flow permissible setting. By setting the different flow tolerance, it is possible to prevent the exposure machine D5 from waiting for a later PJ until the first PJ is finished, thereby increasing throughput. Assuming that the subsequent PJ passes through each layer described in the transport path H1, when the wafer W of this subsequent PJ is transferred to the ICPL, in order to obtain the maximum post-exposure CT required for the second transfer control as described above. The following is a supplementary explanation of the target layer for obtaining the MUTCT and ACT required for the following.

Here, it is assumed that the starting PJ may pass through the same layer as the following transport route H1, or may be transported along the following transport routes H2 to H5. Note that the processing module used in the first project is not limited to the same type of processing module as the processing module used in the transport route H1, and may not pass through some modules or may not pass through some modules, etc. It may be transported to a module whose explanation is omitted.
Transport path H2: Carrier C → CRA layer → MPRA layer → COT layer → IFB layer → IFBS layer → IFBS layer → IFB layer → DEV layer → MPRA layer → CRA layer → Carrier C
Transport path H3: Carrier C → CRA layer → MPRA layer → COT layer → IFB layer → IFB layer → DEV layer → MPRA layer → CRA layer → Carrier C
Transport path H4: Carrier C → CRA layer → MPRA layer → COT layer → MPRA layer → CRA layer → Carrier C
Transport path H5: Carrier C → CRA layer → MPRA layer → DEV layer → MPRA layer → CRA layer → Carrier C

In this way, even if the transport routes are different between the first PJ and the second PJ, the wafer W is placed on standby at the ICPL depending on the bottleneck in the transport route of the wafer W at the later stage of the exposure machine, so the exposure The layer through which the wafer W to be transferred next to the machine D5 is scheduled to pass becomes the layer to be acquired by MUTCT and ACT. Therefore, the layers to be acquired are the IFBS layer, IFB layer, DEV layer, MPRA layer, and CRA layer when the starting PJ is transported on transport routes H1 and H2, and when it is transported on transport route H3, These are the IFB layer, DEV layer, MPRA layer, and CRA layer. When transported by the transport route H4, the layers are the MPRA layer and CRA layer. When transported by the transport route H5, the IFB layer, DEV layer, MPRA layer, and This is the CRA layer.

Even if different flow tolerance settings are made as described above, the MUTCT and ACT of each PJ are acquired from each layer to be calculated, and the post-exposure maximum CT is determined, as described above. Then, the wafer W waits at the ICPL according to the maximum CT after exposure. If this different flow tolerance setting is made, even if there is a starting PJ where the bottleneck is a step that the wafer W of the subsequent PJ does not pass, the subsequent PJ will not be able to overtake the starting PJ and the DEV layer will be This prevents the PED time from being disturbed due to waiting at the entrance or the like.

By the way, the first to fourth conditions for stopping the transport to the exposure machine D5 and the different flow permission settings have been described as matters related to the second transport control, but they also apply to the first transport control. That is, when performing the first transport control, if any of the first to fourth conditions is met, transport of the wafer W to the exposure machine D5 is stopped. Further, in performing the first transfer control, settings can be made such that the wafer W of the subsequent PJ can be transferred to the exposure machine D5 before the end of the first PJ in which the layers and modules to be transferred are different.

[Explanation of third transport control]
Next, the third transport control will be explained. When performing this third transport control, the exposure machine CT is set in advance. In the explanation of the first transport control, it was mentioned that the output interval of the out-ready signal is regarded as the exposure machine CT, but in order to control the PPD time with higher precision, the exposure machine CT should use a pre-prepared setting value. It is preferable to obtain it from exposure machine D5. In the case of acquiring from the exposure machine D5, for example, when starting processing in the coating and developing apparatus 1, the data is acquired via a host computer that controls the control unit 4 of the coating and developing apparatus 1 and the control unit (not shown) of the exposure machine D5. This allows the control unit 4 to acquire the information.

The second transport control described above is executed in a state where the user selects to perform the third transport control. For example, when an arbitrary PJ is transported along the transport path H1, the CT of the DEV layer of the PJ and the exposure machine CT are compared before being carried into the exposure machine D5. Note that the CT of the DEV layer here is the maximum value of the ACT in the DEV layer specified by PJ and the MUTCT obtained from modules other than the entrance and exit, and thereafter the CT of the original DEV layer is used. It is sometimes written as. Note that the original CT of the DEV layer is the time calculated from the circular movement time of PRA34 to 36 and the number of stacks, as described above, and is the circular movement time of PRA set in advance by PJ. This corresponds to the section transport time corresponding to .

As a result of the comparison, if the exposure machine CT is longer (exposure machine CT>DEV layer CT), the exposure machine D5 becomes the transport bottleneck among the exposure machine D5 and the DEV layer in the stage after the ICPL. . In this case, the wafer W of the above PJ is transferred to the DEV layer via the ICPL and the exposure machine D5, and in the DEV layer, the CT of the DEV layer, which is the section transport time, is adjusted to the exposure machine CT. In this state, it is transported toward SCPL3, which is the exit module (FIG. 15). Therefore, the wafer W of the PJ is transported within the DEV layer with a CT longer than the original CT of the DEV layer. More specifically, the PRAs 34 to 36 in the DEV layer are transported in the DEV layer by rotating at a time different from the time predetermined by the PJ. As mentioned above, among the wafers W of the same PJ, at least until the last wafer W to be transported in the DEV layer concerned is transported to the SCPL 3 (that is, until the transport in the DEV layer of the PJ is finished), the DEV The CT of the layer does not change. Depending on the subsequent project, the CT of the DEV layer is maintained as the exposure machine CT.

Note that while the transfer is being performed as described above, since the second transfer control is being executed, the calculation explained in FIG. 14 is performed when transferring the wafer W from the ICPL to the exposure machine D5. W will be placed on standby as appropriate. However, since the exposure machine D5 is the bottleneck of transportation and the output interval of the in-ready signal is relatively long, the tendency is that the maximum CT after exposure < time G1 + time G2 at the time the in-ready signal is output. Therefore, it is difficult for wafers W to be placed on standby at ICPL.

By performing transport control in this manner, all the wafers W of the same PJ are transported within the DEV layer at regular intervals, so that the PPD times of the wafers W of the PJ are the same. Furthermore, since the exposure machine cycle time (that is, the interval at which wafers W are carried out from the exposure machine D5) and the cycle time of the DEV layer are the same, each wafer W is carried to the heating module 1A at regular intervals. The PED times are also the same between wafers W in the same PJ.

On the other hand, as a result of comparing the CT of the DEV layer of the PJ before being carried into the exposure machine D5 and the CT of the exposure machine, if the CT of the exposure machine is longer (if the CT of the exposure machine ≦ the CT of the DEV layer) , the exposure device D5 and the DEV layer, the DEV layer becomes the bottleneck for transportation. In this case, the above-mentioned PJ wafer W is transported to the DEV layer via the ICPL and the exposure machine D5, and then transported to the exit module SCPL3 using the original CT of the DEV layer. (Figure 16). In other words, the CT of the DEV layer is not aligned with the CT of the exposure machine. In this case as well, since the second transfer control is being executed, the wafer W is placed on standby in the ICPL as appropriate based on the calculation described in FIG. 14.

By executing the second transport control as described above, the interval at which the wafers W are carried out from the exposure machine D5 and, furthermore, the interval at which they are carried into the DEV layer is constant or approximately constant. Since the wafers W are sequentially transferred within the DEV layer at regular intervals (original CT of the DEV layer), the PED time and the PPD time are the same between the wafers W in this case as well. Even when wafers W are transported in the CT of the original DEV layer in this way, the last wafer W to be transported in the DEV layer among the wafers W in the same PJ is transported to the module at the exit of the DEV layer. Until then, the CT of the DEV layer remains unchanged.

[Restrictions on loading wafers into exposure equipment]
When the setting is such that the third transfer control is performed, if the first PJ and the second PJ have different flows, the wafer W of the second PJ will not be transferred to the exposure machine D5 until the first PJ is finished, and the first transfer control will be performed. As described in the second transport control, the subsequent PJs are sequentially transported from the ICPL to the exposure machine D5 after the first PJ ends. Therefore, the wafers W transferred to the ICPL by the end of the first PJ wait at the ICPL. This is the same as the reason for preventing the subsequent PJs with different flows from being carried into the exposure machine D5 described in the first transfer control and the second transfer control, and the wafer W of the subsequent PJ is transferred to the exposure machine D5 before the first PJ ends. This is because if this happens, the wafer W of the subsequent PJ may be made to wait at the entrance of the DEV layer, and the PED time may be extended.

Furthermore, even if the CT of the DEV layer is changed between the later PJ and the earlier PJ, the wafer W of the later PJ is not transferred to the exposure machine D5, and the wafer W of the later PJ is not transferred to the exposure machine D5 until the earlier PJ ends. It is not transported to exposure machine D5. This is because since the first wafer W of the first PJ to the last wafer W is transported within the DEV layer in a constant cycle, subsequent PJs whose CT of the DEV layer is different cannot be transported within the DEV layer during that time. .

To give a specific example, it is assumed that the CT of the DEV layer is matched to the exposure machine CT and conveyance is performed in the relationship that exposure machine CT>post-exposure maximum CT for the first PJ. As for the subsequent PJ transported to the ICPL, it is assumed that the CT of the DEV layer>the CT of the exposure machine. That is, alignment is not performed when the DEV layer of the subsequent PJ is transported, and the CT of the DEV layer changes. Therefore, the later PJ is not conveyed to the exposure machine D5 until the end of the first PJ. To give another example, for a starting PJ, the CT of the DEV layer is transported as the original CT, and for a later PJ transported to the ICPL, the CT of the DEV layer is different from the CT of the DEV of the starting PJ. It is assumed that the settings are different. In that case as well, the CT of the DEV layer will change when the DEV layer of the later PJ is conveyed, so the later PJ will not be conveyed to the exposure machine D5 until the end of the first PJ. In this way, when the time of circular movement of PRA 34 to 36 in the DEV layer is changed with respect to the time of conveyance of the first PJ, the conveyance of the second PJ to the exposure machine D5 is stopped.

[Regarding limitations on the number of modules used]
Let us consider a case where all multi-modules of an arbitrary step are used in one stack of the DEV layer. In that case, the wafer W transferred to one of the multi-modules is transferred to the next one of the multi-modules after DEV layer cycles (i.e., PRA rotations) are performed for the number of multi-modules. transported to the module. Therefore, the wafer W stays in the one module for a time equal to the CT of the DEV layer x the number of multi-modules. Specifically, as shown in FIGS. 15 and 16, four heating modules 1A-1 to 1A-4 are provided as the heating module 1A, so the wafer W transferred to the heating module 1A-1 passes through four cycles. Afterwards, it is transported to the next SCPL2. When the CT alignment of the DEV layer described in FIG. 15 and the like is performed, the wafer W stays in the heating module 1A-1 for a time equivalent to 4 cycles of exposure machine CT.

The CT of the DEV layer is extended when viewed from the original CT due to alignment with the exposure machine CT. Therefore, the residence time of the wafer W in each module is also extended, and the PPD time also tends to be extended. In order to suppress this PPD time from increasing, the number of modules used in the multi-module in the DEV layer can be limited when performing this matching. More specifically, it is possible to limit the number of modules in each step except for the inlet and outlet of the DEV layer, and this limit is set so that the number of modules used is the minimum required for conveying the DEV layer with the exposure machine CT. number (assumed to be the number of required modules). In other words, in each step of the DEV layer, the minimum number of modules that can transport one wafer W to the next step in one cycle of the DEV layer is the required number of modules, and the time of one cycle here is the exposure machine It's CT time. Note that the user can select whether or not to limit the number of modules used.

FIG. 17 shows an example in which the DEV layer is transported by limiting the number of modules used in this way, and unused modules are marked with an x. To avoid complicating the explanation, let us first explain how to calculate the number of required modules assuming that the DEV layer is not a multi-stack. If the value contains a decimal value, round the decimal value up to the next integer. For example, assume that the exposure time of the exposure machine CT is 100 seconds. Assume that for any PJ, the MUT of the heating module 1A is calculated to be 90 seconds, the MUT of the SCPL2 is 40 seconds, the MUT of the developing module 15 is 130 seconds, and the MUT of the heating module 1B is calculated to be 90 seconds. In this case, the required number of heating modules 1A is calculated as 1 by rounding up the decimal point of 90 seconds/100 seconds. Using similar calculations, the required numbers of modules for the SCPL 2, the developing module 15, and the heating module 1B are calculated as 1, 2, and 1, respectively.

As mentioned above, this value is based on the assumption that the number of stacks of DEV layers used is one. If the number of multiple stacks of the DEV layer used is 3 as described above, then the required number of modules for each stack may be determined using the transport ratio, for example, similar to Equation 1 for calculating the MUTCT described above. In other words, assuming that the wafers W are transferred equally to each of the three stacks, the required number of developing modules 15 for one stack is determined as 130 seconds/number of multi-stack (=3)/exposure machine CT=1. Bye.

As described above, for the multi-modules of each step, which module is to be used is determined according to the calculated number of required modules. For example, the calculated number of modules are used in ascending order of number. Then, the wafer W of the PJ, which is the basis for calculating the number of required modules, is transported and processed, limited to the modules whose use has been determined in this way. As the number of modules used among the multi-modules is limited in this way, the residence time of the wafer W in the modules used in this way is equal to the exposure machine CT x the number of required modules, so the number of modules is not limited. The wafer W is transferred to the module for the next step more quickly than in the case where the wafer W is transferred to the module for the next step. Therefore, PPD time is shortened.

Note that the required number of modules calculated for the first PJ and the later PJ may be different. To give a specific example, in the heating module 1A, since the processing time is 75 seconds for the first PJ and 100 seconds for the second PJ, the MUT between the first PJ and the second PJ is The required number of modules calculated from the above may differ. If the required number of modules calculated in this way is different, it falls under the condition that the first PJ and the later PJ have different flows as described above, so the later PJ is not transported to the exposure machine D5 until the first PJ is finished. is not performed.

As described above, it is possible to select whether or not to limit the number of modules used. As an example of this selection, even if the PPD time is relatively long, if the effect on the pattern formed on the wafer W is small or has no effect, the subsequent wafer W cannot be transferred to the exposure machine D5 due to a change in the number of required modules. In order to prevent throughput from decreasing due to changes in the number of modules used, the number of modules used is not limited. If a relatively long PPD time has a relatively large effect on the pattern formed on the wafer W, the PPD time may be suppressed by setting a limit on the number of modules used.

[Additional information]
As described above, the first conveyance control, the second conveyance control, and the third conveyance control are performed separately, so of the first to third conveyance controls, only the first conveyance control, or the second conveyance control and The control unit 4 may be configured so that only three transport controls are performed. Note that, regarding the second transport control and the third transport control, only the second transport control may be performed.

It has been described that the exposure machine CT is set when performing the third transport control. Although it has been stated that the output interval of the out-ready signal is regarded as the exposure machine CT when performing the first transport control, if it is possible to execute the first to third transport controls, then in the first transport control , instead of using the output interval of the out-ready signal, the exposure machine CT set for performing the third transport control may be used. Note that in order to control the PPD time with high precision, the exposure machine CT is set as described above in the third transport control, but the setting is not limited to the above-mentioned setting. Similarly to the first transport control, the output interval of the out-ready signal may be used as the exposure machine CT. Furthermore, if wafers W are loaded into and taken out of the exposure machine D5 at appropriate intervals, not only the out-ready signal output interval but also the in-ready signal output interval will be approximately the same as that of the exposure machine CT. The output interval of the in-ready signal may be regarded as the exposure machine CT and used. As described above, the method of acquiring the exposure machine CT is arbitrary.

Although it has been described that the exposure machine D5 and ICPL are made to stand by for the time obtained by performing calculations as described above in the first conveyance control and the second conveyance control, an offset time may be set as appropriate. Therefore, the wafer W can be kept on standby for a time corresponding to the acquired time, and the time according to the acquired time herein includes the acquired time itself.

Note that the substrate processing apparatus is not limited to a coating and developing apparatus. For example, the apparatus may be configured to perform only the processes after exposure and development without performing resist coating. The substrate is not limited to the wafer W, but may also be an FPD (flat panel display) substrate. The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The embodiments described above may be omitted, replaced, modified, and combined in various forms without departing from the scope and spirit of the appended claims.

C Carrier ICPL Temperature adjustment module TRS Transfer module W Wafer 1A Heating module 11 CRA (transport mechanism)
12 MPRA (transport mechanism)
15 Developing module 21 IFB (transport mechanism)
22 IFBS (transport mechanism)
34-36 PRA (transport mechanism)

Claims (12)

comprising a transport mechanism group that transports the substrate taken out from the carrier to the carrier via a module group and an exposure machine,
The module group includes a front module for mounting the substrate at a front stage of the exposure machine;
The exposure machine includes first and second rear-stage modules for mounting the substrate at a rear stage of the exposure machine, a heating module, and a developing module,
The transport mechanism group includes a first transport mechanism that transports the substrate in the order of the front module, the exposure machine, and the first rear module, the first rear module, the heating module, the developing module, and the first rear module. A substrate processing apparatus including: a second transport mechanism that transports the substrate in the order of the second rear module; and one or more rear transport mechanisms that transport the substrate from the second rear module to the carrier. In the board transportation method that
In the transport path on the downstream side of the exposure machine, for each transport section corresponding to each transport mechanism that transports the substrate, obtain the section transport time required to transport the substrate to the next transport section. process and
a loading/unloading step of loading or unloading the substrate into or out of the exposure machine by the first transport mechanism based on the longest maximum section transport time among the section transport times;
A substrate transport method comprising: If the modules that perform the same type of processing on the substrate are multi-modules,
In the step of obtaining the section transport time, a first candidate for the section transport time is obtained according to the residence time of the substrate located in the transport section in each module and the number of modules used in a multi-module. The process of
obtaining a second candidate for the section transport time corresponding to the number of transport steps of the transport mechanism in the transport section;
including;
The substrate transport method according to claim 1, wherein the longest one of the first candidate and the second candidate acquired from each transport section is the maximum section transport time. 3. The substrate transport method according to claim 2, wherein when the substrates of different lots are located in one of the transport sections, the first candidate for the section transport time is acquired for each lot. 3. The substrate transport method according to claim 2, further comprising the step of re-obtaining the maximum section transport time when the number of modules used in the multi-module changes. The loading/unloading process is
3. The substrate transport method according to claim 2, further comprising an unloading step of unloading the substrate from the exposure machine based on an unloading interval at which the substrate can be unloaded in the exposure machine and the maximum section transport time. The unloading process includes:
When the maximum section transport time is longer than the carry-out interval, a time period corresponding to the difference between the carry-out interval of the exposure machine and the maximum section transport time starts from the time when the substrate can be carried out from the exposure machine. a step of waiting the substrate in the exposure machine until the time has passed;
a step of carrying out the substrate from the exposure machine after a time corresponding to the time of the difference has elapsed;
6. The substrate transport method according to claim 5, comprising: The loading/unloading process is
the total time of the time required for transporting the substrate from the front module to the exposure machine and the elapsed time after the transport of the substrate that was transported immediately before to the exposure machine, and the maximum section transport time; a comparison step to compare the
If the maximum section transport time is longer than the total time in the comparison step, then the substrate to be transported to the exposure machine is transferred to the previous module for a time corresponding to the difference between the total time and the maximum section transport time. a step of transporting the substrate to the exposure machine after the substrate is placed on standby;
3. The substrate transport method according to claim 2, comprising: A section conveyance time for conveying the substrate from a conveyance section by the second conveyance mechanism to a conveyance zone by the latter conveyance mechanism, which is set for the substrate scheduled to be conveyed to the exposure machine, and the exposure machine cycle time. a comparison step to compare;
a changing step of changing the section conveyance time according to the result of the comparing step;
The substrate transport method according to claim 7, comprising: When the first lot of the substrates that are first transported to the rear stage of the exposure machine and the second lot of the substrates that are transported next, the transport routes at the rear stage of the exposure machine are different,
4. The substrate transport method according to claim 3, further comprising the step of stopping transport of the second lot to the exposure machine until the last substrate of the first lot is transported to the carrier. When the substrate cannot be transported between one module at the rear stage of the exposure machine and another module at the rear stage of the one module,
2. The substrate transport method according to claim 1, further comprising the step of stopping transport of the substrate to the exposure machine. comprising a transport mechanism group that transports the substrate taken out from the carrier to the carrier via a module group and an exposure machine,
The module group includes a front module for mounting the substrate at a front stage of the exposure machine;
The exposure machine includes first and second rear-stage modules for mounting the substrate at a rear stage of the exposure machine, a heating module, and a developing module,
The transport mechanism group includes a first transport mechanism that transports the substrate in the order of the front module, the exposure machine, and the first rear module, the first rear module, the heating module, the developing module, and the first rear module. A substrate processing apparatus including: a second transport mechanism that transports the substrate in the order of the second rear module; and one or more rear transport mechanisms that transport the substrate from the second rear module toward the carrier;
In the transport path on the downstream side of the exposure machine, for each transport section corresponding to each transport mechanism that transports the substrate, obtain the section transport time required to transport the substrate to the next transport section. step and
a loading/unloading step of carrying the substrate into or out of the exposure machine by the first transport mechanism based on the longest maximum section transport time among the section transport times;
A substrate processing apparatus including a control section that outputs a control signal so that the process is performed. A computer program used in a substrate processing apparatus,
The computer program is characterized in that a group of steps are arranged to execute the substrate transport method according to claim 1.

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